KR20000040316A - Manufacturing method of protective film in semiconductor device - Google Patents
Manufacturing method of protective film in semiconductor device Download PDFInfo
- Publication number
- KR20000040316A KR20000040316A KR1019980055904A KR19980055904A KR20000040316A KR 20000040316 A KR20000040316 A KR 20000040316A KR 1019980055904 A KR1019980055904 A KR 1019980055904A KR 19980055904 A KR19980055904 A KR 19980055904A KR 20000040316 A KR20000040316 A KR 20000040316A
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- Prior art keywords
- protective film
- film
- insulating film
- manufacturing
- semiconductor device
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 반도체 장치의 보호막 제조 방법에 관한 것이다.TECHNICAL FIELD This invention relates to a semiconductor device. Specifically, It is related with the manufacturing method of the protective film of a semiconductor device.
반도체 장치가 고집적화됨에 따라 디자인룰이 감소되어 금속 패턴간의 스페이스도 감소하게 되었다. 그러나 반도체 장치의 제조에 이용되는 막(layer)중 다른 막에 비하여 상대적으로 디자인룰에 민감하지 않은 최종 금속막에 적용되는 패시베이션 공정은 기존의 1.0, 0.5㎛ 디자인룰일때나 더 작은 디자인룰인 0.35㎛인 경우에 동일한 스킴을 적용한다.As semiconductor devices have been highly integrated, design rules have been reduced to reduce the space between metal patterns. However, the passivation process applied to the final metal film, which is relatively insensitive to design rules, compared to other films used in the manufacture of semiconductor devices, is 0.35, which is smaller than the conventional 1.0, 0.5㎛ design rule, or 0.35, which is a smaller design rule. The same scheme applies in the case of μm.
그러나, 최근 디자인룰이 더욱 감소된 0.25㎛의 반도체 장치에 기존의 패시베이션 공정을 적용한 결과, 금속 패턴이 끝나는 부위에 디펙이 발생되었다. 즉, 패시베이션 공정시 금속 패턴 상부에서 패시베이션막이 거의 붙은 형태로 되므로, 금속 패턴간에 보이드가 형성된다. 이처럼 보이드가 형성된 상태에서 패드 형성을 위한 감광막을 코팅하게 되면 상기 금속 패턴이 끝나는 부위에서 상기 감광막이 보이드 내부로 빨려 들어가게 되어 감광막의 두께가 낮아지게 되고, 그 결과 후속의 식각공정에서 패시베이션막이 식각됨으로써 디펙이 발생하게 된다.However, as a result of applying a conventional passivation process to a semiconductor device having a thickness of 0.25 μm, which has been further reduced in recent design rules, defects are generated at the end portions of the metal patterns. That is, during the passivation process, since the passivation film is almost attached to the upper portion of the metal pattern, voids are formed between the metal patterns. As such, when the photosensitive film is coated for pad formation in the voids, the photoresist film is sucked into the void at the end of the metal pattern, and the thickness of the photoresist film is lowered. As a result, the passivation film is etched in a subsequent etching process. Defect will occur.
따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 반도체 장치의 보호막 제조 방법을 제공하는데 있다.It is therefore an object of the present invention to provide a method for manufacturing a protective film for a semiconductor device which can solve the above-mentioned conventional problems.
본 발명의 다른 목적은, 사진공정시 보호막이 손상되는 것을 방지하기 위한 반도체 장치의 보호막 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a protective film of a semiconductor device for preventing the protective film from being damaged during a photographic process.
본 발명의 또 다른 목적은, 반도체 장치의 디자인룰이 감소됨에 따라 보호막에 발생되는 디펙을 억제시키기 위한 반도체 장치의 보호막 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a protective film of a semiconductor device for suppressing defects generated in the protective film as the design rule of the semiconductor device is reduced.
상기 목적들을 달성하기 위해서 본 발명에서는, 반도체 기판 최상부에 복수개의 금속 패턴이 형성되어 있는 반도체 장치의 보호막 제조 방법에 있어서: 상기 복수개의 금속 패턴이 형성되어 있는 반도체 기판 상부에 스텝 커버리지가 우수한 제1절연막을 증착하는 단계와; 상기 제1절연막 상에 제2절연막을 증착한 뒤, 상기 제2절연막 상에 상기 복수개의 금속 패턴간에 존재하는 보이드를 제거하기 위하여 스텝 커버리지가 양호한 제3절연막을 증착하는 단계를 포함함을 특징으로 하는 반도체 장치의 보호막 제조 방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above objects, in the present invention, a method of manufacturing a protective film for a semiconductor device in which a plurality of metal patterns are formed on a top of a semiconductor substrate is provided. Depositing an insulating film; After depositing a second insulating film on the first insulating film, and depositing a third insulating film having good step coverage on the second insulating film to remove voids existing between the plurality of metal patterns. A protective film manufacturing method of a semiconductor device is provided.
도 1a 내지 도 1c는 본 발명의 바람직한 실시예에 따른 보호막 제조 공정을 설명하기 위한 단면도들1A to 1C are cross-sectional views illustrating a protective film manufacturing process according to a preferred embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 장치의 보호막 제조 방법을 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a protective film of a semiconductor device according to an embodiment of the present invention.
먼저, 도 1a를 참조하면, 반도체 장치를 구성하는 각종 패턴들(예컨대, 트랜지스터, 캐패시터, 비트라인 및 워드라인등)이 형성되어 있는 반도체 기판(100) 상부에 전원전압을 인가받기 위한 금속 패턴(102)들을 형성한다. 이어서, 이러한 금속 패턴(102)이 형성되어 있는 반도체 기판(100)을 외부의 영향으로부터 보호하기 위해 패시베이션 공정을 통해 1차적으로 스텝 커버리지가 우수한 P-TEOS 산화막(104)을 약 4000Å 두께로 증착한다.First, referring to FIG. 1A, a metal pattern for applying a power voltage to an upper portion of a semiconductor substrate 100 on which various patterns (eg, transistors, capacitors, bit lines, word lines, etc.) forming a semiconductor device are formed ( 102). Subsequently, in order to protect the semiconductor substrate 100 on which the metal pattern 102 is formed, the P-TEOS oxide film 104 having excellent step coverage is deposited to a thickness of about 4000 kPa through a passivation process. .
이어서, 도 1b를 참조하면, 상기 P-TEOS 산화막(104) 상부에 질화실리콘막(106)을 약 6000Å 두께로 증착한다. 이때, 상기 P-TEOS 산화막(104) 및 P-SiN막(106)이 증착되는 과정에서 상기 금속 패턴(102)간의 간격으로 인해 보이드등이 발생할 경우에는 상기 P-SiN막(106)을 더 두껍게 증착하여 상기 보이드를 제거할 수도 있다. 그러나, 이처럼 P-SiN막(106)을 두껍게 증착하게 되면, 후속의 리던던시를 위한 퓨즈 커팅시나 본딩 패드를 오픈하기 위한 식각공정시에 상기 P-SiN막(106)이 완전히 식각되지 못하게 되는 문제가 발생된다.Subsequently, referring to FIG. 1B, a silicon nitride film 106 is deposited on the P-TEOS oxide film 104 to a thickness of about 6000 Å. At this time, in the process of depositing the P-TEOS oxide film 104 and the P-SiN film 106, if a void or the like occurs due to the gap between the metal patterns 102, the P-SiN film 106 is made thicker. The voids may be removed by vapor deposition. However, if the P-SiN film 106 is thickly deposited, the P-SiN film 106 may not be completely etched during the fuse cutting for the subsequent redundancy or the etching process for opening the bonding pad. Is generated.
따라서, 하기 도 1c에 도시되어 있는 것과 같이, P-TEOS 산화막(108)을 약 1000Å 더 증착한다. 그 결과, 상기 보이드에 P-TEOS 산화막(108)이 채워져 보이드가 제거되거나, 도 1c에 도시되어 있는 것과 같이 상기 보이드의 상부가 막히게 되어 전체적으로 보호막의 스텝 커버리지가 양호해 진다.Thus, as shown in FIG. 1C, a P-TEOS oxide film 108 is further deposited by about 1000 microseconds. As a result, the voids are filled with the P-TEOS oxide film 108 to remove the voids, or the upper portions of the voids are blocked as shown in FIG. 1C, so that the overall step coverage of the protective film is improved.
상기한 바와 같이 본 발명에 따른 패시베이션 공정에서는, 금속 패턴간의 간격으로 인하여 보이드가 발생할 경우에, 스텝 커버리지가 우수한 P-TEOS 산화막을 증착한다. 그 결과, 보이드가 막히게 되어 후속의 사진 공정시 보호막이 손상되는 문제점을 방지할 수 있으며, 후속의 리던던시를 위한 퓨즈 커팅시나 본딩 패드를 오픈하기 위한 식각공정이 용이해지는 장점이 있다.As described above, in the passivation process according to the present invention, when voids occur due to the spacing between metal patterns, a P-TEOS oxide film having excellent step coverage is deposited. As a result, the voids may be blocked to prevent a problem that the protective film is damaged during a subsequent photo process, and an etching process for opening a bonding pad or cutting a fuse for subsequent redundancy may be facilitated.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980055904A KR20000040316A (en) | 1998-12-17 | 1998-12-17 | Manufacturing method of protective film in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980055904A KR20000040316A (en) | 1998-12-17 | 1998-12-17 | Manufacturing method of protective film in semiconductor device |
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| Publication Number | Publication Date |
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| KR20000040316A true KR20000040316A (en) | 2000-07-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019980055904A KR20000040316A (en) | 1998-12-17 | 1998-12-17 | Manufacturing method of protective film in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
-
1998
- 1998-12-17 KR KR1019980055904A patent/KR20000040316A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100355867B1 (en) * | 1999-12-31 | 2002-10-12 | 아남반도체 주식회사 | a manufacturing method of a semiconductor device |
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