JPH09199582A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH09199582A JPH09199582A JP447096A JP447096A JPH09199582A JP H09199582 A JPH09199582 A JP H09199582A JP 447096 A JP447096 A JP 447096A JP 447096 A JP447096 A JP 447096A JP H09199582 A JPH09199582 A JP H09199582A
- Authority
- JP
- Japan
- Prior art keywords
- film
- coated
- insulating film
- trench
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特に素子間を絶縁分離するトレンチを有す
る半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a trench for insulatingly separating elements.
【０００２】[0002]
【従来の技術】従来の半導体装置のトレンチの埋設方法
(以下“従来法”という)について、図５及び図６を参照
して説明する。なお、図５は、工程Ａ〜工程Ｂからなる
従来法の工程順断面図であり、図６は、図５工程Ｂに続
く工程Ｃ〜工程Ｄからなる工程順断面図である。2. Description of the Related Art A conventional method for burying a trench in a semiconductor device
(Hereinafter, referred to as "conventional method") will be described with reference to FIGS. 5 is a process sequence cross-sectional view of a conventional method including process A to process B, and FIG. 6 is a process sequence cross-sectional view including process C to process D following process B of FIG.
【０００３】従来法は、まず図５工程Ａに示すように、
半導体基板31に、素子領域を電気的に絶縁分離するため
にトレンチ32を開口し、表面を薄く酸化して膜厚500Å
の二酸化シリコン膜33を形成した後、ＬＰＣＶＤ法にて
膜厚1200Åの窒化シリコン膜34を形成する。In the conventional method, as shown in FIG.
A trench 32 is opened in the semiconductor substrate 31 to electrically isolate the element region, and the surface is thinly oxidized to a film thickness of 500 Å
After the silicon dioxide film 33 is formed, a silicon nitride film 34 having a film thickness of 1200 Å is formed by the LPCVD method.
【０００４】次に、同じく工程Ａに示すように、ＬＰＣ
ＶＤ法によってテトラエトキシシラン(以下“TEOS”と
略記する))を原料とし、ホウ素及びリンを含んだガラス
膜(以下“TEOS−BPSG膜”と略記する)35を膜厚15,000Å
形成してトレンチを完全に埋設し、続いて、温度1000℃
で窒素と酸素の混合気体雰囲気中で熱処理を行う。Next, as also shown in step A, LPC
By the VD method, tetraethoxysilane (hereinafter abbreviated as “TEOS”) is used as a raw material, and a glass film containing boron and phosphorus (hereinafter abbreviated as “TEOS-BPSG film”) 35 having a film thickness of 15,000Å
Form and completely fill the trench, then temperature 1000 ° C
The heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen.
【０００５】次に、図５工程Ｂに示すように、トレンチ
部以外の領域に形成されたTEOS−BPSG膜35を、バッファ
−ド弗酸を用いた等方性ウエットエッチングによって除
去する。このとき、エッチング後のトレンチ部の段差が
大きくなりすぎないようにする必要がある。その後、図
６工程Ｃに示すように、トレンチ部の段差を平坦化する
ため、塗布・焼成法によるリンを含んだガラス膜(以下
“塗布PSG膜”と略記する)38を形成する。Next, as shown in FIG. 5B, the TEOS-BPSG film 35 formed in the region other than the trench portion is removed by isotropic wet etching using buffered hydrofluoric acid. At this time, it is necessary to prevent the step of the trench portion after etching from becoming too large. Thereafter, as shown in Step C of FIG. 6, a glass film containing phosphorus (hereinafter abbreviated as “coated PSG film”) 38 is formed by a coating / baking method in order to flatten the steps in the trench portion.
【０００６】最後に、図６工程Ｄに示すように、トレン
チ部以外の領域に形成された塗布PSG膜38及び窒化シリ
コン膜34を、それぞれバッファ−ド弗酸及び熱リン酸を
用いた等方性ウエットエッチングによって除去する。Finally, as shown in FIG. 6D, the coated PSG film 38 and the silicon nitride film 34 formed in the regions other than the trench portion are isotropically formed using buffered hydrofluoric acid and hot phosphoric acid, respectively. By wet wet etching.
【０００７】[0007]
【発明が解決しようとする課題】上記従来法では、TEOS
−BPSG膜35をエッチングした後(図５工程Ｂの段階)のト
レンチ部の段差が4,000Åを越えると、その後の塗布PSG
膜38を形成するときに(図６工程Ｃの段階)クラックが発
生しやすくなる。In the above conventional method, the TEOS
-After etching the BPSG film 35 (step B in Fig. 5), if the step difference in the trench exceeds 4,000 Å, the subsequent coating PSG
When the film 38 is formed (step C in FIG. 6), cracks are likely to occur.
【０００８】この塗布PSG膜38にクラック39が発生した
例を図７(Ａ)に示す。一旦クラック39が発生すると、そ
の後バッファ−ド弗酸によってトレンチ部以外の領域に
ある塗布PSG膜38を除去する際(図６工程Ｄの段階)、ク
ラック39の部分も同時にエッチングされ、このため、ク
ラック39の幅が大きく増幅されるようになる。An example in which a crack 39 is generated in the coated PSG film 38 is shown in FIG. 7 (A). Once the crack 39 is generated, when the coated PSG film 38 in the region other than the trench portion is removed by the buffered hydrofluoric acid (step D in FIG. 6), the crack 39 is also etched at the same time. The width of the crack 39 is greatly amplified.
【０００９】さらに直下にあるTEOS−BPSG膜35の一部も
エッチングされてしまうので［図７(Ｂ)（塗布PSG膜を
エッチングした後の図）参照］、クラック39が発生した
部分に大きな段差ができてしまう。そのため、後工程で
ポリシリコンで抵抗などを形成する際、この段差部でポ
リシリコンのエッチング残りによるショ−ト不良が発生
しやすくなる。Further, a portion of the TEOS-BPSG film 35 immediately below is also etched [see FIG. 7 (B) (FIG. 7B after etching the coated PSG film)]. Will be created. Therefore, when a resistor or the like is formed of polysilicon in a later step, short-circuiting is likely to occur at the step portion due to etching residue of polysilicon.
【００１０】そこで、クラック39が発生した場合、塗布
PSG膜38の除去・再形成が必要になるが、塗布PSG膜38の
直下にTEOS−BPSG膜35があるため(図７参照)、塗布PSG
膜38のみを除去しようとしても、どうしてもその下にあ
るTEOS−BPSG膜35までエッチングされてしまう。そのた
め、エッチング後のトレンチの段差がより大きくなって
しまい、再度塗布PSG膜を形成すると、段差部にたまるP
SGの量が多くなって、より一層クラックが発生する危険
性が高くなってしまうという問題が生じ、実質的に塗布
PSG膜の再形成は困難であった。Therefore, if cracks 39 occur, coating
It is necessary to remove and re-form the PSG film 38, but since the TEOS-BPSG film 35 is immediately below the coated PSG film 38 (see FIG. 7), the coated PSG film 38
Even if only the film 38 is to be removed, the TEOS-BPSG film 35 thereunder is inevitably etched. Therefore, the step difference of the trench after etching becomes larger, and when the coated PSG film is formed again, the P stepped portion will accumulate.
The problem that the amount of SG increases and the risk of cracks becoming even higher occurs
It was difficult to reform the PSG film.
【００１１】本発明は、上記問題点に鑑み成されたもの
であって、その目的(課題)とするところは、塗布絶縁膜
にクラックが発生しても、容易に塗布絶縁膜のみを除去
して再度塗布絶縁膜を形成することができる半導体装置
の製造方法を提供することにある。The present invention has been made in view of the above problems, and its object (problem) is to easily remove only the coating insulating film even if a crack occurs in the coating insulating film. Another object of the present invention is to provide a method for manufacturing a semiconductor device in which a coated insulating film can be formed again.
【００１２】[0012]
【課題を解決するための手段】本発明は、塗布絶縁膜の
下にエッチング速度がはるかに小さい絶縁膜を形成する
ことを特徴とし、これにより上記目的とする“塗布絶縁
膜にクラックが発生しても、容易に塗布絶縁膜のみを除
去して再度塗布絶縁膜を形成することができる”という
半導体装置の製造方法を提供するものである。The present invention is characterized in that an insulating film having a much lower etching rate is formed under the coated insulating film, which causes cracks to occur in the above-mentioned "coated insulating film." Even so, it is possible to easily remove only the coating insulating film and form the coating insulating film again ”.
【００１３】即ち、本発明に係る半導体装置の製造方法
は、「素子間を絶縁分離するトレンチを有する半導体装
置の製造方法において、(1) トレンチを埋設するために
リン及び／又はホウ素を含む第１の絶縁膜を形成する工
程、(2) トレンチ部以外の領域に形成された前記第１の
絶縁膜を除去する工程、(3) 全面に第２の絶縁膜を形成
する工程、(4) 更に全面に塗布絶縁膜を形成する工程、
(5) トレンチ部以外の領域に形成された前記塗布絶縁膜
及び前記第２の絶縁膜を除去する工程、を含み、前記第
２の絶縁膜はエッチング速度が前記塗布絶縁膜のそれよ
りはるかに小さいものであり、前記塗布絶縁膜にクラッ
クが発生した場合に容易に該塗布絶縁膜のみを除去でき
ることを特徴とする半導体装置の製造方法。」(請求項
１)を要旨とする。That is, the method of manufacturing a semiconductor device according to the present invention includes: (1) In a method of manufacturing a semiconductor device having a trench for insulating and isolating elements from each other, (1) a phosphor containing boron and / or boron to fill the trench; Forming the first insulating film, (2) removing the first insulating film formed in a region other than the trench portion, (3) forming a second insulating film on the entire surface, (4) Further, a step of forming a coating insulating film on the entire surface,
(5) a step of removing the coating insulating film and the second insulating film formed in a region other than the trench portion, wherein the second insulating film has an etching rate far higher than that of the coating insulating film. A method of manufacturing a semiconductor device, which is small and is capable of easily removing only the coating insulating film when a crack occurs in the coating insulating film. (Claim 1).
【００１４】[0014]
【発明の実施の形態】本発明に係る半導体装置の製造方
法において、前記(3)の“第２の絶縁膜を形成する工
程”として、単層の第２の絶縁膜を形成する以外に多層
構造の膜を形成することもできる(請求項２)。本発明
は、上記単層又は多層構造の膜からなる第２の絶縁膜と
して、エッチング速度が塗布絶縁膜のそれよりはるかに
小さいものとすることにより、塗布絶縁膜にクラックが
発生しても、容易に塗布絶縁膜のみを除去し、塗布絶縁
膜を再度形成することが可能となる作用が生じるもので
ある。BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a semiconductor device according to the present invention, as the step (3) “forming a second insulating film”, a single layer second insulating film is formed It is also possible to form a film having a structure (claim 2). According to the present invention, the second insulating film formed of the single-layer or multi-layered film has an etching rate much lower than that of the coated insulating film, so that even if a crack occurs in the coated insulating film, This brings about the effect that it is possible to easily remove only the coating insulating film and form the coating insulating film again.
【００１５】[0015]
【実施例】次に、本発明の実施例について、図面を参照
して詳細に説明するが、本発明は、以下の実施例にのみ
限定されるものではなく、前記した本発明の要旨を逸脱
しない限り種々の変形、変更が可能である。EXAMPLES Examples of the present invention will now be described in detail with reference to the drawings, but the present invention is not limited to the following examples, and deviates from the gist of the present invention. Unless otherwise, various modifications and changes are possible.
【００１６】（実施例１）図１及び図２は、本発明に係
る半導体装置の製造方法の一実施例(実施例１)を示す図
であり、そのうち図１は、工程Ａ〜工程Ｂからなる製造
工程順縦断面図であり、図２は、図１工程Ｂに続く工程
Ｃ〜工程Ｄからなる製造工程順縦断面図である。(Embodiment 1) FIGS. 1 and 2 are views showing an embodiment (Embodiment 1) of a method for manufacturing a semiconductor device according to the present invention, in which FIG. 2 is a vertical cross-sectional view in the order of manufacturing steps, and FIG. 2 is a vertical cross-sectional view in the order of manufacturing steps including steps C to D following step B in FIG. 1.
【００１７】本実施例１では、まず図１工程Ａに示すよ
うに、半導体基板11に、素子領域を電気的に絶縁分離す
るためにトレンチ12を開口し、表面を薄く酸化して膜厚
500Åの二酸化シリコン膜13を形成した後、ＬＰＣＶＤ
法にて膜厚1200Åの第１の窒化シリコン膜14を形成す
る。In the first embodiment, first, as shown in FIG. 1A, the semiconductor substrate 11 is provided with a trench 12 for electrically insulating and isolating the element region, and the surface is thinly oxidized to form a film thickness.
LPCVD after forming 500 Å silicon dioxide film 13
The first silicon nitride film 14 having a film thickness of 1200 Å is formed by the method.
【００１８】次に、同じく図１工程Ａに示すように、Ｌ
ＰＣＶＤ法にて膜厚15,000ÅのTEOS−BPSG膜15を形成し
てトレンチを完全に埋設した後、温度1000℃で窒素と酸
素の混合気体雰囲気中で熱処理を行う。続いて、トレン
チ部以外の領域に形成されたTEOS−BPSG膜15をバッファ
−ド弗酸を用いた等方性ウエットエッチングによって除
去する。このとき、エッチング後のトレンチ部の段差が
4000Åを越えないようにエッチング時間を調整する。Next, as shown in step A of FIG.
After the TEOS-BPSG film 15 having a film thickness of 15,000Å is formed by the PCVD method to completely bury the trench, heat treatment is performed at a temperature of 1000 ° C. in a mixed gas atmosphere of nitrogen and oxygen. Then, the TEOS-BPSG film 15 formed in the region other than the trench portion is removed by isotropic wet etching using buffered hydrofluoric acid. At this time, the step of the trench portion after etching
Adjust the etching time so that it does not exceed 4000Å.
【００１９】次に、図１工程Ｂに示すように、ＬＰＣＶ
Ｄ法にて膜厚1200Åの第２の窒化シリコン膜17を形成
し、その後、図２工程Ｃに示すように、トレンチ部の段
差を平坦化するため塗布PSG膜18を形成する。Next, as shown in FIG. 1B, LPCV
A second silicon nitride film 17 having a film thickness of 1200 Å is formed by the D method, and then a coated PSG film 18 is formed in order to flatten the steps in the trench portion, as shown in step C of FIG.
【００２０】最後に、図２工程Ｄに示すように、四弗化
炭素(CF4)と酸素(O2)を用いた異方性ドライエッチング
によって、塗布PSG膜18、上層の第２の窒化シリコン膜1
7、下層の第１の窒化シリコン膜14の順にエッチバック
を行う。Finally, as shown in FIG. 2D, anisotropic dry etching using carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) is performed to form the coated PSG film 18 and a second nitriding film as an upper layer. Silicon film 1
7. Etch back is performed in the order of the lower first silicon nitride film 14.
【００２１】ここで、本実施例１による作用効果につい
て、図３を参照して説明する。なお、図３は、実施例１
による作用効果を説明する図であって、そのうち(Ａ)
は、塗布PSG膜にクラックが発生した場合を示す図であ
り、(Ｂ)は塗布PSG膜を除去した後の図である。Now, the operation and effect of the first embodiment will be described with reference to FIG. In addition, FIG.
It is a figure explaining the operation effect by, of which (A)
FIG. 4B is a diagram showing a case where a crack has occurred in the coated PSG film, and FIG. 6B is a diagram after removing the coated PSG film.
【００２２】この実施例１において、塗布PSG膜18とTEO
S−BPSG膜15との間に第２の窒化シリコン膜17が存在す
るが、この第２の窒化シリコン膜17のバッファ−ド弗酸
に対するエッチング速度は、塗布PSG膜18のエッチング
速度に比べると非常に小さいため、図３(Ａ)に示すよう
に、仮に塗布PSG膜18にクラック19が生じても、バッフ
ァ−ド弗酸にてこの塗布PSG膜18のみを除去することが
可能である［図３(Ｂ)参照］。従って、この段階から前
掲の図２工程Ｃにより再度塗布PSG膜18を形成すること
が可能である。In this Example 1, the coated PSG film 18 and TEO
The second silicon nitride film 17 exists between the S-BPSG film 15 and the etching rate of the second silicon nitride film 17 for buffered hydrofluoric acid is higher than that of the coated PSG film 18. Since it is very small, as shown in FIG. 3 (A), even if cracks 19 occur in the coated PSG film 18, it is possible to remove only the coated PSG film 18 with buffered hydrofluoric acid [ See FIG. 3B]. Therefore, from this stage, the coated PSG film 18 can be formed again by the above-mentioned step C in FIG.
【００２３】さらに、TEOS−BPSG膜15上に第２の窒化シ
リコン膜17を形成することにより、段差部に塗布PSG膜1
8のたまる量が少なくなるので、クラックの発生を低減
することができる。Further, by forming the second silicon nitride film 17 on the TEOS-BPSG film 15, the PSG film 1 coated on the step portion is formed.
Since the amount of accumulation of 8 is reduced, the occurrence of cracks can be reduced.
【００２４】（実施例２）図４は、本発明に係る半導体
装置の製造方法の他の実施例(実施例２)を示す工程Ａ〜
工程Ｃからなる製造工程順縦断面図である。(Embodiment 2) FIGS. 4A to 4C show steps A to 5 showing another embodiment (Embodiment 2) of the method for manufacturing a semiconductor device according to the present invention.
It is a manufacturing-process order longitudinal cross-sectional view which consists of process C.
【００２５】本実施例２では、まず図４工程Ａに示すよ
うに、半導体基板21にトレンチ22を開口し、二酸化シリ
コン膜23，第１の窒化シリコン膜24，TEOS−BPSG膜25を
形成した後、トレンチ部以外の領域にあるTEOS−BPSG膜
25をバッファ−ド弗酸を用いて除去する。次に、同じく
図４工程Ａに示すように、常圧ＣＶＤ法にて膜圧4000〜
5000Åの第２の二酸化シリコン膜26を形成し、続いて、
ＬＰＣＶＤ法にて膜圧1000Åの第２の窒化シリコン膜27
を形成する。In the second embodiment, first, as shown in FIG. 4A, a trench 22 is opened in a semiconductor substrate 21, and a silicon dioxide film 23, a first silicon nitride film 24, and a TEOS-BPSG film 25 are formed. After that, the TEOS-BPSG film in the area other than the trench part
25 is removed using buffered hydrofluoric acid. Next, as shown in FIG.
The second silicon dioxide film 26 of 5000 Å is formed, and then,
The second silicon nitride film 27 with a film pressure of 1000Å by the LPCVD method.
To form
【００２６】その後、図４工程Ｂに示すように、トレン
チ部の段差を平坦化するため塗布PSG膜28を形成する。
最後に、図４工程Ｃに示すように、四弗化炭素(CF4)と
酸素(O2)を用いた異方性ドライエッチングによって、塗
布PSG膜28，第２の窒化シリコン膜27，第２の二酸化シ
リコン膜26，第１の窒化シリコン膜24の順にエッチバッ
クを行う。After that, as shown in FIG. 4B, a coated PSG film 28 is formed in order to flatten the steps in the trench portion.
Finally, as shown in Step C of FIG. 4, the coated PSG film 28, the second silicon nitride film 27, and the second silicon nitride film 27 are formed by anisotropic dry etching using carbon tetrafluoride (CF 4 ) and oxygen (O 2 ). The second silicon dioxide film 26 and the first silicon nitride film 24 are etched back in this order.
【００２７】この実施例２においては、塗布PSG膜28とT
EOS−BPSG膜25との間に存在する絶縁膜は、第２の窒化
シリコン膜27と第２の二酸化シリコン膜26との二層構造
になっているが、塗布PSG膜28に接している方の絶縁膜
は第２の窒化シリコン膜27であるため、塗布PSG膜28に
クラックが発生しても、容易にこの塗布PSG膜28を除去
することができ、再形成させることができる。さらに、
二層構造の絶縁膜全体の膜圧を厚くすることで、段差部
の領域が狭くなり、塗布PSG膜28がたまり難くなり、表
面をより平坦にすることができる(図４工程Ｃ参照)。In the second embodiment, the coated PSG film 28 and T
The insulating film existing between the EOS-BPSG film 25 has a two-layer structure of the second silicon nitride film 27 and the second silicon dioxide film 26, but is in contact with the coated PSG film 28. Since the insulating film is the second silicon nitride film 27, even if a crack occurs in the coated PSG film 28, the coated PSG film 28 can be easily removed and reformed. further,
By increasing the film thickness of the entire insulating film having a two-layer structure, the area of the step portion is narrowed, the coated PSG film 28 is less likely to accumulate, and the surface can be made more flat (see step C in FIG. 4).
【００２８】[0028]
【発明の効果】本発明は、以上詳記したとおり、塗布絶
縁膜の下にエッチング速度がはるかに小さい絶縁膜を形
成することを特徴とし、これにより、仮に塗布絶縁膜に
クラックが発生しても、容易に塗布絶縁膜のみを除去し
て再度塗布絶縁膜を形成することができるという効果を
有する。As described in detail above, the present invention is characterized in that an insulating film having a much lower etching rate is formed under the coated insulating film, which may cause cracks in the coated insulating film. Also, there is an effect that only the coating insulating film can be easily removed and the coating insulating film can be formed again.
【図１】本発明に係る半導体装置の製造方法の一実施例
(実施例１)を示す工程Ａ〜工程Ｂからなる製造工程順縦
断面図。FIG. 1 is an embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIG. 6 is a vertical cross-sectional view in order of the manufacturing steps, which includes Step A and Step B showing (Example 1).
【図２】図１工程Ｂに続く工程Ｃ〜工程Ｄからなる製造
工程順縦断面図。2 is a longitudinal cross-sectional view in the order of manufacturing steps, which includes steps C to D following step B in FIG. 1;
【図３】実施例１による作用効果を説明する図であっ
て、そのうち(Ａ)は、塗布PSG膜にクラックが発生した
場合を示す図であり、(Ｂ)は塗布PSG膜を除去した後の
図。3A and 3B are diagrams illustrating the operation and effect of Example 1, wherein FIG. 3A is a diagram showing a case where cracks occur in the coated PSG film, and FIG. 3B is a diagram after removing the coated PSG film. Illustration.
【図４】本発明に係る半導体装置の製造方法の他の実施
例(実施例２)を示す工程Ａ〜工程Ｃからなる製造工程順
縦断面図。FIG. 4 is a longitudinal cross-sectional view in order of the manufacturing steps, which includes steps A to C showing another embodiment (Example 2) of the method for manufacturing the semiconductor device according to the invention.
【図５】従来の半導体装置のトレンチの埋設方法につい
て説明する図であって、工程Ａ〜工程Ｂからなる工程順
縦断面図。FIG. 5 is a view for explaining a conventional method for burying a trench in a semiconductor device, which is a vertical cross-sectional view in order of steps A to B.
【図６】図５工程Ｂに続く工程Ｃ〜工程Ｄからなる工程
順縦断面図。6A to 6C are vertical cross-sectional views in order of the processes including process C to process D following process B in FIG. 5;
【図７】従来法による問題点を説明する図であって、
(Ａ)は塗布PSG膜にクラックが発生した例を示す図であ
り、(Ｂ)は塗布PSG膜をエッチングした後の図。FIG. 7 is a diagram illustrating a problem with the conventional method,
(A) is a figure which shows the example which the crack generate | occur | produced in the coating PSG film, (B) is a figure after etching the coating PSG film.
１１，２１，３１ 半導体基板 １２，２２，３２ トレンチ １３，２３，３３ 二酸化シリコン膜 １４，２４， − 第１の窒化シリコン膜 − ， − ，３４ 窒化シリコン膜 １５，２５，３５ ＴＥＯＳ−ＢＰＳＧ膜 − ，２６， − 第２の二酸化シリコン膜 １７，２７， − 第２の窒化シリコン膜 １８，２８，３８ 塗布ＰＳＧ膜 １９， − ，３９ クラック 11, 21, 31 Semiconductor substrate 12, 22, 32 Trench 13, 23, 33 Silicon dioxide film 14, 24, -First silicon nitride film-,-, 34 Silicon nitride film 15, 25, 35 TEOS-BPSG film- , 26, -Second silicon dioxide film 17,27, -Second silicon nitride film 18,28,38 Coated PSG film 19,-, 39 Crack
Claims (2)
半導体装置の製造方法において、(1) トレンチを埋設す
るためにリン及び／又はホウ素を含む第１の絶縁膜を形
成する工程、(2) トレンチ部以外の領域に形成された前
記第１の絶縁膜を除去する工程、(3) 全面に第２の絶縁
膜を形成する工程、(4) 更に全面に塗布絶縁膜を形成す
る工程、(5) トレンチ部以外の領域に形成された前記塗
布絶縁膜及び前記第２の絶縁膜を除去する工程、を含
み、前記第２の絶縁膜はエッチング速度が前記塗布絶縁
膜のそれよりはるかに小さいものであり、前記塗布絶縁
膜にクラックが発生した場合に容易に該塗布絶縁膜のみ
を除去できることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device having a trench for insulatingly separating elements from each other, (1) a step of forming a first insulating film containing phosphorus and / or boron to fill the trench, (2) A step of removing the first insulating film formed in a region other than the trench portion, (3) a step of forming a second insulating film on the entire surface, (4) a step of further forming a coating insulating film on the entire surface, 5) A step of removing the coating insulating film and the second insulating film formed in a region other than the trench portion, wherein the etching rate of the second insulating film is much smaller than that of the coating insulating film. A method of manufacturing a semiconductor device, characterized in that when a crack occurs in the coated insulating film, only the coated insulating film can be easily removed.
ことを特徴とする請求項１に記載の半導体装置の製造方
法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a film having a multilayer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8004470A JP3039350B2 (en) | 1996-01-16 | 1996-01-16 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8004470A JP3039350B2 (en) | 1996-01-16 | 1996-01-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09199582A true JPH09199582A (en) | 1997-07-31 |
| JP3039350B2 JP3039350B2 (en) | 2000-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8004470A Expired - Fee Related JP3039350B2 (en) | 1996-01-16 | 1996-01-16 | Method for manufacturing semiconductor device |
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| Country | Link |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100300871B1 (en) * | 1998-06-29 | 2001-10-19 | 박종섭 | Method of forming gate oxide in semiconductor memory device |
| KR100312943B1 (en) * | 1999-03-18 | 2001-11-03 | 김영환 | A semiconductor device and fabricating method thereof |
| KR100332521B1 (en) * | 1997-12-24 | 2002-06-20 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor integrated circuit and method for manufacturing the same and semiconductor device and method for manufacturing the same |
| JP2004527916A (en) * | 2001-05-24 | 2004-09-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Structure and method for retaining STI during etching |
-
1996
- 1996-01-16 JP JP8004470A patent/JP3039350B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100332521B1 (en) * | 1997-12-24 | 2002-06-20 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor integrated circuit and method for manufacturing the same and semiconductor device and method for manufacturing the same |
| KR100300871B1 (en) * | 1998-06-29 | 2001-10-19 | 박종섭 | Method of forming gate oxide in semiconductor memory device |
| KR100312943B1 (en) * | 1999-03-18 | 2001-11-03 | 김영환 | A semiconductor device and fabricating method thereof |
| JP2004527916A (en) * | 2001-05-24 | 2004-09-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Structure and method for retaining STI during etching |
| JP2009094547A (en) * | 2001-05-24 | 2009-04-30 | Internatl Business Mach Corp <Ibm> | Structure and method of preserving sti during etching |
| JP2010192919A (en) * | 2001-05-24 | 2010-09-02 | Internatl Business Mach Corp <Ibm> | Method for protecting semiconductor shallow trench isolation (sti) oxide from etching |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3039350B2 (en) | 2000-05-08 |
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