JP2994128B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a MOS device having a so-called LDD structure in which a diffusion region is formed on a silicon substrate using a gate electrode portion having a sidewall as a mask, and particularly to a method for reducing crystal defects in a Si substrate.

[0002]

2. Description of the Related Art A method of manufacturing a conventional MOS device having an LDD structure will be described with reference to FIG. That is, first, the SiO ₂ film 1 is formed on the Si substrate 11 by an ordinary method.
The gate electrode 13 is formed via the gate electrode 2 (see FIG. 2A). Next, C is deposited on the entire surface of the Si substrate 11 and the gate electrode 13.
An SiO ₂ film is laminated by the VD method, and then etched by reactive ion etching (RIE) and HF cleaning while leaving SiO ₂ on the upper surface of the gate to form a sidewall 14 (FIG. 2B). At this time, the SiO ₂ film 14a of about 100 to 400 ° remains on the Si substrate. Next, ion implantation 15 is performed using the gate electrode and the sidewall as a mask (see FIG. 2C), and then a high-temperature heat treatment is performed to form a diffusion region on the Si substrate.
However, in this method, oxygen in the SiO ₂ film is implanted into the Si substrate together with the implanted ions, and the crystal defects 16
Are fixed, and the crystal defects do not disappear even after high-temperature heat treatment is performed. Further, since the thickness variation of the remaining film 14a due to the RIE method and the HF cleaning method at the time of forming the sidewall is large, the defect density is increased. Such crystal defects cause an electric leak and lower the yield.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in order to improve the above-mentioned problems.
forming a gate electrode on an i-substrate via an insulating film; b) forming an insulating film on the entire surface of the Si substrate and the gate electrode; forming a polysilicon layer or an amorphous silicon layer thereon; Forming a SiO ₂ sidewall on the side wall of the gate electrode covered with the insulating film and the polysilicon layer or the amorphous silicon layer, and then performing ion implantation for forming a diffusion layer; After removal, a diffusion layer is formed by performing an intermediate temperature heat treatment at 800 to 850 ° C., and then, after removing the polysilicon layer or the amorphous silicon layer,
An object of the present invention is to provide a method for manufacturing a semiconductor device, comprising laminating an interlayer insulating film and performing a high-temperature heat treatment at 900 to 950 ° C.

[0004] Each of the above steps a) and b) of the present invention can be carried out using known means and equipment. a)
In the step, a gate electrode is formed on the Si substrate via an insulating film. Usually, an SiO ₂ film is used as the insulating film,
It is formed by a thermal oxidation method, a CVD method, or the like. The gate electrode may be a polysilicon layer only, or an N
SG (non-doped silicated glass), BPSG (boron
-doped phosphosilicate glass). These layers can be formed by a CVD method.

In the next step b), a polysilicon layer or an amorphous silicon layer is formed after an insulating film is formed on the entire surface of the Si substrate on which the gate electrode has been formed in the step a).

Here, as the insulating film, the same SiO ₂ film as in the step (a) can be used, but an SiN film may be used. The thickness of this insulating film is preferably 50 to 100 °.
Polysilicon layer or amorphous silicon layer is low pressure C
It can be formed by the VD method. At this time, a silicon compound such as Si ₂ H ₆ , SiH ₄ , SiH ₂ Cl ₂ , or SiCl ₄ can be used as a raw material. The polysilicon layer can be generally formed by a CVD method at a high temperature such as 600 to 650 ° C. under a pressure of 10 to 50 Pa. In addition, the amorphous silicon layer is generally formed at a low temperature such as 450 to 500 ° C.
It can be formed by a CVD method under a pressure of 50 Pa. The thickness of these polysilicon layers or amorphous silicon layers is preferably about 100 to 200 °.

In the next step c), sidewalls are formed. The sidewall is formed by first depositing SiO ₂ over the entire surface by a low-pressure CVD method and then using an etching method. As the etching method, a dry etching method is used, and CF ₄ , C ₂ F ₆ , CHF ₃
For example, an RIE method using cations (for example, CF ₃ ⁺ ) generated by applying high-frequency power to discharge in an atmosphere of a fluorocarbon-based gas such as CF ₃ ⁺ can be used. After this RIE method, for example, H for etching the edge portion of the sidewall
F processing may be performed. Next, ions such as As ⁺ and P ⁺ are implanted in a direction perpendicular to the Si substrate.

In the next step d), the sidewalls are removed with HF to make them stress-free. Next, heat treatment is performed. This heat treatment is for forming a diffusion layer by the ions implanted into the Si substrate, and an intermediate temperature of, for example, 800 to 850 ° C. is generally suitable.

Next, the polysilicon layer or the amorphous silicon layer is removed by an etching method. As an etching method, a dry etching method is used, and CCl
_{4. An} isotropic RIE etching method using SF ₆ gas or the like can be used. Next, an interlayer insulating film is laminated on the entire surface. As the interlayer insulating film, first, an NSG layer may be stacked and a BPSG layer may be further stacked, or only the BPSG layer may be used. Next, for example, a high-temperature heat treatment at about 900 to 950 ° C. is performed to flatten the interlayer insulating film and complete the formation of the diffusion layer.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the embodiments shown in the drawings, but the present invention is not limited thereto.

Embodiment 1 First, as shown in FIG.
A gate electrode 3 of a polysilicon layer is formed by a CVD method via the SiO ₂ layer formed by the D method. Next, a small amount of SiO ₂ film remaining on the Si substrate 1 is removed by performing a hydrofluoric acid treatment. Next, an SiO ₂ film 4 of about 50 to 100 ° is formed on the entire surface of the Si substrate 1 and the gate electrode 3 by a thermal oxidation method, and a CVD method using Si ₂ H ₆ thereon at 620 ° C. under a pressure of 20 Pa. To form a polysilicon layer 5 having a thickness of about 100 to 200 [deg.] (FIG. 1B). Next, S of the sidewall material
iO ₂ is deposited by a CVD method and etched by an RIE method using CF ₄ to remove the sidewall 6 from the SiO _2.
It is formed on the side surface of the gate electrode 3 having the film 4 and the polysilicon layer 5 (FIG. 1C). At an acceleration energy of 60 to 80 Kev and a dose of 5 × 10 ¹⁵ , As ⁺ ions are implanted using the gate electrode 3, the SiO ₂ film 4, the polysilicon layer 5 and the sidewall 6 as a mask (arrow 7). After removing the sidewall by hydrofluoric acid treatment to make it stress-free, heat treatment is performed at 800 to 850 ° C. to form a diffusion layer. Then CCl ₄ a polysilicon layer 5
[FIG. 1 (d)]. Then B
A semiconductor device is manufactured by depositing PSG over the whole by a conventional method, heat-treating it at 900 to 950 ° C. to flatten it, and then forming a contact hole and metal wiring.

Embodiment 2 First, as shown in FIG.
To make the Si substrate 1_TwoOf the polysilicon layer through the film
The gate electrode 3 is formed. Next, hydrofluoric acid treatment is performed to
A small amount of SiO remaining on the substrate 1_TwoRemove the film. Next
About 5 μm on the entire surface of the Si substrate 1 and the gate electrode 3 by thermal oxidation.
0-100% SiO_TwoA film 4 is formed, and 46
At 0 ° C. under a pressure of 20 Pa, Si_TwoH₆CVD method using
To form an amorphous silicon layer 5 'of about 100 to 200
Laminate [FIG. 1 (b)]. Next, S of the sidewall material
iO_TwoIs deposited by a CVD method, and CF is deposited._FourMethod using RIE
(Hydrofluoric acid treatment may be added.)
With the SiO_TwoThe film 4 and the amorphous silicon layer 5 '
[FIG. 1]
(C)]. 60-80 Kev acceleration energy and 5
× 10^FifteenWith a dose of ⁺Ions to the gate electrode
3, SiO_TwoFilm 4, amorphous silicon layer 5 ',
Injection is performed using the wall 6 as a mask (arrow 7). Rhinoceros
The door is removed by hydrofluoric acid treatment and stress free
And heat-treated at 800-850 ° C to form a diffusion layer.
Let it run. Next, the amorphous silicon layer 5 is_FourTo
It is removed by the RIE method used (FIG. 1D). Then N
SG and BPSG are sequentially deposited on the whole by a usual method,
Heat treatment at 900-950 ° C. to planarize, then
Semiconductor devices with contact holes and metal wiring
Is produced.

[0013]

According to the method of the present invention, S
iO_TwoFilm and polysilicon layer or amorphous silicon
Since the layers are stacked, when ion implantation is performed,
O_TwoOxygen in the film is less likely to be implanted into the Si substrate.
Therefore, the number of crystal defects in the diffusion layer generated after the heat treatment is small.
No. Moreover, the etching at the time of forming the above-mentioned sidewalls
Stops at the polysilicon layer or amorphous silicon layer
The above SiO _TwoVariation in thickness of film and silicon layer
Stickiness is small. Therefore, it is easy to control the film thickness and the diffusion layer
The defect density decreases. Also especially amorphous silicon
The layer has an implantation efficiency of SiO_TwoAs much as a membrane
Has the advantage that uneven ion implantation does not occur.
You. As a result, the obtained semiconductor device and the leakage current decrease.
Lowering of the junction withstand voltage, improving reliability
The yield is improved.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a manufacturing process showing a manufacturing method of the present invention.

FIG. 2 is an explanatory view of a manufacturing process showing a conventional manufacturing method.

[Explanation of symbols]

1 Si substrate 2 SiO ₂ film 3 gate electrode 4 SiO ₂ film 5 polysilicon layer 5 'amorphous silicon layer 6 sidewalls 7 ion implantation

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] A) forming a gate electrode on a semiconductor Si substrate via an insulating film; b) forming an insulating film over the entire surface of the Si substrate and the gate electrode, and further forming a polysilicon layer or Forming an amorphous silicon layer, c) forming a SiO ₂ side wall on the side wall of the gate electrode covered with the insulating film and the polysilicon layer or the amorphous silicon layer, and then forming ions for forming a diffusion layer. After implanting and d) removing the sidewalls, 80
The diffusion layer is formed by performing intermediate temperature heat treatment at from 0 to 850 ° C., and then after removing the polysilicon layer or amorphous silicon layer above, by laminating an interlayer insulating film 9
A method for manufacturing a semiconductor device, comprising performing a high-temperature heat treatment at 00 to 950 ° C.