JPH07245382A - Manufacture of composite element and lamination substrate - Google Patents

Manufacture of composite element and lamination substrate

Info

Publication number
JPH07245382A
JPH07245382A JP6035126A JP3512694A JPH07245382A JP H07245382 A JPH07245382 A JP H07245382A JP 6035126 A JP6035126 A JP 6035126A JP 3512694 A JP3512694 A JP 3512694A JP H07245382 A JPH07245382 A JP H07245382A
Authority
JP
Japan
Prior art keywords
substrate
oxide film
semiconductor substrate
bonded
supporting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6035126A
Other languages
Japanese (ja)
Other versions
JP3298291B2 (en
Inventor
Hiroshi Shimabukuro
浩 島袋
Atsuo Hirabayashi
温夫 平林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP03512694A priority Critical patent/JP3298291B2/en
Publication of JPH07245382A publication Critical patent/JPH07245382A/en
Application granted granted Critical
Publication of JP3298291B2 publication Critical patent/JP3298291B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To acquire a composite element wherein a power element of high breakdown strength and an element of fast operation are formed on the same substrate by making a thickness of an insulation film irregular by thickening a part wherein an application voltage of an insulation film rises between a semiconductor substrate and a supporting substrate wherein a high breakdown strength element is formed. CONSTITUTION:Impurities are selectively introduced from a surface to an SOI substrate 1 whose conductivity type is n-type, a diode structure is formed by providing a p<+>-anode region 22 and an n<+>-cathode region 23 having an n<->-layer 21 therebetween and a field oxide film 24, an anode electrode 25 and a cathode electrode 26 are arranged on a surface like usual. Furthermore, an oxide film 2 is made thick below the p<+>-region 22. Thereby, breakdown strength is improved. For example, even if t=1mum, element withstand voltage attains 400V by making T=4mum. According to this constitution, not only a diode but also a power element such as IGBT and a logic circuit can be manufactured in the same process simultaneously.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高耐圧素子と高速素子
とからなる複合素子およびその複合素子に用いる貼り合
わせ基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite element including a high breakdown voltage element and a high speed element and a method for manufacturing a bonded substrate used for the composite element.

【0002】[0002]

【従来の技術】電力用半導体素子を制御回路あるいは駆
動回路と同一半導体基体に複合するため、十分な電気絶
縁性を有するSOI ( Silicon on Insulatar ) 基板を
用いた誘電体分離構造が採用される。一般的なSOI基
板として、シリコンウエーハを酸化膜を介して接着した
貼り合わせ基板が知られている。このような貼り合わせ
基板は、高耐圧のIGBTなどにも用いられる。
2. Description of the Related Art In order to combine a power semiconductor element with a control circuit or a drive circuit on the same semiconductor substrate, a dielectric isolation structure using an SOI (Silicon on Insulatar) substrate having sufficient electric insulation is adopted. As a general SOI substrate, a bonded substrate in which a silicon wafer is bonded via an oxide film is known. Such a bonded substrate is also used for a high breakdown voltage IGBT or the like.

【0003】図2 (a) 〜 (c) は従来の貼り合わせ基
板の製造方法を示し、シリコンウエーハ10の表面に、
酸素あるいは水蒸気雰囲気中での熱処理により均一な熱
酸化膜2を形成する〔同図 (a) 〕。熱酸化膜2の膜厚
は、SOI基板の仕様に合わせて決定され、またその時
の熱処理条件も、一般的な条件で差支えなく、効率的な
条件でよい。熱酸化した後も十分に鏡面状態は保たれて
おり、このままウエーハの鏡面同志を重ね合わせても密
着性は高いが、例えば古川、新保、応用物理第60巻
(1991) p. 790に記載されているように、洗浄
活性化処理を行って重ね合わせた方が、ウエーハ表面に
結合された水酸基 (OH基) の働きにより、その後の熱
処理による接着の均一性が良い。同図 (b) に示したよ
うに重ね合わせた2枚のウエーハ10を、電気炉にて熱
処理する。温度は200〜900℃、時間は1時間から
10時間で、雰囲気は特に重要な因子ではない。シリコ
ンとシリコン酸化膜の熱膨張係数が異なる点を考慮する
と、比較的低温で処理した方が良いが、熱処理後に未接
合部分であるボイドの発生がない事や、接着面が十分な
強度を有しているかなど考慮しなければならない。この
ような手法による貼り合わせでは、貼り合わせ面が鏡面
であること、表面を活性化処理することが、均一で広い
面積を接合するためのポイントである。そのあと、素子
を形成する側のシリコンウエーハ10を研磨し、素子を
形成するために必要な厚さをもったSOI基板1を形成
するが、その厚さは一般的には5〜50μmであり、こ
のように極薄であるため、一方のシリコンウエーハ10
は、支持基板として役立つ〔同図(c) 〕。全体の厚さ
は400〜700μmであって、それ以後のLSI形成
工程に回される。素子形成工程での発塵を抑えるため
に、SOI基板1の外周部はエッチングされ、支持基板
10よりも若干面積が小さくなる。
FIGS. 2A to 2C show a conventional method for manufacturing a bonded substrate, in which the surface of the silicon wafer 10 is
A uniform thermal oxide film 2 is formed by heat treatment in an oxygen or water vapor atmosphere [FIG. The film thickness of the thermal oxide film 2 is determined in accordance with the specifications of the SOI substrate, and the heat treatment conditions at that time may be general conditions and may be efficient conditions. Even after thermal oxidation, the mirror surface condition is sufficiently maintained, and even if the mirror surfaces of the wafers are piled up as they are, the adhesion is high. For example, Furukawa, Shinho, Applied Physics Vol. 60.
As described in (1991) p. 790, when the washing activation treatment is performed and the layers are superposed, the uniformity of the adhesion by the subsequent heat treatment is caused by the function of the hydroxyl group (OH group) bonded to the surface of the wafer. Is good. The two wafers 10 stacked as shown in FIG. 7B are heat-treated in an electric furnace. The temperature is 200 to 900 ° C., the time is 1 to 10 hours, and the atmosphere is not a particularly important factor. Considering that the coefficient of thermal expansion of silicon and that of silicon oxide film are different, it is better to process at a relatively low temperature, but there are no voids that are unbonded parts after heat treatment, and the bonding surface has sufficient strength. You have to consider what you are doing. In the bonding by such a method, the bonding surface is a mirror surface, and the surface activation treatment is a point for bonding a uniform and large area. After that, the silicon wafer 10 on the element forming side is polished to form the SOI substrate 1 having a thickness necessary for forming the element. The thickness is generally 5 to 50 μm. , Because it is extremely thin, one silicon wafer 10
Serves as a supporting substrate [(c) in the figure]. The total thickness is 400 to 700 μm, and is passed to the subsequent LSI forming process. In order to suppress dust generation in the element forming process, the outer peripheral portion of the SOI substrate 1 is etched so that the area is slightly smaller than that of the supporting substrate 10.

【0004】[0004]

【発明が解決しようとする課題】上記のような工程で作
られたSOI基板1は均一な厚さを持ち、支持基板10
とは均一な厚さの酸化膜2によって絶縁されている。し
かし、同一基板に電力用半導体素子とロジック回路を形
成する場合、電力用素子は高耐圧で厚い半導体基体を必
要とし、ロジック回路は高速動作を達成するためにでき
るだけ薄い半導体基板が望ましいが、この双方の要求を
満足させることができない。貼り合わせの前に鏡面研磨
を行う関係から、そのような厚さの異なるSOI基板を
もち、共通の平らな表面をもつ貼り合わせ基板の製造は
困難である。薄い半導体基板に高耐圧素子を形成する方
策として横型半導体素子を採用することも考えられる。
しかし、その場合、図3に示す問題がある。図3は横型
ダイオードを示し、シリコン支持基板10と酸化膜2を
介して接着されたSOI基板1のn- 層21の一方の側
にp+ アノード領域22、他方の側にn+ カソード領域
23が形成され、フィールド酸化膜24に開けられた接
触孔でアノード電極25、カソード電極26がそれぞれ
接触している。電源の+極をK端子を介してカソード電
極26に、−極をA端子を介してアノード電極25に接
続し、ダイオードに逆方向バイアスを印加する。点線で
示した等電位線27は、n- 層21の表面部では、フィ
ールド酸化膜24、アノード電極25、カソード電極2
6の最適化された耐圧設計により間隔を広げることがで
きるが、等電位線27は支持基板10内には広がらない
ので、酸化膜2の中では密となってしまう。結果、高速
素子のためのSOI基板と同様に薄い酸化膜2の上のS
OI基板に横型ダイオードを形成しても、酸化膜2の中
で電界強度が強くなるため、絶縁破壊が起こり、高い素
子耐圧が得られない。
The SOI substrate 1 manufactured by the above process has a uniform thickness, and has the supporting substrate 10
Are insulated by an oxide film 2 having a uniform thickness. However, when a power semiconductor element and a logic circuit are formed on the same substrate, the power element requires a high breakdown voltage and a thick semiconductor substrate, and the logic circuit is preferably as thin as possible in order to achieve high-speed operation. We cannot meet the requirements of both parties. It is difficult to manufacture a bonded substrate having an SOI substrate having such a different thickness and having a common flat surface because of mirror-polishing before bonding. As a measure for forming a high breakdown voltage element on a thin semiconductor substrate, it may be possible to adopt a lateral semiconductor element.
However, in that case, there is a problem shown in FIG. FIG. 3 shows a lateral diode, which is a p + anode region 22 on one side of the n layer 21 and an n + cathode region 23 on the other side of the SOI substrate 1 bonded to the silicon supporting substrate 10 through the oxide film 2. Is formed, and the anode electrode 25 and the cathode electrode 26 are in contact with each other through the contact holes formed in the field oxide film 24. The + pole of the power source is connected to the cathode electrode 26 via the K terminal, and the − pole of the power source is connected to the anode electrode 25 via the A terminal, and a reverse bias is applied to the diode. The equipotential lines 27 shown by dotted lines are the field oxide film 24, the anode electrode 25, and the cathode electrode 2 on the surface portion of the n layer 21.
Although the gap can be widened by the optimized breakdown voltage design of 6, the equipotential lines 27 do not spread in the supporting substrate 10, and therefore become dense in the oxide film 2. As a result, S on the thin oxide film 2 is similar to the SOI substrate for the high speed device.
Even if the lateral diode is formed on the OI substrate, the electric field strength becomes strong in the oxide film 2, so that dielectric breakdown occurs and a high element breakdown voltage cannot be obtained.

【0005】本発明の目的は、上述の問題を解決し、高
耐圧の電力用素子と高速動作の素子とを同一基体上に形
成した複合素子およびそれに用いることのできる貼り合
わせ基板の製造方法を提供することにある。
An object of the present invention is to solve the above problems and to provide a composite element in which a high breakdown voltage power element and a high-speed operation element are formed on the same substrate, and a method for manufacturing a bonded substrate which can be used for the composite element. To provide.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成するた
めに、請求項1に記載の本発明は、同一支持基板と絶縁
膜によって絶縁された半導体基板に形成される半導体基
板に形成される高耐圧素子と高速素子とを含む複合素子
において、絶縁膜の厚さが均一でなく、高耐圧素子の形
成される半導体基板と支持基板との間の絶縁膜の印加電
圧が高くなる部分で厚くされたものとする。そのような
複合素子に用いられることのできる、素子の形成される
半導体基板と支持用半導体基板とからなる貼り合わせ基
板の、請求項2に記載の本発明の製造方法は、支持用半
導体基板の一面上に加工により凹部を形成したのち、そ
の凹部を埋める厚い部分を有する酸化膜によりこの面を
覆い、その酸化膜と素子用半導体基板の一面を覆う酸化
膜とを重ね合わせ、熱処理により接着するものとする。
重ね合わせる前に、支持用半導体基板一面上の酸化膜の
表面に水素基を結合させ、素子用半導体基板一面上の酸
化膜の表面に水酸基を結合させることが有効である。支
持用半導体基板の一面上の酸化膜表面をドライエッチン
グしたのち、光励起により活性化した水素を接触させる
ことにより、前記酸化膜の表面に水素基を結合させるの
が良い方法である。
In order to achieve the above object, the present invention according to claim 1 is formed on a semiconductor substrate formed on the same supporting substrate and a semiconductor substrate insulated by an insulating film. In a composite element including a high breakdown voltage element and a high speed element, the thickness of the insulating film is not uniform, and the thickness is increased in a portion where the applied voltage of the insulating film between the semiconductor substrate on which the high breakdown voltage element is formed and the supporting substrate is high. It has been done. The manufacturing method of the present invention according to claim 2, wherein the manufacturing method of the present invention is a bonded substrate comprising a semiconductor substrate on which an element is formed and a supporting semiconductor substrate that can be used for such a composite element. After forming a recess on one surface by processing, this surface is covered with an oxide film having a thick portion filling the recess, and the oxide film and the oxide film covering one surface of the element semiconductor substrate are overlapped and bonded by heat treatment. I shall.
Before stacking, it is effective to bond a hydrogen group to the surface of the oxide film on the one surface of the supporting semiconductor substrate and bond a hydroxyl group to the surface of the oxide film on the one surface of the device semiconductor substrate. It is a good method to dry-etch the surface of the oxide film on one surface of the supporting semiconductor substrate and then bring hydrogen activated by photoexcitation into contact therewith to bond hydrogen groups to the surface of the oxide film.

【0007】[0007]

【作用】支持基板との間の絶縁膜への印加電圧が高くな
る高耐圧素子の部分は絶縁膜の厚さを厚くすることによ
り電界強度が緩和されるため、同一支持基板上の半導体
基板に高耐圧素子を複合させることができる。このよう
な絶縁膜の厚い部分は、支持基板の表面を加工して凹部
を形成することにより作らねばならず、加工された面が
かなり荒れてしまうため、その部分に形成される酸化膜
の表面も荒れているが、その面に水素基を結合させる
と、この水素基と酸素基のある支持基板の表面の酸化膜
は、従来技術のように水酸基の結合した素子用半導体基
板の表面の酸化膜と熱処理により良好に接着する。
Since the electric field strength is relaxed by increasing the thickness of the insulating film in the portion of the high breakdown voltage element where the voltage applied to the insulating film between the supporting substrate and the substrate is high, the semiconductor substrate on the same supporting substrate is not affected. High breakdown voltage elements can be combined. Such a thick portion of the insulating film must be formed by processing the surface of the supporting substrate to form a recess, and the processed surface is considerably roughened. Therefore, the surface of the oxide film formed in that portion is considerably roughened. However, when a hydrogen group is bonded to the surface, the oxide film on the surface of the supporting substrate having the hydrogen group and the oxygen group is oxidized on the surface of the semiconductor substrate for a device to which a hydroxyl group is bonded as in the conventional technique. Good adhesion by film and heat treatment.

【0008】[0008]

【実施例】図1は、SOI基板に形成された本発明の一
実施例の横型ダイオードを示し、図2、図3と共通の部
分には同一の符号が付されている。導電形がn形のSO
I基板1に、表面から選択的に不純物を導入してn-
21をはさむp+ アノード領域22、n+ カソード領域
23を設けてダイオード構造を作り、表面上にフィール
ド酸化膜24、アノード電極25、カソード電極26を
配置することは図3のダイオードと同様であるが、p+
領域22の下で酸化膜2が厚くされている。これにより
耐圧が向上することを図4に示したデータから示す。こ
のデータは、図1と同様の構造の図5のダイオードにお
いて、厚さt 0 5μmのSOI基板の下の酸化膜2の薄
い部分の厚さtが1μm、2μm、3μmのもので、厚
い部分の厚さTを変えた場合の素子耐圧である。酸化膜
2の厚さtを厚くすれば素子耐圧は上昇しているが、素
子作成工程の熱履歴で基板の歪みが発生しやすくなり、
同一半導体基体に微細な論理回路は形成できない。しか
し、例えばt=1μmでもT=4μmにすることによ
り、素子耐圧は400Vに達し、このような構造にする
ことにより、ダイオードに限らずIGBTなどの電力用
素子と論理回路を同一工程で同時に製造することができ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows one embodiment of the present invention formed on an SOI substrate.
The horizontal diode of the embodiment is shown, and the same parts as those in FIGS.
Minutes are given the same reference numerals. N type conductivity SO
N is obtained by selectively introducing impurities into the I substrate 1 from the surface.-layer
P sandwiching 21+Anode region 22, n+Cathode area
Create a diode structure by providing 23, and feel on the surface
The oxide film 24, the anode electrode 25, and the cathode electrode 26.
Placement is similar to the diode of FIG. 3, but p+
The oxide film 2 is thickened below the region 22. This
It is shown from the data shown in FIG. 4 that the breakdown voltage is improved. This
The data in the diode of FIG. 5 having the same structure as that of FIG.
And the thickness t 0Thin oxide film 2 under 5 μm SOI substrate
The thickness t of the uncoated part is 1 μm, 2 μm, 3 μm,
It is the element breakdown voltage when the thickness T of the open portion is changed. Oxide film
If the thickness t of 2 is increased, the withstand voltage of the element increases, but
Substrate distortion easily occurs due to the thermal history of the child making process,
A fine logic circuit cannot be formed on the same semiconductor substrate. Only
However, for example, even if t = 1 μm, by setting T = 4 μm,
Therefore, the device breakdown voltage reaches 400 V, and such a structure is adopted.
As a result, not only for diodes but also for power such as IGBT
Devices and logic circuits can be manufactured simultaneously in the same process
It

【0009】次に、請求項2に記載の本発明のこのよう
な電力用素子を形成できる貼り合わせ基板製造の実施例
を図面を引用して説明する。図6 (a) 〜 (e) に示す
製造工程では、図2 (a) と同様にシリコンウエーハ1
0を熱酸化し、酸化膜2を形成する〔同図 (a) 〕。次
にそのようなウエーハの少なくとも1枚の表面にレジス
ト3のパターンを形成し、酸化膜およびシリコンをエッ
チングして溝4を形成する〔同図6 (b) 〕。この溝
は、前述の横型ダイオードにおけるように、高い電圧の
印加されるようになる酸化膜2の部分に形成する。次い
で、レジスト3を除去し、洗浄してから、熱CVD法に
よる酸化膜2を、溝4が十分に埋まるまで堆積後、ドラ
イエッチングで平坦化する〔同図6 (c) 〕。ドライエ
ッチングの終点の検出は、時間で管理する方法、あるい
はCVD膜2を形成する前にエッチング速度の異なる熱
窒化膜を所期の厚さに形成してストッパとする方法など
がある。この段階でエッチングむらが無いように細心の
注意が必要であるが、これまでの工程は、すでに開発さ
れているLSIプロセス技術で対応可能なものである。
Next, an embodiment of manufacturing a laminated substrate capable of forming such a power element of the present invention according to claim 2 will be described with reference to the drawings. In the manufacturing process shown in FIGS. 6A to 6E, the silicon wafer 1 is manufactured in the same manner as in FIG.
0 is thermally oxidized to form an oxide film 2 [(a) in the same figure]. Next, a pattern of the resist 3 is formed on the surface of at least one of such wafers, and the oxide film and silicon are etched to form the groove 4 [FIG. 6 (b)]. This groove is formed in the portion of the oxide film 2 where a high voltage is applied, as in the lateral diode described above. Next, after removing the resist 3 and washing, the oxide film 2 by the thermal CVD method is deposited until the groove 4 is sufficiently filled, and then flattened by dry etching [FIG. 6 (c)]. The detection of the end point of the dry etching may be performed by a method of managing it by time, or a method of forming a thermal nitride film having a different etching rate to a desired thickness before using the CVD film 2 as a stopper. At this stage, it is necessary to pay close attention to prevent uneven etching, but the steps up to this point can be handled by the already developed LSI process technology.

【0010】次に貼り合わせ前の洗浄処理の工程に移
る。従来方法の場合は、液中での洗浄処理中に、酸化膜
表面のSi−O−Si結合が切れ、Si−OH結合で終
端された表面になる。洗浄法としてもいろいろと検討さ
れているが、本質的には水酸 (O−H) 基で置換すれば
よく、一般的な塩酸過水 (塩酸と過酸化水素の混合液)
とアンモニア過水 (アンモニアと過酸化水素の混合液)
による洗浄で十分であった。しかしながら、図6 (c)
に示す片方が加工された面の場合、広い面にわたってボ
イド (未接合部) のない貼り合わせ基板を作ることは困
難であった。そこで、加工を行ったウエーハについて
は、塩酸過水洗浄の後に、光励起したH2 雰囲気中で、
数分間処理する工程を付加した。同処理後は、すみやか
に図6(a)の工程のみを経て未加工のウエーハ10と
密着させ、貼り合わせ熱処理を行う〔同図 (d) 〕。熱
処理は、比較的低温 (200〜400℃) で1〜2時間
と、比較的高温 (700〜900℃) で2〜4時間の2
段階処理を行う方が望ましい。
Next, the step of cleaning treatment before bonding is performed. In the case of the conventional method, the Si—O—Si bond on the surface of the oxide film is broken during the cleaning treatment in the liquid, resulting in a surface terminated with a Si—OH bond. Various cleaning methods have been studied, but essentially, it can be replaced with a hydroxyl (OH) group, and a general hydrochloric acid / hydrogen peroxide mixture (mixture of hydrochloric acid and hydrogen peroxide).
And ammonia hydrogen peroxide (a mixture of ammonia and hydrogen peroxide)
Washing with was sufficient. However, FIG. 6 (c)
In the case where one of the surfaces shown in (1) was processed, it was difficult to make a bonded substrate without voids (unbonded parts) over a wide surface. Therefore, for the processed wafer, after washing with hydrochloric acid / hydrogen peroxide, in a photoexcited H 2 atmosphere,
A step of treating for several minutes was added. After the treatment, the raw wafer 10 is immediately brought into close contact with the unprocessed wafer 10 only through the step of FIG. 6 (a), and a bonding heat treatment is carried out [FIG. 6 (d)]. Heat treatment is performed at a relatively low temperature (200-400 ° C) for 1-2 hours and at a relatively high temperature (700-900 ° C) for 2-4 hours.
It is desirable to perform stepwise treatment.

【0011】このようにして貼り合わせた図6 (d) に
示すウエーハを、赤外線の透過強度差を利用した方法で
ボイドの発生状況を調べた結果、未加工同志を貼り合わ
せた場合と遜色のない良好なものであることが確認され
た。最終的には、従来通りSOI基板1の研磨、仕上げ
を行い, 絶縁膜2の厚さが部分的に異なる貼り合わせS
OI基板が得られた〔図6 (e) 〕。
The wafers shown in FIG. 6 (d) bonded in this way were examined for the occurrence of voids by the method utilizing the difference in infrared transmission intensity. As a result, the results were comparable to those when the unprocessed comrades were bonded. It was confirmed that it was not good. Finally, the SOI substrate 1 is polished and finished as usual, and the bonding S in which the thickness of the insulating film 2 is partially different is performed.
An OI substrate was obtained [Fig. 6 (e)].

【0012】ここまでに至る経過について説明する。当
初、貼り合わせがうまくいかないのは、一般的に考えら
れるように、溝4の加工を加えた表面はかなり荒れてし
まい、密着性が悪くなったためと考え、機械研磨を試み
た。シリコン酸化膜2つまりガラスの研磨はかなり高度
な技術を要し、歩留まり、コスト面から実用的でないこ
とが分かった。
The process up to this point will be described. Initially, it was thought that the reason why the bonding was not successful was that, as is generally considered, the surface on which the groove 4 had been processed was considerably roughened, and the adhesion was poor, and an attempt was made to perform mechanical polishing. It has been found that polishing of the silicon oxide film 2, that is, glass requires a considerably high technique, is not practical in terms of yield and cost.

【0013】さまざまな試行錯誤のうち、平坦化やレジ
スト・アッシングなどのドライプロセス工程により不良
が発生すること、これら工程により形成されたダメージ
層を希ふっ酸で除去しても改善されないこと、また、鏡
面の熱酸化膜でも希ふっ酸によるエッチングで面の凹凸
が顕著になり、ボイドが発生しやすくなることなどが分
かった。一方で、上記加工を経たウエーハでも、相手側
が鏡面のシリコン面であれば、ボイドの発生が無いこと
も分かった。
Among various trials and errors, defects are caused by dry process steps such as planarization and resist ashing, and the damage layer formed by these steps is not improved even if removed by dilute hydrofluoric acid. It was also found that even with the thermal oxide film on the mirror surface, the unevenness of the surface became remarkable by etching with dilute hydrofluoric acid, and voids were easily generated. On the other hand, it was also found that even with the wafer that has undergone the above processing, voids do not occur if the other side is a mirror-finished silicon surface.

【0014】このような実験事実から、極端な平坦性が
必ずしも必要ではなく、境界面の反応を高めることで、
良好な貼り合わせウエーハを形成できることが分かっ
た。本発明による貼り合わせ方法の要点を、図を用いて
説明する。まず、ドライエッチングによる平坦化工程
は、通常、グロープラズマ放電や、ECRプラズマによ
り行われる。その際、図7に示すように酸化膜2との境
界層にシース31と呼ばれる強電界層が形成され、同空
間により加速された正イオン32の働きで、酸化膜2の
表面にダメージ層5を形成する。このダメージ層5は、
極めて薄いが、アンモニア過水洗浄後の表面荒れ状態
が、ドライプロセス工程を経ないものと比較して、明ら
かに異なることからその存在を確認できる。このダメー
ジ層5は、準安定状態のガラス層と考えられ、通常より
Si−O−Si結合は弱いと考えられる。
From such experimental facts, extreme flatness is not always necessary, and by increasing the reaction of the boundary surface,
It was found that a good bonded wafer can be formed. The essential points of the bonding method according to the present invention will be described with reference to the drawings. First, the flattening step by dry etching is usually performed by glow plasma discharge or ECR plasma. At that time, as shown in FIG. 7, a strong electric field layer called a sheath 31 is formed in the boundary layer with the oxide film 2, and the positive ions 32 accelerated by the space act to damage the surface of the oxide film 2 to the damaged layer 5. To form. This damage layer 5 is
Although it is extremely thin, its presence can be confirmed from the fact that the surface roughening state after cleaning with ammonia-hydrogen peroxide is clearly different compared to that without the dry process step. The damaged layer 5 is considered to be a metastable glass layer, and the Si-O-Si bond is considered to be weaker than usual.

【0015】前述のように加工されたウエーハ10に
は、塩酸過水洗浄のみを行い、光励起による水素ラジカ
ル処理を行う。この処理は、真空チャンバ内にウエーハ
を設置し、H2 ガスを10〜500Paの圧力に調整し
ながら紫外線ランプを照射し、5〜10分程度保持す
る。紫外線照射によりH2 ガスが活性化し、図8に示す
ようにさまざまな種類の活性な水素基33が発生する。
この水素基33は、ダメージ層5の表面の不安定なSi
−O−Si結合を切り、酸化膜2の表面上にSi−H結
合を多く形成して行く。先程のドライプロセスと異な
り、ガスの電離がないため、ダメージを受けることなく
反応がゆるやかに進む。通常のグロープラズマ放電やE
CRプラズマ装置を改造し、ウエーハに中性のラジカル
のみが到達するようにしても同様な効果がある。
The wafer 10 processed as described above is only washed with hydrochloric acid / hydrogen peroxide mixture and subjected to hydrogen radical treatment by photoexcitation. In this process, a wafer is installed in a vacuum chamber, an ultraviolet lamp is irradiated while H 2 gas is adjusted to a pressure of 10 to 500 Pa, and the wafer is held for about 5 to 10 minutes. The UV irradiation activates the H 2 gas, and various types of active hydrogen groups 33 are generated as shown in FIG.
This hydrogen group 33 is an unstable Si on the surface of the damage layer 5.
The —O—Si bond is broken, and many Si—H bonds are formed on the surface of the oxide film 2. Unlike the previous dry process, there is no ionization of gas, so the reaction proceeds slowly without damage. Normal glow plasma discharge and E
Similar effects can be obtained by modifying the CR plasma device so that only neutral radicals reach the wafer.

【0016】相手側のウエーハの密着は、Si−H結合
が空気中の水分と反応しないうちに行い、熱処理工程に
入る。図9に示すように、まず低温では、Si−Oと水
酸基の反応でSi−O−Si結合ができ、接着が進む。
発生した水分は一時、酸化膜2中に蓄えられる。次に高
温処理に移行する。ここでは、水分が拡散して抜ける
が、その際、ダメージ層5の回復、流動性を助け、また
Si−H結合部へ酸素を供給する。このような働きによ
りボイド部分が埋められ、良好な貼り合わせ基板を得る
ことができる。
The mating of the wafer on the other side is performed before the Si--H bond reacts with the moisture in the air, and the heat treatment step is started. As shown in FIG. 9, first, at low temperature, Si—O—Si bond is formed by the reaction of Si—O and hydroxyl group, and adhesion proceeds.
The generated water is temporarily stored in the oxide film 2. Next, the high temperature treatment is performed. Here, water diffuses and escapes, but at this time, it assists the recovery and fluidity of the damage layer 5, and also supplies oxygen to the Si—H bond portion. By such a function, the void portion is filled, and a good bonded substrate can be obtained.

【0017】この技術を応用すれば、鏡面加工が困難で
あったSiC基板や石英ガラスにも、同様に広い面積に
渡って良好な貼り合わせが可能である。以上の実施例で
は、酸化膜が一部分厚い貼り合わせ基板の製造方法とし
て、エッチングによるシリコン基板の加工とCVDによ
る酸化膜の埋め込みによる方法を示したが、応用する素
子の仕様に合わせて、LOCOS技術、増速酸化を用い
て製造コストを低減することも可能である。
By applying this technique, good bonding can be similarly performed over a wide area even on a SiC substrate or quartz glass, which has been difficult to be mirror-finished. In the above embodiments, as a method of manufacturing a bonded substrate having a partially thick oxide film, a method of processing a silicon substrate by etching and embedding an oxide film by CVD has been described. However, according to the specifications of an applied device, the LOCOS technique is used. It is also possible to reduce the manufacturing cost by using accelerated oxidation.

【0018】[0018]

【発明の効果】請求項1の本発明によれば、支持基板と
貼り合わせたSOI基板に高耐圧素子を含む複合素子を
形成する場合に中間の絶縁膜を高い電圧の印加される部
分のみ厚くすることにより、高速素子を含む制御回路な
どの論理回路と同一基板に複合することが可能となっ
た。請求項2の本発明によれば、このような複合素子に
用いることのできるSOI貼り合わせ基板の製造に、厚
い酸化膜を設ける凹部を加工した支持用半導体基板上の
酸化膜の活性化に水素基を用いることにより、ボイドの
発生を抑えた貼り合わせが可能となり、製造歩留まりの
向上、低コスト化が可能となった。
According to the present invention of claim 1, when a composite element including a high breakdown voltage element is formed on an SOI substrate bonded to a supporting substrate, an intermediate insulating film is thickened only in a portion to which a high voltage is applied. By doing so, it has become possible to combine a logic circuit such as a control circuit including a high-speed element on the same substrate. According to the present invention of claim 2, in manufacturing an SOI bonded substrate that can be used for such a composite element, hydrogen is used for activation of an oxide film on a supporting semiconductor substrate in which a concave portion provided with a thick oxide film is processed. By using the base, it becomes possible to perform the bonding while suppressing the generation of voids, and it is possible to improve the manufacturing yield and reduce the cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1の本発明の一実施例の複合素子のうち
のダイオード部分の断面図
FIG. 1 is a sectional view of a diode portion of a composite element according to an embodiment of the present invention according to claim 1.

【図2】従来のSOI貼り合わせ基板の製造工程を
(a) 〜 (c) の順に示す断面図
FIG. 2 shows a manufacturing process of a conventional SOI bonded substrate
Sectional drawing shown in order of (a)-(c)

【図3】従来の複合素子のダイオード部分の断面図FIG. 3 is a sectional view of a diode portion of a conventional composite element.

【図4】SOI基板の酸化膜の厚さをパラメータとした
ダイオード素子耐圧と厚い酸化膜部分の厚さとの関係線
FIG. 4 is a diagram showing the relationship between the breakdown voltage of a diode element and the thickness of a thick oxide film with the thickness of the oxide film of the SOI substrate as a parameter.

【図5】図4のデータを得るためのダイオードの断面図5 is a cross-sectional view of a diode for obtaining the data of FIG.

【図6】請求項2の本発明の一実施例の製造工程を
(a) ないし (e) の順に示す断面図
FIG. 6 shows a manufacturing process of an embodiment of the present invention according to claim 2.
Sectional views shown in the order of (a) to (e)

【図7】請求項2の本発明の一実施例のドライプロセス
工程の説明のための断面図
FIG. 7 is a cross-sectional view for explaining a dry process step of an embodiment of the present invention of claim 2;

【図8】請求項2の本発明の一実施例の水素処理工程の
説明のための断面図
FIG. 8 is a sectional view for explaining a hydrogen treatment process of an embodiment of the present invention according to claim 2;

【図9】請求項2の本発明の一実施例の熱処理工程の説
明のための断面図
FIG. 9 is a sectional view for explaining a heat treatment process of an embodiment of the present invention according to claim 2;

【符号の説明】[Explanation of symbols]

1 SOI基板 2 酸化膜 3 レジスト 4 溝 10 支持基板 21 n- 層 22 p+ アノード領域 23 n+ カソード領域 25 アノード電極 26 カソード電極1 SOI Substrate 2 Oxide Film 3 Resist 4 Groove 10 Supporting Substrate 21 n - Layer 22 p + Anode Region 23 n + Cathode Region 25 Anode Electrode 26 Cathode Electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】同一支持基板と絶縁膜によって絶縁された
半導体基板に形成される高耐圧素子と高速素子とを含む
ものにおいて、絶縁膜の厚さが均一でなく、高耐圧素子
の形成される半導体基板と支持基板との間の絶縁膜が印
加電圧が高くなる部分で厚くされたことを特徴とする複
合素子。
1. A high withstand voltage element formed on a semiconductor substrate insulated by the same supporting substrate and an insulating film, wherein the high withstand voltage element is not uniform and the high withstand voltage element is formed. A composite element characterized in that an insulating film between a semiconductor substrate and a supporting substrate is thickened in a portion where an applied voltage is high.
【請求項2】素子の形成される半導体基板と支持用半導
体基板とからなる貼り合わせ基板の製造方法において、
支持用半導体基板の一面上に加工により凹部を形成した
のち、その凹部を埋める厚い部分を有する酸化膜により
この面を覆い、その酸化膜と素子用半導体基板の一面を
覆う酸化膜とを重ね合わせ、熱処理により接着すること
を特徴とする貼り合わせ基板の製造方法。
2. A method for manufacturing a bonded substrate comprising a semiconductor substrate on which elements are formed and a supporting semiconductor substrate,
After forming a recess on one surface of the supporting semiconductor substrate by processing, cover this surface with an oxide film having a thick portion filling the recess, and superimpose the oxide film and the oxide film covering one surface of the device semiconductor substrate. A method for manufacturing a bonded substrate, which comprises bonding by heat treatment.
【請求項3】重ね合わせる前に、支持用半導体基板一面
上の酸化膜の表面に水素基を結合させ、素子用半導体基
板一面上の酸化膜の表面に水酸基を結合させる請求項2
記載の貼り合わせ基板の製造方法。
3. Prior to stacking, a hydrogen group is bonded to the surface of the oxide film on the one surface of the supporting semiconductor substrate, and a hydroxyl group is bonded to the surface of the oxide film on the one surface of the device semiconductor substrate.
A method for manufacturing the bonded substrate as described.
【請求項4】支持用半導体基板の一面上の酸化膜表面を
ドライエッチングしたのち、光励起により活性化した水
素を接触させることにより、前記酸化膜の表面に水素基
を結合させる請求項3記載の貼り合わせ基板の製造方
法。
4. The surface of an oxide film on one surface of a supporting semiconductor substrate is dry-etched, and then hydrogen activated by photoexcitation is brought into contact with the surface of the oxide film to bond a hydrogen group. Manufacturing method of bonded substrate.
JP03512694A 1994-03-07 1994-03-07 Method for manufacturing composite element and bonded substrate Expired - Lifetime JP3298291B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03512694A JP3298291B2 (en) 1994-03-07 1994-03-07 Method for manufacturing composite element and bonded substrate

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Application Number Priority Date Filing Date Title
JP03512694A JP3298291B2 (en) 1994-03-07 1994-03-07 Method for manufacturing composite element and bonded substrate

Publications (2)

Publication Number Publication Date
JPH07245382A true JPH07245382A (en) 1995-09-19
JP3298291B2 JP3298291B2 (en) 2002-07-02

Family

ID=12433247

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041590A1 (en) * 1996-04-26 1997-11-06 Sumitomo Sitix Corporation Method for joining silicon semiconductor substrate
US6992363B2 (en) 2002-12-19 2006-01-31 Mitsubishi Denki Kabushiki Kaisha Dielectric separation type semiconductor device and method of manufacturing the same
JP2006156858A (en) * 2004-12-01 2006-06-15 Shin Etsu Chem Co Ltd Silicon substrate with oxide film and its manufacturing method
JP2009260503A (en) * 2008-04-14 2009-11-05 Sharp Corp Light-receiving amplifier element, optical pickup, and optical disk recording and reproducing device equipped with the same
WO2016021304A1 (en) * 2014-08-05 2016-02-11 株式会社村田製作所 Method for manufacturing piezoelectric resonator, and piezoelectric resonator

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JPS63205909A (en) * 1987-02-23 1988-08-25 Nippon Telegr & Teleph Corp <Ntt> Junction method of semiconductor substrate
JPH01137652A (en) * 1987-11-24 1989-05-30 Fujitsu Ltd Plate bonding
JPH027467A (en) * 1988-06-24 1990-01-11 Sony Corp Manufacture of semiconductor device
JPH05198549A (en) * 1991-08-26 1993-08-06 Nippondenso Co Ltd Manufacture of semiconductor substrate

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
JPS49130691A (en) * 1973-04-13 1974-12-14
JPS61294846A (en) * 1985-06-20 1986-12-25 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Manufacture of semiconductor device
JPS63205909A (en) * 1987-02-23 1988-08-25 Nippon Telegr & Teleph Corp <Ntt> Junction method of semiconductor substrate
JPH01137652A (en) * 1987-11-24 1989-05-30 Fujitsu Ltd Plate bonding
JPH027467A (en) * 1988-06-24 1990-01-11 Sony Corp Manufacture of semiconductor device
JPH05198549A (en) * 1991-08-26 1993-08-06 Nippondenso Co Ltd Manufacture of semiconductor substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041590A1 (en) * 1996-04-26 1997-11-06 Sumitomo Sitix Corporation Method for joining silicon semiconductor substrate
US6992363B2 (en) 2002-12-19 2006-01-31 Mitsubishi Denki Kabushiki Kaisha Dielectric separation type semiconductor device and method of manufacturing the same
JP2006156858A (en) * 2004-12-01 2006-06-15 Shin Etsu Chem Co Ltd Silicon substrate with oxide film and its manufacturing method
JP4603865B2 (en) * 2004-12-01 2010-12-22 信越化学工業株式会社 Manufacturing method of silicon substrate with oxide film and silicon substrate with oxide film
JP2009260503A (en) * 2008-04-14 2009-11-05 Sharp Corp Light-receiving amplifier element, optical pickup, and optical disk recording and reproducing device equipped with the same
WO2016021304A1 (en) * 2014-08-05 2016-02-11 株式会社村田製作所 Method for manufacturing piezoelectric resonator, and piezoelectric resonator
JPWO2016021304A1 (en) * 2014-08-05 2017-04-27 株式会社村田製作所 Method for manufacturing piezoelectric resonator and piezoelectric resonator
US10560065B2 (en) 2014-08-05 2020-02-11 Murata Manufacturing Co., Ltd. Piezoelectric resonator manufacturing method and piezoelectric resonator

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