KR100268800B1 - Method for manufacturing junction type soi substrates - Google Patents
Method for manufacturing junction type soi substrates Download PDFInfo
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- KR100268800B1 KR100268800B1 KR1019970027716A KR19970027716A KR100268800B1 KR 100268800 B1 KR100268800 B1 KR 100268800B1 KR 1019970027716 A KR1019970027716 A KR 1019970027716A KR 19970027716 A KR19970027716 A KR 19970027716A KR 100268800 B1 KR100268800 B1 KR 100268800B1
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 title abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims description 21
- 238000004140 cleaning Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 241000252506 Characiformes Species 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005304 joining Methods 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 50
- 239000003990 capacitor Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 5
- 238000005498 polishing Methods 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000011800 void material Substances 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 2
- 238000003795 desorption Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000005661 hydrophobic surface Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 150000003018 phosphorus compounds Chemical class 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
Description
본 발명은 반도체용 기판의 제조 방법에 관한 것으로, 특히 접합형 SOI(Silicon-On-Insulator)기판의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a bonded silicon-on-insulator (SOI) substrate.
SOI형 기판을 제조하기 위한 방법으로는 여러가지 형태가 있으나 그 중의 하나로 접합에 의한 방법이 있다.There are various methods for manufacturing an SOI type substrate, but one of them is a method by bonding.
상기 접합에 의한 방법은 두 장의 웨이퍼를 접합한 후, 후면 연마(back-grinding)와 식각을 통해 수 ㎛까지 씨닝(thinning)공정을 진행한 뒤, 최종적으로 화학기계적 연마를 통해 소자 형성을 위한 얇은 실리콘층을 얻는 방법이다.In the bonding method, two wafers are bonded to each other, followed by a thinning process up to several μm through back-grinding and etching, and finally a thin layer for forming a device through chemical mechanical polishing. It is a method of obtaining a silicon layer.
특히 상기 2 장의 웨이퍼를 접합시킬 경우, 상온에서 접촉시키면서 상부에서 가볍게 압력을 가하면 반데르 바알스(Vander Walls)힘에 의해 접합이 이루어지고, 또한 접합강도를 증가시키기 위해 후속적인 고온 열처리를 가해준다.In particular, when the two wafers are bonded together, lightly pressurized at the top while contacting at room temperature, the bonding is performed by Vander Walls force, and subsequent high temperature heat treatment is applied to increase the bonding strength. .
그러나 상기 웨이퍼 접합시 웨이퍼 표면상태나 파티컬(Particle) 등에 따라 접합이 잘되지 않고 보이드(Void)가 발생하게 된다.However, when the wafer is bonded, voids are generated without bonding well depending on the wafer surface state or particles.
상기 보이드의 발생 여부는 웨이퍼간에 접합이 이루어질 경우 웨이퍼 접촉(Contact) 속도에 따라서도 좌우된다.Whether the void is generated also depends on the wafer contact speed when the bonding is performed between the wafers.
또한 SOI 기판을 제조하는 방법으로 무공정 웨이퍼(bare wafer)를 열산화법을 이용하여 열산화막을 형성시킨 다음, 이를 또 다른 무공정 웨이퍼와 접합하여 패턴이 없는 SOI 웨이퍼를 제조하는 방법이 있다.In addition, a method of manufacturing an SOI substrate includes a method of manufacturing a SOI wafer without a pattern by forming a thermal oxide film on a bare wafer using a thermal oxidation method, and then bonding it to another unprocessed wafer.
상기의 방법보다 약간 진보된 방법으로, 접합전 소자 분리에 사용되는 필드산화막을 형성시키고, 집적공정중 문제가 될수 있는 토폴로지를 유발하는 캐패시터를 형성시킨 다음, 화학 증착 연마법(Chemical Mechanical Polishing : 이하 CMP법이라 칭함.) 등을 이용하여 평탄화시킨 뒤, 지지 웨이퍼(supporting wafer)와 접합하는 방법을 채택하고 있다.Slightly more advanced than the above method, a field oxide film used for device isolation is formed, and a capacitor causing a topology which may be a problem during the integration process is formed, followed by chemical mechanical polishing. After the planarization using a CMP method, etc.), a method of joining with a supporting wafer is adopted.
상기의 방법을 채택할 경우, 접합면으로 사용되는 표면이 어떤 막이나 층으로 드러나 있는지에 영향을 받게 되는데, 특히 화학증착법을 이용하여 형성시킨 화학 증착 산화막의 경우, 증착에 사용된 원물질(precusor)에 따라 후속 열처리중 탈착되어 접합특성을 악화시켜 접합강도를 떨어뜨리는 물질을 막 중에 유발시킬 수있다. 이로 인해 접합하여 얇은 실리콘층을 얻기 위한 후속 씨닝(thinning) 공정시에 낮은 접합강도로 인해 웨이퍼가 깨지거나 웨이퍼에 응력을 줄 수 있다.When the above method is adopted, it is influenced by which film or layer the surface used as the bonding surface is exposed. In particular, in the case of the chemical vapor deposition oxide formed by chemical vapor deposition, the raw material used for the deposition (precusor) May desorb during the subsequent heat treatment to deteriorate the bonding properties and cause materials in the film to degrade the bonding strength. This can result in cracking or stressing the wafer due to low bonding strength in subsequent thinning processes to bond and obtain a thin silicon layer.
통상, 접합전 두 웨이퍼의 표면에 증착되어 있는 증착 산화막 중 가장 많이 사용되고 있는 것은 BPSG 인데, 상기와 같은 탈착물질을 최소화하기 위해 BPSG 증착시 사용되는 보론과 인의 농도를 줄임으로써 이와 같은 문제점을 해결하는 방법이있다.In general, BPSG is the most commonly used deposition oxide film deposited on the surfaces of two wafers before bonding, and this problem is solved by reducing the concentrations of boron and phosphorus used in BPSG deposition to minimize the desorption material. There is a way.
그러나 상기의 방법은 보론과 인의 농도를 낮추기 때문에 증착후 플로우(flow) 시키는 단계에서 점도가 증가하게 되므로 플로우 특성을 개선시키기 위해 플로우 시간 또는 온도를 올려 주어야 하기 때문에 열이력(thermal budget)을 많이 받게 된다는 단점이 있다. 또한 보론과 인의화합물 형태가 아닌 제 3의 탈착 물질의 발생에는 효과적이지 못하다.However, since the method reduces the concentrations of boron and phosphorus, the viscosity increases during the post-deposition flow, so that the flow time or temperature must be increased to improve the flow characteristics. It has the disadvantage of being. It is also not effective for the generation of third desorbents that are not in the form of boron and phosphorus compounds.
특히 테오스(TEOS)를 사용하는 경우에는 이러한 경향이 뚜렷하다. 예컨데, BPSG에서 탈착되어 나오는 물질의 분석을 열탈착 분석법(TDS : Thermal Deposition Spectroscopy)으로 분석한 데이터에 의하면, 상당한 양의 다양한 물질이 탈착되어 나옴을 알 수 있으며, 상기의 사실은 보론과 인의 농도만을 낮추는 것으로는 탈착물질에 의한 공극발생을 억제하기가 어려워 결국, 보이드의 발생이 많아지게 된다.This tendency is especially evident when using TEOS. For example, the data of the desorption of BPSG by thermal desorption spectroscopy (TDS) shows that a large amount of various substances desorbed. By lowering it, it is difficult to suppress the generation of voids due to the desorbing material, and eventually, the generation of voids increases.
상기 보이드가 일단 한 번 발생하게 되면, 보이드중 미세한 보이드는 고온열처리시 트랩(trap)된 가스가 방출됨에 따라 사라지나 큰 보이드는 제거되지 않아 후속적인 웨이퍼 씨닝공정에서 드러나게 되어 웨이퍼 접합강도를 떨어뜨리게 되는요인으로 작용하는 문제점이 있다.Once the voids are generated once, the fine voids in the voids disappear as the trapped gas is released during the high temperature heat treatment, but the large voids are not removed and are revealed in the subsequent wafer thinning process to reduce the wafer bonding strength. There is a problem that acts as a factor.
따라서 본 발명은 상기한 문제점을 해결하기 위한 것으로, 베어 지지 웨이퍼 상부면 또는 상기 지지 웨이퍼와 접합하는 씨드 웨이퍼의 상부면에 소정두께의 화학 증착 산화막을 형성한 다음, 일정 조건하에서 접합전 열처리를 실시하고, CMP공정으로 평탄화를 실시한 다음, 곧바로 상온에서 접합을 실시하고, 다시 열처리 공정을 실시하는 단계로 진행하여 SOI웨이퍼를 접합시 보이드의 발생을 억제하여 접합특성을 향상시킴으로 웨이퍼 제조수율의 향상 및 반도체 소자의 신뢰성을 향상시킬 수 있는 접합용 SOI 웨이퍼 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above problems, a chemical vapor deposition oxide film of a predetermined thickness is formed on the top surface of the bare support wafer or the top surface of the seed wafer to be bonded to the support wafer, and then subjected to pre-bonding heat treatment under a certain condition. After the planarization by the CMP process, the process is performed at room temperature immediately, and then the heat treatment process is performed again to suppress the generation of voids when the SOI wafer is bonded, thereby improving the bonding properties and improving the wafer manufacturing yield. It is an object of the present invention to provide a method for manufacturing a SOI wafer for bonding, which can improve the reliability of a semiconductor device.
제1도는 접합전 지지 웨이퍼와 씨드 웨이퍼의 단면 상태를 도시한 도면.1 is a cross-sectional view of a support wafer and seed wafer before bonding;
제2a도와 제2b도는 열처리 공정 후, 증착된 화학 증착 산화막을 평탄화하기 위한 CMP 공정을 실시하기 전과 후의 단면상태를 도시한 도면.2A and 2B show cross-sectional states after a heat treatment process and before and after a CMP process for planarizing the deposited chemical vapor deposition oxide film.
제3도는 접합이 완료된 SOI 기판을 도시한 단면도.3 is a cross-sectional view illustrating a SOI substrate on which bonding is completed.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11,31 : 실리콘 기판 13,35 : 화학 증착 산화막11,31
32 : 필드 산화막 33 : 캐패시터32: field oxide film 33: capacitor
상기 목적을 달성하기 위해 본 발명에 따른 접합형 SOI 기판 제조방법은, 지지웨이퍼 상부에 소정 두께의 제1절연막을 형성하는 공정과, 소정의 하부구조물이 구비되어 있는 씨드웨이퍼 상부에 제2절연막을 형성하는 단계와, 상기 제1절연막 및 제2절연막 내의 불순물을 탈착시키는 제1열처리공정을 실시하는 단계와, 상기 제2절연막을 CMP 공정으로 평탄화시키는 단계와, 세정공정을 실시하여 상기 평탄화된 제2절연막의 표면을 친수화시키는 공정과, 상기 제1절연막과 상기 평탄화된 제2절연막의 표면이 접합계면이 되도록 상기 지지 웨이퍼와 씨드 웨이퍼를 접합시키는 단계와, 상기 접합된 웨이퍼를 제2열처리하는 단계로 구성되는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a bonded SOI substrate according to the present invention includes forming a first insulating film having a predetermined thickness on an upper side of a support wafer, and forming a second insulating film on a seed wafer having a predetermined lower structure. Forming, performing a first heat treatment step of desorbing impurities in the first insulating film and the second insulating film, planarizing the second insulating film by a CMP process, and performing a cleaning process to perform the planarizing agent. 2) hydrophilizing the surface of the insulating film, bonding the support wafer and the seed wafer so that the surface of the first insulating film and the planarized second insulating film are a bonding interface, and performing a second heat treatment of the bonded wafer. Characterized in that consists of.
한편, 상기 본 발명의 기술적 원리에 대한 이해를 돕기위해 부가적으로 기술하면 아래와 같다.On the other hand, if described additionally to help understand the technical principle of the present invention as follows.
접합에 사용되는 두 웨이퍼의 양쪽표면 또는 한쪽 표면이 화학증착법으로 증착된 산화막으로 이루어져 있을 경우, 접합전 증착 산화막에 대한 선열처리(pre-heat treatment)를 통해 접합 후 접합강도 증가를 위해 실시하는 열처리 공정중 탈착되어 나올 수 있는 물질들에 선행탈착(pre-deposition) 과정을 통해 접합 후 이러한 탈착 물질에 의한 공극(보이드 또는 버블)을 줄이는 방법을 사용한다.When both surfaces or one surface of two wafers used for bonding are composed of an oxide film deposited by chemical vapor deposition, heat treatment is performed to increase the bonding strength after bonding through pre-heat treatment of the deposited oxide film before bonding. A method of reducing voids (voids or bubbles) caused by these desorption materials after bonding is performed by pre-deposition to materials that may come out during the process.
반도체 소자 제조 공정에서 가장 많이 사용되는 화학 증착 산화막의 경우인 BPSG의 경우에는 대부분 산화막을 증착한 뒤, 평탄화 특성을 향상시키고 막의 특성을 향상시키기 위해 후속 열처리를 통해 플로우를 시켜 주지만 대부분의 플로우 온도와 시간하에서는 이러한 탈착이 불완전하게 이루어지게 되고 이로 인해 후속공정에서 이루어지는 접합 후 열처리 공정에서 탈착되어 나옴으로써 접합 특성을 나쁘게 하는 결과를 낳게 되므로 BPSG의 경우에는 증착 후 적절한 온도와 시간하에서 플로우를 진행함으로써 이러한 문제점을 해결할 수 있게 된다.In the case of BPSG, which is the most commonly used chemical vapor deposition oxide film in the semiconductor device manufacturing process, most of the oxide film is deposited and then flowed through subsequent heat treatment to improve planarization characteristics and film characteristics. Under time, such desorption is incomplete, which leads to deterioration of the bonding properties by desorption in the post-bonding heat treatment process, which is performed in a subsequent process. The problem can be solved.
상기와 같이 함으로써 다른 화학 증착 산화막의 경우와는 달리 탈착만을 위한 열처리 과정이 따로 이루어지지 않기 때문에 공정상으로도 상당히 유리하다. 평판의 경우에는 상기와 같은 처리 후 공극의 발생을 억제키 위한 다양한 표면 친수화 처리를 실시한 뒤 접합을 하고, 열처리 과정을 통해 접합강도를 증가시켜 주며, 패턴이 형성되어 있는 웨이퍼의 경우에는 이러한 선탈착 열처리 공정 이외에 패턴의 형성으로 인해 발생한 단차를 CMF 공정을 통해 제거하여야만 단차에 의한 공극의 발생을 억제할 수 있다. 부가적으로 설명하면, 접합 전 필드 산화막을 형성시킨 뒤 캐패시터를 형성한 패턴 웨이퍼의 경우에는 필드 산화막에 의한 단차에 캐패시터 형성에 의한 단차가 추가되므로 단차 제거를 위한 CMP 공정은 필수적이다. 대부분의 장비는 이와 같은 CMP 연마 후, 웨이퍼의 세정을 위한 후속 세정장비가 있는 데, 이러한 후속 세정을 통해 표면을 친수성이 되도록 한 다음, 접합을 함으로써 소수성 표면으로 인한 접합 후 공극의 발생을 막을 수 있다.As described above, unlike the case of other chemical vapor deposition oxide film, since the heat treatment process for desorption is not performed separately, it is also advantageous in terms of process. In the case of a flat plate, after performing the above-described treatment, various surface hydrophilization treatments are performed to suppress the generation of voids, and then bonded, and the bonding strength is increased through a heat treatment process. In addition to the desorption heat treatment process, steps generated due to the formation of a pattern must be removed through a CMF process to prevent generation of voids due to steps. In addition, in the case of the pattern wafer in which the capacitor is formed after the field oxide film is formed before the bonding, the step by the capacitor formation is added to the step by the field oxide film, and thus a CMP process for removing the step is essential. Most of the equipment has a subsequent cleaning equipment for cleaning the wafer after such CMP polishing, which makes the surface hydrophilic and then joins to prevent the formation of post-bonding voids due to the hydrophobic surface. have.
이하, 첨부된 도면을 참조하여 본 발명에 따른 접합형 SOI 기판 제조방법의 일실시예에 대하여 상세히 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of a bonded SOI substrate manufacturing method according to the present invention.
도 1은 접합전 지지 웨이퍼와 씨드 웨이퍼의 단면 상태를 도시한 도면으로서, 지지 웨이퍼(11)상부에 화학 증착 산화막(13)을 형성시킨 상태를 도시하고 있다. 한편, 접합전의 단계에서 상기 화학 증착 산화막(13)을 지지 웨이퍼(11)와 씨드웨이퍼(31) 모두에 형성할 수 있으며, 이때 상기 씨드 웨이퍼(11) 상에는 도시된 바와 같이, 필드 산화막(32), 캐패시터(33)와 같은 패턴들이 형성되고, 그 상부에 화학 증착 산화막(35)이 형성된다.FIG. 1 is a view showing a cross-sectional state of the support wafer and the seed wafer before bonding, and shows a state in which a chemical vapor
상기 화학 증착 산화막(35) 형성시 그 두께는 500∼10,000Å로 하고, 350∼450℃에서 화학기상증착법으로 증착한다.When the chemical vapor
또한 상기 화학 증착 산화막(35)은 PE-TEOS, SiH4, BSG, BPSG, PSG 산화막중 어느 하나를 사용할 수 있다.In addition, the chemical
다음, 접합전 탈착 과정을 위해 O2, N2분위기하에서 650℃∼1050℃의 온도 범위내에서 소정시간 예컨데 30분 내지 2시간 동안 열처리를 실시한다.Next, heat treatment is performed for a predetermined time, for example, 30 minutes to 2 hours in a temperature range of 650 ° C. to 1050 ° C. under an O 2 , N 2 atmosphere for desorption before bonding.
상기 열처리 공정 후, 증착된 화학 증착 산화막을 평탄화하기 위한 CMP 공정을 실시하여 단차를 제거한다.(도 2a, 2b 참조)After the heat treatment step, a CMP process for planarizing the deposited chemical vapor deposition oxide film is performed to remove the step (see FIGS. 2A and 2B).
이때 평판 웨이퍼의 경우에는 CMP 공정을 실시하지 않고 표면의 친수화를 위해 피라나 세정 또는 SC-1 세정을 실시하거나, SC-1 세정과 피라나세정을 1개의 연속레시피 내에 포함시킬 수도 있다.In this case, in the case of the flat wafer, the Pyranha cleaning or the SC-1 cleaning may be performed for the surface hydrophilization without performing the CMP process, or the SC-1 cleaning and the Piranha cleaning may be included in one continuous recipe.
다음, 상기 열처리된 두개의 웨이퍼(11,31)를 증착된 화학 증착 산화막(13,33)을 접합계면으로 하여 상온에서 접합을 실시한다.Next, the heat-treated two
이때 상기 접합시에는 10-4∼10-6torr의 진공하에서 상온에서 실시한다.(도 3참조)At this time, the bonding is carried out at room temperature under a vacuum of 10 -4 to 10 -6 torr (see Fig. 3).
한편, 상기 본 발명의 방법에 따라 접합에 사용되는 두 웨이퍼는 그 표면에 모두 화학 증착 산화막인 경우에도 적용할 수 있으며, 특히 산화막의 종류가 서로 다른 경우에도 적용할 수 있고, 평판형 웨이퍼 뿐만 아니라 패턴이 형성된 웨이퍼에도 적용할 수 있다.On the other hand, the two wafers used for bonding according to the method of the present invention can be applied to the case of both chemical vapor deposition oxide film on the surface, in particular in the case of different types of oxide film, as well as a flat wafer It can also be applied to a wafer on which a pattern is formed.
접합형 SOI 기판의 제조시, 얇은 두께 예컨데, 약 0.1∼0.2㎛의 얇은 실리콘층을 얻기 위해서는 여러가지 씨닝 공정을 실시하게 되는데, 이러한 씨닝 공정 진행시 웨이퍼가 깨어지지 않도록 하기 위해서는 접합계면에 공극이 존재하지 않아야하며, 후속 열처리 공정을 통해 접합강도를 증가시켜 주어야 한다. 상술한 본 발명의 방법에서와 같이, 접합할 예정인 한개 또는 두 개의 웨이퍼 접합면에 화학 증착 산화막을 증착함에 의해 접합면에 존재하는 공극을 줄임으로써, 공정의 안정화와 반도체 소자 제조에 따른 수율향상 및 소자의 신뢰성을 향상시킬 수 있다.In the manufacture of a bonded SOI substrate, various thinning processes are performed to obtain a thin silicon layer having a thickness of about 0.1 to 0.2 μm. In order to prevent the wafer from breaking during the thinning process, voids exist in the bonding interface. The strength of the bond should be increased by subsequent heat treatment. As in the method of the present invention described above, by reducing the voids present in the bonding surface by depositing a chemical vapor deposition oxide on one or two wafer bonding surfaces to be bonded, the stabilization of the process and the yield improvement according to the semiconductor device manufacturing and The reliability of the device can be improved.
Claims (11)
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