JPS63205909A - Junction method of semiconductor substrate - Google Patents
Junction method of semiconductor substrateInfo
- Publication number
- JPS63205909A JPS63205909A JP3979187A JP3979187A JPS63205909A JP S63205909 A JPS63205909 A JP S63205909A JP 3979187 A JP3979187 A JP 3979187A JP 3979187 A JP3979187 A JP 3979187A JP S63205909 A JPS63205909 A JP S63205909A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon substrate
- substrate
- substrates
- type silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 title claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 72
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 72
- 239000010703 silicon Substances 0.000 claims abstract description 72
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000011261 inert gas Substances 0.000 claims description 6
- 239000007789 gas Substances 0.000 abstract description 5
- 239000001307 helium Substances 0.000 abstract description 3
- 229910052734 helium Inorganic materials 0.000 abstract description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 8
- 125000004429 atom Chemical group 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000005304 joining Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000009864 tensile test Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多数枚の半導体基板を接合する多層基板の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer substrate in which a large number of semiconductor substrates are bonded together.
２個の金属部品を接合する方法として、現在までに多種
多様な接合法が実用化されている。それらの中の一つと
して拡散接合法がある。通常、拡散接合は接合面が酸化
しないように真空中あるいはアルゴンガス中で加熱加圧
することにより行われている。拡散接合は、平滑で清浄
な面どうしを接触させ、接触面間に凝集力が働くまで両
面を接触させればよいと考えられている。しかし、一般
に金属の弐面には凹凸がちシ、また、酸化被膜があるた
めに、接合する面を接近させるのは非常にむずかしい。As a method for joining two metal parts, a wide variety of joining methods have been put into practical use to date. One of them is the diffusion bonding method. Diffusion bonding is usually performed by heating and pressurizing in vacuum or argon gas to prevent oxidation of the bonding surfaces. Diffusion bonding is thought to be achieved by bringing smooth, clean surfaces into contact with each other until a cohesive force is exerted between the contact surfaces. However, since the second side of metal is generally uneven and has an oxide film, it is extremely difficult to bring the surfaces to be joined close together.
そこで、圧力を加え、また熱を加えることによシ酸化被
膜を消失させ、かつ、接合面を近接させている。Therefore, by applying pressure and heat, the silicon oxide film is removed and the bonding surfaces are brought closer together.
一般の金属では圧力を加えた場合に金属内部に生ずる応
力による欠陥は問題にならないが、半導体基板の場合、
内部応力によシ容易に欠陥（格子欠陥）を生じ半導体基
板として使用できない状態となる。このために、従来、
半導体基板を拡散接合によシ接合することは不可能であ
ると考えられていた。In general metals, defects caused by the stress that occurs inside the metal when pressure is applied are not a problem, but in the case of semiconductor substrates,
Internal stress easily causes defects (lattice defects), making it unusable as a semiconductor substrate. For this purpose, conventionally
It was considered impossible to bond semiconductor substrates by diffusion bonding.
本発明は、加圧することなく、また、従来、不要なもの
と考えられていた酸化被膜を利用することによシ、半導
体基板の接合を可能としたものであるＯ
〔問題点を解決するための手段及び発明の構成〕本発明
は接合する面に存在する酸化被膜中のＯｘ原子が半導体
基板中に拡散することによシ、酸化被膜の下の平滑でか
つ清浄な面が現われ、接合することを特徴とするもので
ある。従来技術における加圧下の接合法では、格子欠陥
が発生し易く使用にたえない基板となる。従来の拡散接
合のような圧力を加えることなく、また、真空中でなく
ても格子欠陥のない接合処理が可能で、さらに、接合面
を清浄にするための処理が不要であることが従来の技術
とは異なる。The present invention makes it possible to bond semiconductor substrates without applying pressure and by using an oxide film, which was conventionally thought to be unnecessary. [Means and Structure of the Invention] The present invention allows oxygen atoms in the oxide film existing on the surface to be bonded to diffuse into the semiconductor substrate, thereby revealing a smooth and clean surface under the oxide film and bonding. It is characterized by this. In the conventional bonding method under pressure, lattice defects are likely to occur, resulting in a substrate that is unusable. Unlike conventional diffusion bonding, bonding without lattice defects can be achieved without applying pressure or in a vacuum, and there is no need to clean the bonding surface. It is different from technology.
第１図は本発明の第一の実施例を説明する図であって、
１はＰ形のシリコン基板、２はＮ形のシリコン基板、３
はＰ形のシリコン基板１の表面の薄い酸化被膜、４はＮ
形のシリコン基板２の表面の薄い酸化被膜、５はヘリウ
ムガス、６は加熱ヒーターである。FIG. 1 is a diagram illustrating a first embodiment of the present invention,
1 is a P-type silicon substrate, 2 is an N-type silicon substrate, 3
is a thin oxide film on the surface of P-type silicon substrate 1, and 4 is N
5 is helium gas, and 6 is a heater.
Ｐ形のシリコン基板１とＮ形のシリコン基板２とを重ね
合せ、不活性ガスであるヘリウムガス５中で保持し、加
熱ヒータ６で加熱することにょシ、薄い酸化被膜３およ
び４の中の０２原子がＰ形シリコン基板１およびＮ形シ
リコン基板２の中に拡散し、薄い酸化被膜３および４は
消失する。これによシＰ形シリコン基板１およびＮ形シ
リコン基板２の清浄面が現われ、Ｐ形シリコン基板１と
Ｎ形シリコン基板２は接合する。加熱ヒータ６による加
熱温度と接合する時間とはある種の関係が成シ立ち、加
熱温度１３００℃で約２時間、加熱温度９００℃では約
２５０時間が必要である。A P-type silicon substrate 1 and an N-type silicon substrate 2 are placed on top of each other, held in helium gas 5, which is an inert gas, and heated with a heater 6. The 02 atoms diffuse into the P-type silicon substrate 1 and the N-type silicon substrate 2, and the thin oxide films 3 and 4 disappear. This exposes the clean surfaces of the P-type silicon substrate 1 and the N-type silicon substrate 2, and the P-type silicon substrate 1 and the N-type silicon substrate 2 are joined. A certain relationship is established between the heating temperature by the heater 6 and the bonding time; at a heating temperature of 1300°C, approximately 2 hours are required, and at a heating temperature of 900°C, approximately 250 hours are required.
Ｐ形シリコン基板１とＮ形シリコン基板２とが接合する
ことにより、Ｐ−Ｈのトランジスタを形成した基板が得
られる。従来、この種の基板を製造するためには、１枚
のシリコン基板の上面および下面よシ拡散あるいはイオ
ン注入することによシ形成していた。このために均一に
拡散あるいは注入できない。Ｐ形とＮ形の境界面が一定
でない。By joining the P-type silicon substrate 1 and the N-type silicon substrate 2, a substrate on which a P-H transistor is formed is obtained. Conventionally, in order to manufacture this type of substrate, it has been formed by diffusion or ion implantation from the upper and lower surfaces of a single silicon substrate. For this reason, uniform diffusion or injection is not possible. The boundary surface between P type and N type is not constant.
などの欠点があ、９、Ｐ−Ｎ）ランジスタを形成しても
、基板の各所で均一な特性を得ることは困難であった。9. Even if transistors are formed, it is difficult to obtain uniform characteristics at various locations on the substrate.
本発明では、均一な特性のＰ形シリコンおよびＮ形シリ
コンを接合するので均一な特性のＰ−Ｎシ−リコン基板
を得ることが出来るという利点がある。The present invention has the advantage that since P-type silicon and N-type silicon having uniform characteristics are bonded, a P-N silicon substrate having uniform characteristics can be obtained.
なお、本発明の接合の基となる酸化被膜中の０２原子が
シリコン中に拡散し、酸化被膜が消失する現象について
は実験的に見い出した新しい現象である０
第２図は本発明の第２の実施例であって、１０はＰ形シ
リコン基板、１１はＮ形シリコン基板、１２はＰ形シリ
コン基板、１３はＰ形シリコン基板１０の表面の薄い酸
化被膜、１４はＮ形シリコン基板１１の表面の薄い酸化
被膜、１５はＰ形シリコン基板１２の表面の薄い酸化被
膜である。このように３層に重ねたものを不活性ガス中
で加熱することによシ、酸化被膜１３ 、１４ 、１５
の中の０１原子がＰ形シリコン基板１０、Ｎ形シリコン
基板１１およびＰ形シリコン基板１２の中に拡散し、Ｐ
形シリコン基板１０とＮ形シリコン基板１１およびＮ形
シリコン基板１１とＰ形シリコン基板１２が接合するこ
とによりＰ−Ｎ−Ｐ接合を形成する基板が得られる。The phenomenon in which the 02 atoms in the oxide film, which forms the basis of the bonding of the present invention, diffuse into silicon and the oxide film disappears is a new phenomenon discovered experimentally. 10 is a P-type silicon substrate, 11 is an N-type silicon substrate, 12 is a P-type silicon substrate, 13 is a thin oxide film on the surface of the P-type silicon substrate 10, and 14 is a thin oxide film on the surface of the N-type silicon substrate 11. A thin oxide film 15 on the surface is a thin oxide film on the surface of the P-type silicon substrate 12. By heating the three layers stacked in this way in an inert gas, oxide films 13, 14, 15 are formed.
01 atoms in the P type silicon substrate 10, N type silicon substrate 11 and P type silicon substrate 12 diffuse into P type silicon substrate 10, N type silicon substrate 11 and P type silicon substrate 12.
By joining the N-type silicon substrate 10 and the N-type silicon substrate 11 and the N-type silicon substrate 11 and the P-type silicon substrate 12, a substrate forming a P-N-P junction is obtained.
なお、酸化被膜の厚さが厚いと０１原子が拡散し、清浄
４面が現われるまでに時間を要するので酸化被膜は出来
る限り薄い方がよい。清浄な大気中でシリコン基板を放
置するとその雰囲気条件によって差異はあるがシリコン
基板表面に１０〜数１ｏｏＸ位の酸化膜が出来るがこの
位の薄さの膜の方が熱処理によシ付着する酸化膜よシも
薄く、接合には都合が良い。Note that if the oxide film is thick, the 01 atoms will diffuse and it will take time for the four clean surfaces to appear, so it is better to make the oxide film as thin as possible. When a silicon substrate is left in a clean atmosphere, an oxide film of about 10 to several 100X is formed on the surface of the silicon substrate, although this varies depending on the atmospheric conditions. The film is thin and is convenient for bonding.
また、酸素雰囲気中で加熱し、接合を行なおうとすると
、シリコン基板中に０２原子が拡散し、消失する酸化膜
よυも酸化によシ生成される酸化膜の方の量が多いため
に、接合されにくい。In addition, when attempting to bond by heating in an oxygen atmosphere, 02 atoms diffuse into the silicon substrate, and the amount of oxide film produced by oxidation is larger than that of the oxide film that disappears. , difficult to join.
不活性ガス中で接合することが最良であるが、大気中で
も接合は可能である。Although it is best to bond in an inert gas, bonding is also possible in the atmosphere.
第３図は本発明の第３の実施例であって、艶は第１のシ
リコン基板、２１は厚い酸化被膜、２２は薄い酸化被膜
、囚は第２のシリコン基板、冴は薄いい酸化膜Ｕを有す
る第２のシリコン基板２３と重ね合せ、不活性ガス中で
加熱することにより、薄い酸化膜２２および冴の中のＯ
２原子はシリコン基板中に拡散し、この部分は接合する
。しかし、厚い酸化膜２１の部分は酸化被膜が残シ、接
合しない。FIG. 3 shows a third embodiment of the present invention, where gloss is the first silicon substrate, 21 is the thick oxide film, 22 is the thin oxide film, the bottom is the second silicon substrate, and the dull oxide film is the thin oxide film. The thin oxide film 22 and the O in the substrate are stacked on the second silicon substrate 23 having U and heated in an inert gas.
The two atoms diffuse into the silicon substrate and this portion is bonded. However, the oxide film remains on the thick oxide film 21, and no bonding occurs.
従って、接合し、導通した部分と酸化被膜が残り、絶縁
抵抗となった部分とを有する基板を得ることが出来る。Therefore, it is possible to obtain a substrate having a bonded and electrically conductive portion and a portion where the oxide film remains and has an insulating resistance.
薄い酸化膜と厚い酸化膜とをパターン化しておけばシリ
コンの同一基板上の中に任意のパターンの絶縁抵抗を有
する基板を得ることが出来る。接合した基板の両面に素
子を形成することによシ、多層のＬ８Ｉを製造すること
が出来る。By patterning a thin oxide film and a thick oxide film, a substrate having an arbitrary pattern of insulation resistance can be obtained on the same silicon substrate. By forming elements on both sides of the bonded substrates, a multilayer L8I can be manufactured.
なお、薄い酸化膜は大気中にシリコン基板を放置すれば
自然に形成される。この場合、清浄な空気中に放置する
ことが望ましい。また、厚い酸化膜は薄い酸化膜として
残したい部分にマスクをし、熱酸化炉中で処理すれば、
処理時間あるいは処理温度などの条件を変化させること
によって所定の厚さの酸化膜を得ることが出来る。Note that a thin oxide film is formed naturally if the silicon substrate is left in the atmosphere. In this case, it is desirable to leave it in clean air. In addition, for thick oxide films, mask the areas you want to leave as thin oxide films and process in a thermal oxidation furnace.
An oxide film of a predetermined thickness can be obtained by changing conditions such as processing time or processing temperature.
第４図は第４の実施例であって、（９）はシリコン基板
、３１は薄い酸化膜、北は第１の厚い酸化膜、北は第２
の厚い酸化膜、詞は第３の厚い酸化膜である。あけ第２
のシリコン基板で、あはその表面の薄い酸化膜である。FIG. 4 shows a fourth embodiment, in which (9) is a silicon substrate, 31 is a thin oxide film, north is a first thick oxide film, and north is a second thick oxide film.
The third thick oxide film is the third thick oxide film. Ake 2nd
A is a thin oxide film on the surface of the silicon substrate.
第１の厚い酸化膜３２．第２の厚い酸化膜３３．第３の
厚い酸化膜あけそれぞれ酸化膜厚が違い、（資）のシリ
コン基板を図示していない薄い酸化膜を有する基板と接
合した場合、絶縁抵抗値の異々る基板を得ることが出来
る。First thick oxide film 32. Second thick oxide film 33. The third thick oxide film openings have different oxide film thicknesses, and when the (material) silicon substrate is bonded to a substrate having a thin oxide film (not shown), substrates with different insulation resistance values can be obtained.
なお、薄い酸化膜の厚さは１０〜数１ｏｏＸ、厚い酸化
膜の厚さは絶縁抵抗値によシ定めればよいが、数１００
Ｘ〜１０μｍ位とすればよい。Note that the thickness of a thin oxide film may be determined from 10 to several 100X, and the thickness of a thick oxide film may be determined depending on the insulation resistance value, but it may be several 100X.
It may be approximately X to 10 μm.
以上、説明した実施例では単に多数枚のシリコン基板を
重ね合せ、真全中又は不活性ガス中で接合したが、格子
欠陥が発生しない程度の僅かの（数ｆ程度）で加圧し、
加熱すればよシ密着性よく一層確実な接合が得られる。In the above-described embodiments, a large number of silicon substrates were simply stacked and bonded together in a vacuum or in an inert gas, but the pressure was applied at a small amount (about several f) to the extent that lattice defects did not occur.
By heating, a more secure bond with better adhesion can be obtained.
但し、ここで言う、加圧とは従来のように大きな力を加
えるのではなく、シリコン基板の面と面とが均一に接触
するように加える小さな力である。However, the pressurization mentioned here does not mean applying a large force as in the conventional case, but a small force applied so that the surfaces of the silicon substrates come into uniform contact.
加熱処理は特にクリーンルーム内でなくてもよいが、清
浄な雰囲気中であれば、歩留り、および信頼性の高い接
合が得られるので、出来る限り清浄雰囲気中で加熱する
方がよい。Although the heat treatment does not necessarily have to be carried out in a clean room, it is better to perform the heating in a clean atmosphere as much as possible, since high yield and reliable bonding can be obtained in a clean atmosphere.
シリコン基板の表面精度については一般的な仕上げ精度
、平面度２〜３μｍ以内１表面粗さＲｍａｘ３０久以内
位であれば充分に接合する。Regarding the surface accuracy of the silicon substrate, if the general finishing accuracy is a flatness of 2 to 3 μm or less, and the surface roughness Rmax is within 30 minutes, sufficient bonding will be achieved.
次に本発明によシ形成された接合体の特性について説明
する。Next, the characteristics of the joined body formed according to the present invention will be explained.
１、 Ｐ形基板とｎ形とを接合し、Ｈｅ（ヘリウム）
雰囲気中で１２００℃でＩ時間保持し、Ｐｎ接合ダイオ
ードを形成した。そのダイオードのＩ−Ｖ特性（電流−
電圧特性）を第５図に示す。1. Join the P-type substrate and the N-type substrate, and
The temperature was maintained at 1200° C. for I hours in an atmosphere to form a Pn junction diode. The diode's IV characteristic (current -
Figure 5 shows the voltage characteristics.
２．８ｉ基板の接合強度の実験結果について説明する。The experimental results of the bonding strength of the 2.8i substrate will be explained.
５インチＳｉ基板を短冊状に切断し、本発明方法によシ
接合した。その断面図を第６図に示す。第６図に示す如
く横方向に力を加え引張シ試験を行なった。その特性を
第７図に示す。同図中、曲線工はＩ時間処理した場合、
曲線２は２時間処理した場合を示す。A 5-inch Si substrate was cut into strips and bonded using the method of the present invention. A sectional view thereof is shown in FIG. A tensile test was conducted by applying force in the lateral direction as shown in FIG. Its characteristics are shown in FIG. In the figure, when the curved work is processed for I time,
Curve 2 shows the case of 2 hours of treatment.
次に、本発明のプロセスについて説明する。Next, the process of the present invention will be explained.
本発明において使用するシリコン基板は、通常のＬＳＩ
用のＳｉウエノ・でよい。まず、単結晶ロッドをスライ
シングした後、両面同時ラッピングを施し、さらにエツ
チングを行う。このエツチングによって加工変質層は除
去されているが、凹凸があるので超微粒子をアルカリ液
に懸濁させたコロイダルシリカを用いて無歪の平滑鏡面
ボリシング（湿式メカノケミカルポリＺング）を施す。The silicon substrate used in the present invention is an ordinary LSI
For example, Si Ueno is sufficient. First, after slicing a single crystal rod, both sides are simultaneously wrapped and etched. Although the process-affected layer has been removed by this etching, since there are irregularities, distortion-free and smooth mirror-finishing (wet mechanochemical poly-Zing) is performed using colloidal silica in which ultrafine particles are suspended in an alkaline solution.
この場合、両面をボリンしても、もちろんよい。少なく
とも接合をする面をボリンしなければならない。In this case, it goes without saying that both sides may be covered. At least the surface to be joined must be bolted.
ボリシング後、８ｉウエノ・を洗浄する。この場合、接
合面に塵埃等があると良好な均一接合ができないので、
精密洗浄を行う必要があｊ５、ＬＳＩにおけるクリーン
ルーム内でのＲＣＡ洗浄等が望ましい。After borishing, wash the 8i Ueno. In this case, if there is dust on the bonding surface, good uniform bonding cannot be achieved.
It is necessary to perform precision cleaning, and RCA cleaning in a clean room for LSI is desirable.
洗浄したＳｉウェハは、クリーンルーム等の清浄な雰囲
気内に放置すれば自然酸化膜が形成される・。If the cleaned Si wafer is left in a clean atmosphere such as a clean room, a natural oxide film will form.
次に本発明方法によシつくられた半導体基板の応用につ
いて説明する。Next, applications of the semiconductor substrate manufactured by the method of the present invention will be explained.
ｉ、 ｐ形とＮ形ｓｉ薄片を第８図に図示の如く多層
接合することによってＨｔｏｏｏｖ、数１０人程度のＩ
−Ｖ特性を示す高耐圧のスイッチング素子を得ることが
できる。By joining I, P-type and N-type Si thin slices in multiple layers as shown in Fig. 8, Htooov, several dozen I
A high voltage switching element exhibiting -V characteristics can be obtained.
２、 高電圧・大電力パワートランジスタ従来、拡散・
注入等によシ浅いＰ層、Ｎ層しか形成出来なかったので
、高電圧のパワートランジスタを得ることは困難であっ
た。本発明方法による接合により、任意の深さのＰ４．
Ｎ層を形成することが可能となシ、高電圧のパワートラ
ンジスタの製作が可能となる。2. Conventional high voltage/high power power transistors, diffusion/
Since only shallow P and N layers could be formed by implantation or the like, it was difficult to obtain a high voltage power transistor. By joining according to the method of the present invention, P4.
Since it is possible to form an N layer, it is possible to manufacture a high voltage power transistor.
３、 ＤＩ半導体基板の製造が可能となった。3. It has become possible to manufacture DI semiconductor substrates.
第９図（ａ）に示す半導体基板は、旧基板１と、８１基
板２のＶ溝に多結晶シリコン３を付着させた半導体基板
２とを接合させたものであシ、接合面にはそれぞれ酸化
膜４が設けられた本発明方法によシ接合されている。The semiconductor substrate shown in FIG. 9(a) is made by bonding the old substrate 1 and the semiconductor substrate 2 in which polycrystalline silicon 3 is attached to the V-groove of the 81 substrate 2. The bonding is performed by the method of the present invention in which an oxide film 4 is provided.
第９図（ｂ）は、第９図（ａ）と同様でおるが異なる所
はＶ溝に多結晶シリコンを付着させないで３の部分は突
気（ａｉｒ ）であることである。FIG. 9(b) is similar to FIG. 9(a), except that polycrystalline silicon is not attached to the V-groove and the portion 3 is air-filled.
このようにしてつくった半導体基板は誘電体基板として
有用なものとなる。The semiconductor substrate thus produced is useful as a dielectric substrate.
前述したように均一な特性を有するシリコン基板同志を
加圧することなく接合できるので、Ｐ−Ｎ特性を有する
均一なシリコン基板、Ｐ−Ｎ−Ｐ特性を有する基板など
各種の特性を有する均一なシリコン基板を得ることが出
来るとともに、素子を形成した基板同志を接合した多層
基板を容易に得ることが串来る。As mentioned above, silicon substrates with uniform characteristics can be bonded together without applying pressure, so it is possible to bond uniform silicon substrates with various characteristics such as uniform silicon substrates with P-N characteristics and substrates with P-N-P characteristics. In addition to being able to obtain a substrate, it is also possible to easily obtain a multilayer substrate in which substrates on which elements are formed are bonded together.
また、中間に各種特性の絶縁体を有するシリコン基板な
ど、新しいシリコン基板を提供できる利点がある。Another advantage is that new silicon substrates, such as silicon substrates with insulators with various properties in between, can be provided.
第１図は、本発明の第１の実施例を説明する図、第２図
は、第２の実施例の断面図、
第３図は、第３の実施例の断面図、
第４図は、第４の実゛施例の断面図である。
第５図は、本発明方法によってＰ形基板とｎ形基板を接
合したＰｎ接合ダイオードのＩ−Ｖ特性を示す。
第６図は、本発明によって接合し九半導体基板の断面図
を示し、
第７図は、引張り試験特性を示す。
第８図は、本発明によシ多層接合を形成した高耐圧のス
イッチング素子を示す。
第９図（ａｌ （ｂ）は、本発明方法によるＤＩ半導体
基板を示す。
１・・・Ｐ形シリコン基板
２・・・Ｎ形シリコン基板
３・・・薄い酸化被膜
４・・・薄い酸化被膜
１０・・・Ｐ形シリコン基板
１１・・・Ｎ形シリコン基板
ル・・・Ｐ形シリコン基板
１３ 、１４ 、１５・・・薄い酸化被膜頒・・・シリ
コン基板
２１・・・厚い酸化被膜
２２・・・薄い酸化被膜
詔・・・シリコン基板
２４・・・薄い酸化被膜
（９）・・・シリコン基板
３１・・・薄い酸化膜
３２・・・厚い酸化膜
あ・・・厚い酸化膜
詞・・・厚い酸化膜
特許出願人 日本電信電話株式会社
代理人弁理士 玉 蟲 久 五 部（外２名）第１図
第 ２ 図
第３図
第４図
第５図
第８図
第９図Fig. 1 is a diagram for explaining the first embodiment of the present invention, Fig. 2 is a sectional view of the second embodiment, Fig. 3 is a sectional view of the third embodiment, and Fig. 4 is a sectional view of the third embodiment. , is a sectional view of the fourth embodiment. FIG. 5 shows the IV characteristics of a Pn junction diode in which a P-type substrate and an N-type substrate are bonded together by the method of the present invention. FIG. 6 shows a cross-sectional view of a semiconductor substrate bonded according to the present invention, and FIG. 7 shows tensile test characteristics. FIG. 8 shows a high voltage switching element formed with a multilayer junction according to the present invention. FIG. 9(b) shows a DI semiconductor substrate according to the method of the present invention. 1... P-type silicon substrate 2... N-type silicon substrate 3... Thin oxide film 4... Thin oxide film 10...P-type silicon substrate 11...N-type silicon substrate P-type silicon substrate 13, 14, 15...Thin oxide film distribution...Silicon substrate 21...Thick oxide film 22... ...Thin oxide film...Silicon substrate 24...Thin oxide film (9)...Silicon substrate 31...Thin oxide film 32...Thick oxide film...Thick oxide film...・Thick Oxide Film Patent Applicant: Nippon Telegraph and Telephone Corporation Patent Attorney Hisashi Tamamushi (2 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 8 Figure 9
Claims (5)
上のシリコン基板を重ね合せ、７００℃〜１４００℃の
範囲の温度で加熱し、該２枚以上のシリコン基板を接合
することを特徴とする半導体基板の接合方法。(1) Two or more silicon substrates having a thin oxide film of 10 Å to 500 Å are stacked together and heated at a temperature in the range of 700°C to 1400°C to bond the two or more silicon substrates. A method for bonding semiconductor substrates.
する特許請求の範囲第１項に記載の半導体基板の接合方
法。(2) The method for bonding semiconductor substrates according to claim 1, wherein heating is performed in an inert gas or the atmosphere.
有するシリコン基板を重ね合せ、接合することを特徴と
する特許請求の範囲第１項に記載の半導体基板の接合方
法。(3) The method for bonding semiconductor substrates according to claim 1, wherein a silicon substrate having a thin oxide film and a silicon substrate having a thick oxide film are stacked and bonded.
２枚以上のシリコン基板を重ね合せ、接合することを特
徴とする特許請求の範囲第１項に記載の半導体基板の接
合方法。(4) The method for bonding semiconductor substrates according to claim 1, wherein two or more silicon substrates having a thin oxide film portion and a thick oxide film portion are stacked and bonded.
とを特徴とする特許請求の範囲第３項に記載の半導体基
板の接合方法。(5) The method for bonding semiconductor substrates according to claim 3, wherein the thickness of the thick oxide film varies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3979187A JPS63205909A (en) | 1987-02-23 | 1987-02-23 | Junction method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3979187A JPS63205909A (en) | 1987-02-23 | 1987-02-23 | Junction method of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205909A true JPS63205909A (en) | 1988-08-25 |
Family
ID=12562773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3979187A Pending JPS63205909A (en) | 1987-02-23 | 1987-02-23 | Junction method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205909A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07245382A (en) * | 1994-03-07 | 1995-09-19 | Fuji Electric Co Ltd | Manufacture of composite element and lamination substrate |
-
1987
- 1987-02-23 JP JP3979187A patent/JPS63205909A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07245382A (en) * | 1994-03-07 | 1995-09-19 | Fuji Electric Co Ltd | Manufacture of composite element and lamination substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5373184A (en) | SOI/semiconductor heterostructure fabrication by wafer bonding | |
| US3922705A (en) | Dielectrically isolated integral silicon diaphram or other semiconductor product | |
| JP2856030B2 (en) | Method for manufacturing bonded wafer | |
| JPH01315159A (en) | Dielectric-isolation semiconductor substrate and its manufacture | |
| JPH03280538A (en) | Fabrication method for semiconductor device formation substrate | |
| US3488835A (en) | Transistor fabrication method | |
| JPH03165577A (en) | Semiconductor device and its manufacture | |
| JPH0799239A (en) | Semiconductor device and manufacture thereof | |
| US3902936A (en) | Germanium bonded silicon substrate and method of manufacture | |
| JPS63205909A (en) | Junction method of semiconductor substrate | |
| JPH01302740A (en) | Dielectric isolation semiconductor substrate | |
| JPH05275300A (en) | Method of joining semiconductor wafers | |
| JPH03181115A (en) | Manufacture of semiconductor substrate | |
| US4411060A (en) | Method of manufacturing dielectrically-isolated single-crystal semiconductor substrates | |
| JPS62283655A (en) | Manufacture of semiconductor multilayered substrate | |
| JPH05335649A (en) | Hall element | |
| JP3563144B2 (en) | Manufacturing method of bonded SOI substrate | |
| JPH04199632A (en) | Soi wafer and manufacture thereof | |
| JPS6314449A (en) | Manufacture of dielectric isolation substrate | |
| JP3614927B2 (en) | Method for manufacturing bonded semiconductor substrate | |
| JPS6362252A (en) | Manufacture of dielectric isolation substrate | |
| KR0180622B1 (en) | Method of manufacturing soi wafer having a multi-layer structure by silicon wafer junction at low temperature and soi wafer manufactured by this method | |
| JPS60236243A (en) | Manufacture of semiconductor device | |
| JP3795150B2 (en) | Oxide film bonded substrate and manufacturing method thereof | |
| JP2608443B2 (en) | Method for manufacturing semiconductor wafer |