JPS62283655A - Manufacture of semiconductor multilayered substrate - Google Patents
Manufacture of semiconductor multilayered substrateInfo
- Publication number
- JPS62283655A JPS62283655A JP61127738A JP12773886A JPS62283655A JP S62283655 A JPS62283655 A JP S62283655A JP 61127738 A JP61127738 A JP 61127738A JP 12773886 A JP12773886 A JP 12773886A JP S62283655 A JPS62283655 A JP S62283655A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- substrates
- polishing
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 85
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 230000003746 surface roughness Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 32
- 239000011261 inert gas Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 abstract description 19
- 238000005498 polishing Methods 0.000 abstract description 19
- 238000010438 heat treatment Methods 0.000 abstract description 14
- 238000012545 processing Methods 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000007781 pre-processing Methods 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 241001663154 Electron Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000002649 leather substitute Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は多数枚のウェハを重ね合せ一枚の多層クエへと
する接合による半導体多層基板の製造方法に関するもの
である。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor multilayer substrate by stacking a large number of wafers and bonding them into a single multilayer board. be.
Ｓｔウェハを重ね合わせて１枚の単結晶ウェハを作る技
術が発表されている（日経エレクトロニクス、 １ 、
２７ （１９８６＞１０８〜１１０）。A technology to create a single single crystal wafer by stacking St wafers has been announced (Nikkei Electronics, 1,
27 (1986>108-110).
この技術は、例えば、Ｐ型ウェハとｎ型ウェハを重ね合
わせ接合することにより、Ｐｎ接合を作ることのできる
技術で深い拡散や厚いエピタキシャル成長に代替できる
量産に向いた技術である。This technique is suitable for mass production and can replace deep diffusion or thick epitaxial growth, as it can create a Pn junction by overlapping and bonding a P-type wafer and an n-type wafer, for example.
第４図は発表された接合技術の接合工程を示すものであ
る。■のＳｉウエノＳ、ｔ−■で鏡面研磨し、■の洗浄
処理において水中で２枚のウェア・を重ね合せ、２枚の
ウニへ間に水酸基を付着させる。Figure 4 shows the joining process of the announced joining technology. (2) mirror polishing with Si Ueno S, t-(2), and in (2) washing process, two pieces of wear are superimposed in water to attach hydroxyl groups to the two pieces of sea urchin.
次に、■において幽界囲気中で約１０００℃に加熱し、
脱水することにより■で２枚のウェア・が接合する。Next, in (2), it is heated to about 1000°C in an astral atmosphere,
By dehydrating, the two pieces of clothing will be joined together.
この技術の技術的ポイントは洗浄処理の水酸基の付着と
熱処理における加熱条件にある。The technical points of this technology are the attachment of hydroxyl groups during cleaning treatment and the heating conditions during heat treatment.
洗浄処理では脱脂や酸洗浄などによりウェア・表面を活
性化させている。熱処理では未接合の空洞（ボイド）が
発生しないように温度管理を行っている。In the cleaning process, the wear and surface are activated by degreasing and acid cleaning. During heat treatment, temperature is controlled to prevent the formation of unbonded cavities (voids).
この技術の欠点は洗浄が非常に複雑な工程となり、また
、熱処理でウェー・全面にわたって未接合の空洞をなく
することは非常に困難であることである。The disadvantage of this technique is that cleaning is a very complicated process, and it is very difficult to eliminate unbonded cavities over the entire surface of the wafer by heat treatment.
この原因は通常の鏡面研磨は高々４０ ＸＲｍａｘ程度
の表面粗さでありＳｉ原子が直接つながる精度となって
いないこと、洗浄処理でＳｉウェア１表面から空気やゴ
ミなどの異物を完全に除去できないこと、および、熱処
理で完全に脱水できないことにある。The reason for this is that normal mirror polishing has a surface roughness of about 40 , and that it cannot be completely dehydrated by heat treatment.
また、多層化した場合、加熱によシ下部に形成されてい
る素子の特性を劣化させる欠点がある。Furthermore, when multi-layered, there is a drawback that the characteristics of the elements formed under the layer deteriorate due to heating.
この種の従来技術の他の例として、半導体集積回路を形
成した基板を、絶縁物を介して他の半導体基板に熱接着
する技術がある（特願昭６Ｏ−１３５０２）。Another example of this type of prior art is a technique in which a substrate on which a semiconductor integrated circuit is formed is thermally bonded to another semiconductor substrate via an insulator (Japanese Patent Application No. 6O-13502).
しかし、この技術においても、熱処理によシ多層基板を
形成するもので、加熱の影響を避けることはできない。However, even in this technique, a multilayer substrate is formed by heat treatment, and the influence of heating cannot be avoided.
従来における接合技術は、上述のように工程が複雑にな
ったり、未接合の空洞が生じる問題があつ゛た。また、
接合工程に加熱が必要であって、下部に形成されている
素子の特性を劣化させる等の熱処理による影響が発生す
る問題があった。Conventional bonding techniques have had the problems of complicating the process and creating unbonded cavities, as described above. Also,
The bonding process requires heating, and there is a problem in that the heat treatment causes effects such as deteriorating the characteristics of the elements formed below.
そこで本発明は、これらの欠点を除去し、常温下で単結
晶基板を他の基板に接合することによシ多層化基板の形
成を可能とする製造方法を提供しようとす−るものであ
る。Therefore, the present invention aims to eliminate these drawbacks and provide a manufacturing method that makes it possible to form a multilayer substrate by bonding a single crystal substrate to another substrate at room temperature. .
本発明は、第１の半導体基板および第２の半導体基板に
形成された半導体または絶縁体表面を真空中または不活
性ガス中でエツチングする工程と、該真空中または不活
性ガス中において、第１の半導体基板の上記エツチング
面と第２の半導体基板の上記エツチング面と金合せ接合
する工程とを有することを特徴とする半導体多層基板の
製造方法を提供するものでおる。The present invention includes a step of etching the surfaces of semiconductors or insulators formed on a first semiconductor substrate and a second semiconductor substrate in a vacuum or in an inert gas; The present invention provides a method for manufacturing a semiconductor multilayer substrate, comprising the step of bonding the etched surface of the second semiconductor substrate with the etched surface of the second semiconductor substrate.
そして、本発明に係る工程においては、上記基板は＾オ
ーダの表面粗さに加工され、真空中または不活性ガス中
で洗浄の役割を果すエツチングを行ない接合される。In the process according to the present invention, the substrates are processed to have a surface roughness on the order of ^, and then bonded after being etched in a vacuum or in an inert gas for cleaning.
その構成によれば、従来の技術と異なり、加工精度、熱
処理の点で全く異なるものである。また、接着材となる
接合媒体を用いない点でも異なる。According to its configuration, it is completely different from conventional technology in terms of processing accuracy and heat treatment. Another difference is that a bonding medium serving as an adhesive is not used.
特に本発明を第１図に示した本発明の実施例に■１１四
ｖ＋ｇ□□ノ□入□す□□□□ふ□□１□て説明すると
、■において単結晶基板を用意し、■の超平面研磨工程
で数にの表面粗さに研磨する。In particular, the present invention will be explained by entering the embodiment of the present invention shown in FIG. The ultra-flat surface polishing process polishes the surface to several degrees of roughness.
次に■の工程で真空装置内でエツチングを行ない、■の
工程で同真空装置内で２枚の基板を真空中で重ね合せ接
合し、■の接合ウェハを得る。Next, in the step (2), etching is performed in a vacuum apparatus, and in the step (2), the two substrates are stacked and bonded in vacuum in the same vacuum apparatus to obtain a bonded wafer (3).
上記において、■の超平面研磨工程で、単結晶基板を数
人オーダに研磨するのは基板！−構成する物質の原子と
同じオーダの寸法とすることである。In the above, in the ultra-plane polishing process (■), the single crystal substrate is polished by several people! -The dimensions should be on the same order as the atoms of the constituent substances.
また、■の真空中（又は不活性ガス中）のエツチングは
基板表面を洗浄し、基板生来の処女面を創成して基板表
面を活性化するものである。そしてその真空または不活
性雰囲気を破ることなくひき続いて基板同士を合せ接合
している〜
上記の接合の原理は、真空中で硬脆材料・金属等の結晶
の臂開面同士は、完全に接合することによるものである
。基板の表面粗さを原子、オーダとし、真空中で基板表
面を活性化することにより、２枚の基板はお互いに面で
接触するので、分子（原子）間引力によって、常温で確
実に接合する。Etching in a vacuum (or in an inert gas) (2) cleans the substrate surface, creates a virgin surface inherent to the substrate, and activates the substrate surface. The substrates are then bonded together without breaking the vacuum or inert atmosphere. This is by joining. By setting the surface roughness of the substrate to the atomic order and activating the substrate surface in a vacuum, the two substrates come into contact with each other on their surfaces, so they can be reliably bonded at room temperature due to intermolecular (atomic) attraction. .
従来の技術におけるような、表面粗さ、空気やゴミの付
着、脱水の不完全等によシ未接合の空洞部分は殆んど発
生しない。また、常温中での処理なので、加熱による素
子劣化は全くない。Unlike conventional techniques, unbonded cavities are hardly generated due to surface roughness, adhesion of air or dust, incomplete dehydration, etc. Furthermore, since the process is performed at room temperature, there is no element deterioration due to heating.
（実施例１）
先に説明した第１図の工程の中で、超精密研磨とエツチ
ングがポイントとなる。表面粗さ数又は通常の研磨装置
では加工困難である。第１図には図示してないが、当然
、超精密研磨を実行するためには、「前加工→精密研磨
」を順次試料に施した上で超精密研磨を行う。前加工は
ラッピングや研削でよいが、後の加工（研磨）工程に負
担をかけないように極力精度の高い、かつ加工変質層の
少ない加工条件を選ぶことが望ましい。精密研磨では、
所謂、メカノケミカルボリジング法を適用する。加工条
件としては、例えば１００＾前後の５ｉＯｆ微粒子を弱
アルカリ性液に懸濁させたコロイダルシリカをボリシ剤
とし、また軟質の人工皮革をポリシャとして行う。この
場合、加工面の平面度が劣化するので、ポリシャ貼付は
定盤に注意ｔ−ｉする。例えば、定盤の形状として、高
精度平面が作成できるような円錐状とし、その上、試料
の大きさにくらべて定盤の径を数〜１０倍程度にする。(Example 1) Among the steps shown in FIG. 1 described above, the key points are ultra-precision polishing and etching. Due to the surface roughness, it is difficult to process with ordinary polishing equipment. Although not shown in FIG. 1, naturally, in order to perform ultra-precision polishing, the sample is sequentially subjected to "pre-processing → precision polishing" and then ultra-precision polishing is performed. Pre-processing may be done by lapping or grinding, but it is desirable to select processing conditions that have as high precision as possible and minimize the number of damaged layers so as not to put a burden on the subsequent processing (polishing) process. In precision polishing,
A so-called mechanochemical boriding method is applied. As for the processing conditions, for example, colloidal silica in which 5iOf fine particles of about 100^ are suspended in a slightly alkaline liquid is used as a polishing agent, and soft artificial leather is used as a polisher. In this case, since the flatness of the machined surface deteriorates, care must be taken when attaching the polisher to the surface plate. For example, the shape of the surface plate is a conical shape so that a highly accurate plane can be created, and the diameter of the surface plate is several to ten times larger than the size of the sample.
さらに、研磨装置における注意事項として、駆動系等も
しくは外部から発生する振動を除去、加工系全体を±０
．５℃以下に温度コントロールすることである。このよ
うな前処理を終えた段階で、平面精度２７１０〜２１５
０１表面粗さ１０又Ｒｍａｘ以下。Furthermore, as precautions for polishing equipment, vibrations generated from the drive system or the outside should be removed, and the entire machining system should be kept at ±0.
．． The temperature should be controlled to below 5°C. After completing this preprocessing, the plane accuracy is 2710 to 215.
01 Surface roughness 10 or less than Rmax.
加工変質層深さ数１０〜数λ程度の試料が得られる。A sample with a process-affected layer depth of several tens to several λ can be obtained.
次に、超ｆ［研磨では、原子オーダで加工ができる非接
触研磨法を適用して仕上げる。この非接触研磨法は、動
圧発生工具をポリシャとして高速回転させ、液中（加工
剤液中）研磨を行うと、試料はポリシャ面から完全に浮
上し、加工剤中の粒子が試料の加工面に衝突し、試料表
面の材料が原子オーダで弾性破壊・除去されるというメ
カニズムであシ、最適な加工条件を選ぶことによって表
面粗さ数λが実現できる。Next, in ultra-f polishing, a non-contact polishing method that allows processing on the atomic order is applied to finish. In this non-contact polishing method, a dynamic pressure generating tool is used as a polisher to rotate at high speed, and when polishing is performed in a liquid (processing agent liquid), the sample is completely lifted off the surface of the polisher, and the particles in the processing agent are used to polish the sample. The mechanism is that the material on the sample surface is elastically destroyed and removed on the atomic order by colliding with a surface, and a surface roughness number λ can be achieved by selecting optimal processing conditions.
ここでの注意すべきことは、加工面（試料面）が均一に
加工されるように、動圧工具を設計すること、加工剤中
の粒子としては、比較的軟質な数１０ Ｋの超微粒子を
用いること、装置的には、超防震対策、超恒温保持対策
（温度コントロール）。The important thing to keep in mind here is to design the dynamic pressure tool so that the machined surface (sample surface) is machined uniformly, and the particles in the processing agent should be relatively soft ultrafine particles of several tens of kilograms. In terms of equipment, we use ultra-earthquake protection measures and ultra-constant temperature maintenance measures (temperature control).
超防塵対策等に配慮すること、などである。加工剤の液
には、単なる純水でもよいが、加工試料に対して有効な
化学液を用いれば能率は向上する。Consideration should be given to ultra-dust-proof measures, etc. Although pure water may be used as the processing agent liquid, efficiency can be improved by using a chemical liquid that is effective against the processing sample.
以上の研磨工程によって、平面精度λ／１００以下、表
面粗さ数又以下、加工変質層なしの試料が得られる。Through the above polishing process, a sample with a flatness accuracy of λ/100 or less, a surface roughness of a few degrees or less, and no process-affected layer can be obtained.
一方、エツチングに関しては、所謂エツチングという概
念ではなく、むしろクリーニングというべきものであり
、加工表面に付着もしくは吸着している微小な異物のみ
を除去する目的の工程である。従って、異物のみを選択
的に除去できる、もしくはファインなエツチングの条件
を選ぶべきである。例えば、ＦＡＢ （Ｆａｓｔ Ａｔ
ｏｍ Ｂｏｎｂｅｒ−ｃｍｅｗｔ ）＋ＥＣＲ（Ｅｌｅ
ｃｔｒｏｎ Ｃｙｅｌｏｔｏｒｏｎ Ｒｅ５ｏｎａｎｃ
ｅ ）などを使用すればよい。On the other hand, etching is not the concept of so-called etching, but rather cleaning, and is a process whose purpose is to remove only minute foreign matter adhering to or adsorbing on the processed surface. Therefore, conditions for selectively removing only the foreign matter or fine etching conditions should be selected. For example, FAB (Fast At
om Bomber-cmewt )+ECR(Ele
ctron Cyelotoron Re5onanc
e) etc. may be used.
真空中（又は不活性ガス中）での２枚の基板試料の重ね
合せはロボット（マニュピレータ）ｔ−用いつつある程
度加圧して行えば容易にできる。The superposition of two substrate samples in a vacuum (or in an inert gas) can be easily accomplished by using a robot (manipulator) and applying some pressure.
（実施例２）
第２図は本発明の他の実施例であって、素子を形成した
基板と他の基板を接合した例である。１は単結晶基板、
２は基板上に形成された素子、３は絶縁物層、４は単結
晶基板、５は基板上に形成された素子である。このよう
な多層基板の製造方法は、単結晶基板１上に素子２が形
成され、その上に絶縁物を堆積させ絶縁物層３を形成す
る。絶縁物としては例えば５ｉｎｓ ’ｃ ＣＶＤで堆
積させる。(Example 2) FIG. 2 shows another example of the present invention, in which a substrate on which an element is formed is bonded to another substrate. 1 is a single crystal substrate,
2 is an element formed on a substrate, 3 is an insulating layer, 4 is a single crystal substrate, and 5 is an element formed on the substrate. In this method of manufacturing a multilayer substrate, an element 2 is formed on a single crystal substrate 1, and an insulator is deposited thereon to form an insulator layer 3. The insulator is deposited, for example, by 5 ins 'c CVD.
絶縁物を堆積した単結晶基板１と単結晶基板４の接合は
実施例１で示した工程で行えばよい。絶縁物層３の上部
と単結晶基板４の下部とを研磨し、真空中でエツチング
し、接合すれば２層の基板が出来上る。同様な工程をく
り返せば３層以上の多層基板を製造することができる。The bonding of the single crystal substrate 1 on which the insulator is deposited and the single crystal substrate 4 may be performed by the process shown in the first embodiment. The upper part of the insulating layer 3 and the lower part of the single-crystal substrate 4 are polished, etched in a vacuum, and bonded together to complete a two-layered substrate. By repeating similar steps, a multilayer board with three or more layers can be manufactured.
前述のように、全く加熱の工程がないので素子２および
素子５を劣化させることはない。As mentioned above, since there is no heating process at all, the elements 2 and 5 will not deteriorate.
（実施例３）
第３図は本発明の第３の実施例である。１０は第１の単
結晶基板、１１はｌＯ上に形成された素子、ｎは絶縁物
層、１３は第２の単結晶基板、１４は１３上に形成され
た素子、１５は絶縁物層である。(Embodiment 3) FIG. 3 shows a third embodiment of the present invention. 10 is a first single crystal substrate, 11 is an element formed on IO, n is an insulating layer, 13 is a second single crystal substrate, 14 is an element formed on 13, and 15 is an insulating layer. be.
本実施例は絶縁物層戎と絶縁物層１５間で接合し、第１
の単結晶基板ｌＯと第２の単結晶基板１３とが２層基板
を形成している。In this embodiment, the insulator layer 15 is bonded to the insulator layer 15, and the first
The single crystal substrate lO and the second single crystal substrate 13 form a two-layer substrate.
製造方法については実施例１の工程で行えばよいので省
略する。The manufacturing method will be omitted since it can be carried out using the steps in Example 1.
なお、その他、本発明によれば、半導体基板同志を、別
に用意した絶縁体を介して接合することも可能であり、
その半導体基板と絶縁体の接合に適用できる。In addition, according to the present invention, it is also possible to bond semiconductor substrates together via a separately prepared insulator,
It can be applied to bonding the semiconductor substrate and the insulator.
第３図に示した基板を１つのモジュールとして用意し、
これを積み重ねて行けば要求された機能を出すことので
きる多層基板を形成することが可能である。カスタム多
層基板ＬＳＩが可能である。Prepare the board shown in Figure 3 as one module,
By stacking these layers, it is possible to form a multilayer substrate that can provide the required function. Custom multilayer substrate LSI is possible.
以上の説明ではＳｉ基板同士の接合を想定したが、本発
明は３ｉ基板のみでなく、Ｓｌ基板とＧａＡａ基板、Ｇ
ａ Ａ ｓ基板同士、Ｇ ａ Ａ ａ基板とＩｎＰ基
板、等種々の基板間あるいは異種基板間の接合が可能で
ある。基板の表面粗さを数又と原子オーダとする未だ実
現されていない新しい基板を作シ出すことが出来、新し
いＬＳＩの出現も考えられる。In the above explanation, it is assumed that Si substrates are bonded to each other, but the present invention is applicable not only to 3i substrates but also to Si substrates, GaAa substrates, G
It is possible to bond various types of substrates, such as between aAs substrates, between a GaAa substrate and an InP substrate, or between different types of substrates. It is possible to create a new substrate whose surface roughness is on the atomic order, which has not yet been realized, and the emergence of new LSIs.
本発明によりＬＳＩの理想とされている全く新しいＳＯ
Ｉ （５ｉｉｉｃｏｎ ｏｎ Ｉｎ５ｕｌａｔｏｒ ）
基板の実現も秘めていることは言うまでもない。A completely new SO that is considered as an ideal LSI by this invention
I (5iiicon on In5ulator)
Needless to say, the realization of the circuit board is also a secret.
以上説明したように本発明によれば以下のような利点が
ある。As explained above, the present invention has the following advantages.
（１） 集積回路を形成した基板あるいはｎ層とＰ層
のように性質の違う基板を多層に接合した多層基板を量
産化ができる。(1) It is possible to mass produce substrates on which integrated circuits are formed or multilayer substrates in which substrates with different properties, such as an n-layer and a p-layer, are bonded together.
（２）常温で接合が可能で形成した集積回路への影響は
全くない。(2) Bonding is possible at room temperature and has no effect on the formed integrated circuit.
（３） 真空中または不活性ガス中で接合することに
よシ基板全面にわたる完全な接合が得られる。(3) Complete bonding over the entire surface of the substrate can be obtained by bonding in vacuum or in an inert gas.
（４） 異種基板の接合が可能である。(4) It is possible to bond different types of substrates.
第１図は本発明に係る接合方法を示す工程図、第２図お
よび第３図は本発明の実施例における工程断面図、
！４図は従来の接合方法を示す工程図である。
１・・・単結晶基板
２・・・素子
３・・・絶縁物層
４・・・単結晶基板
５・・・素子
１０・・・単結晶基板
１１・・・素子
１２・・・、ｓ＃ｇｋｍ層
１３・・・単結晶基板
１４・・・素子
１５・・・絶縁物層
特許出願人 日本電信電話株式会社
代理人弁理士 玉 蟲 久 五 部（外２名）本発明
に係る接合工程図
第１図
実施例２の工程ｌｆｒ面図
第２図
実施例３の工程断面図
第３ 図FIG. 1 is a process diagram showing a joining method according to the present invention, FIGS. 2 and 3 are process cross-sectional views in an embodiment of the present invention, ! FIG. 4 is a process diagram showing a conventional joining method. 1...Single crystal substrate 2...Element 3...Insulator layer 4...Single crystal substrate 5...Element 10...Single crystal substrate 11...Element 12..., s# Gkm layer 13...Single crystal substrate 14...Element 15...Insulator layer Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent Attorney Hisashi Tamamushi (2 others) Bonding process diagram according to the present invention Fig. 1 Process lfr side view of Example 2 Fig. 2 Process sectional view of Example 3 Fig. 3
Claims (3)
された半導体または絶縁体表面を真空中または不活性ガ
ス中でエッチングする工程と、 該真空中または不活性ガス中において、第１の半導体基
板の上記エッチング面と第２の半導体基板の上記エッチ
ング面とを合せ接合する工程とを有することを特徴とす
る半導体多層基板の製造方法。(1) A step of etching the semiconductor or insulator surfaces formed on the first semiconductor substrate and the second semiconductor substrate in a vacuum or in an inert gas; A method for manufacturing a semiconductor multilayer substrate, comprising the step of aligning and bonding the etched surface of a semiconductor substrate and the etched surface of a second semiconductor substrate.
絶縁体表面および前記第２の半導体基板に形成された半
導体または絶縁体表面の双方を数Åの表面粗さに加工す
ることを特徴とする特許請求の範囲第（１）項記載の半
導体多層基板の製造方法。(2) Both the semiconductor or insulator surface formed on the first semiconductor substrate and the semiconductor or insulator surface formed on the second semiconductor substrate are processed to have a surface roughness of several angstroms. A method for manufacturing a semiconductor multilayer substrate according to claim (1).
それぞれ集積回路が形成された半導体基板であり、該第
１および第２の半導体基板を絶縁体を介して接合するこ
とを特徴とする特許請求の範囲第（１）項または（２）
項のいずれかに記載の半導体多層基板の製造方法。(3) The first semiconductor substrate and the second semiconductor substrate are semiconductor substrates each having an integrated circuit formed thereon, and the first and second semiconductor substrates are bonded via an insulator. Claims paragraph (1) or (2)
A method for manufacturing a semiconductor multilayer substrate according to any one of Items 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61127738A JPS62283655A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor multilayered substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61127738A JPS62283655A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor multilayered substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62283655A true JPS62283655A (en) | 1987-12-09 |
Family
ID=14967457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61127738A Pending JPS62283655A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor multilayered substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62283655A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02126625A (en) * | 1988-11-05 | 1990-05-15 | Shin Etsu Handotai Co Ltd | Junction of semiconductor wafer |
| JP2008021971A (en) * | 2006-07-11 | 2008-01-31 | Soi Tec Silicon On Insulator Technologies | Method of directly bonding two substrates used for electronics, optics, or optoelectronics |
| JP2010207908A (en) * | 2009-03-12 | 2010-09-24 | Nikon Corp | Fabricating apparatus for fabricating semiconductor device and method for fabricating semiconductor device |
| JP2018101746A (en) * | 2016-12-21 | 2018-06-28 | 株式会社Sumco | Method of producing pn-junction silicon wafer and pn-junction silicon wafer |
| JP2018101745A (en) * | 2016-12-21 | 2018-06-28 | 株式会社Sumco | Method of producing pn-junction silicon wafer and pn-junction silicon wafer |
| US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
| US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
-
1986
- 1986-06-02 JP JP61127738A patent/JPS62283655A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02126625A (en) * | 1988-11-05 | 1990-05-15 | Shin Etsu Handotai Co Ltd | Junction of semiconductor wafer |
| US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
| US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
| JP2008021971A (en) * | 2006-07-11 | 2008-01-31 | Soi Tec Silicon On Insulator Technologies | Method of directly bonding two substrates used for electronics, optics, or optoelectronics |
| JP2010207908A (en) * | 2009-03-12 | 2010-09-24 | Nikon Corp | Fabricating apparatus for fabricating semiconductor device and method for fabricating semiconductor device |
| JP2018101746A (en) * | 2016-12-21 | 2018-06-28 | 株式会社Sumco | Method of producing pn-junction silicon wafer and pn-junction silicon wafer |
| JP2018101745A (en) * | 2016-12-21 | 2018-06-28 | 株式会社Sumco | Method of producing pn-junction silicon wafer and pn-junction silicon wafer |
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