JPH02126625A - Junction of semiconductor wafer - Google Patents

Abstract

PURPOSE:To make voids substantially disappear with high reproducibility and improve the high integration of a semiconductor IC as well as the yield of such integrated circuits by joining semiconductor wafers which are made to have roughness of each mirror face that is less than 0.5nm or below at a center line average height by polishing the mirror face. CONSTITUTION:Two sheets of semiconductor wafers which are made to have roughness of each mirror face that is less than 0.5nm or below at a center line average height are used in a joining system of the semiconductor wafers. When this system is performed through oxide films, one or both sides of the mirror face of a silicon wafer having the roughness of each mirror face that is less than 0.5nm or below at a center line average height is oxidized and then the wafers are joined. If both mirror faces are made to come into contact with each other and slight pressure produced by holding two faces with fingers is applied, its joining is performed completely. However, after a mirror face is put on top of the other mirror face of each wafer, addition of pressure from center to outside prevents easily atmospheric gases from being trapped inside the wafer. Even though a slight amount of its gas remains, it is removed by a subsequent heating process. If heated in a state where no pressure is applied after joining them, its heating renders its junction more firm.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor wafer bonding method for bonding the mirror surfaces of two mirror-polished semiconductor wafers to each other directly or via an oxide film.

[Prior Art] As techniques for introducing impurities as a substrate process in the manufacture of semiconductor electronic devices, the thermal diffusion method and the Evita Kinyar growth method are currently widely used as they are almost technologically established. However, when trying to make a power device using these methods, there are technical limitations in forming a high resistance layer of 100 ΩC or more by collector diffusion by thermal diffusion or Evita kinial growth, and there are difficulties in increasing the volume with a high breakdown voltage.

In addition, in particular, in semiconductor integrated circuits, although dielectric isolation technology that separates individual elements with a dielectric material is superior in terms of parasitic capacitance and isolation breakdown voltage, the warpage of the substrate is too large, making it difficult to manufacture The above is very problematic.

The method of bonding the mirror surfaces of two mirror-polished silicon wafers to each other directly or via an oxide film has not received much attention in the past, but recently it has been developed to bond the mirror surfaces of two mirror-polished silicon wafers to each other, either directly or via an oxide film, but recently it has been developed to bond the mirror surfaces of two mirror-polished silicon wafers to each other directly or via an oxide film. It has gained a lot of attention as a manufacturing method for circuit boards. For either application, the drawbacks of the conventional methods mentioned above can be significantly improved.

Such a method for bonding Noricon wafers is disclosed in Japanese Patent Publication No. 39-17869, for example, although it is not intended to be used for the above purpose.

Currently, the method of bonding to Noricon wafers is to stack mirror-finished Noricon wafers in air at room temperature, and then heat them at a high temperature, for example, 1100°C, for about 2 hours, at a certain oxygen/nitrogen ratio. In particular, when there is an oxide film between the wafers, applying a DC or AC voltage between the wafers to utilize the electrostatic attraction force that acts between the wafers, and in a nitrogen stream. A heating method is used.

There are two technical problems in bonding Norikono wafers.
At the bonding surfaces of two mirror-finished wafers that correspond to each other, unattached portions where bonding is insufficient appear partially, forming what is commonly called a void. In order to suppress the occurrence of such voids, investigations are being carried out to find out the causes thereof, and dust, dirt, or scratches adhering to the surface of the wafer are thought to be the cause.In particular, dust is attracting attention as the biggest cause of void occurrence. ing.

However, the inventors have confirmed through experiments that voids cannot be completely removed by eliminating these causes.

In addition, as an improved bonding technology for silicon wafers, for example, Japanese Patent Application Laid-open No. 182216/1983 discloses that voids can be eliminated by using a gas that can easily pass through or be absorbed by semiconductors as an atmosphere when bonding semiconductor substrates. A method for preventing the occurrence is disclosed. However, when gases are retained at the -degree joint surface, it is actually very difficult to remove them by permeation and absorption.

[Problems to be Solved by the Invention] In view of the above problems, an object of the present invention is to provide a semiconductor wafer bonding method that can substantially eliminate the occurrence of voids with good reproducibility.

[Means for Solving the Problem] In order to achieve this object, in the semiconductor wafer bonding method according to the present invention, the surface roughness of the mirror surface of two semiconductor wafers/% is determined by the center line average roughness. A material with a thickness of 0.5 nm or less is used. When using an oxide film, the Q
, mirror surface No. 1 with a surface roughness of 5na+ or less. One or both of the resin wafers are oxidized and then bonded.

In the present invention, the two semiconductor wafers to be joined are not limited to silicon wafers, but may also be a combination of a silicon wafer and a compound semiconductor wafer, a combination of the same or different types of compound semiconductor wafers, or compound semiconductor wafers with the same or different mixed crystal ratios. It also applies to combinations of

[Operation] In direct bonding of semiconductor wafers, it is obvious from theoretical considerations of bonding that the surface roughness of the opposing mirror surfaces is smaller, but in conventional bonding technology to semiconductor wafers, However, no special consideration was given to mirror-finishing the semiconductor wafer, and sufficient technical studies were not conducted to determine how rough the mirror surface should be to prevent voids from forming. In other words, the roughness of semiconductor mirror-finished wafers is said to be between 100 and 500, but studies have been conducted on how much the mirror-finished surface roughness can be reduced using mechanochemical boring, which is the mainstream technology for mirror-finishing. blindly,
When I thought of a mirror surface, I only had a vague idea of some kind of ideal flat surface.

The present inventor investigated various known semiconductor wafer bonding techniques, but none of them yielded satisfactory results, and upon further research, it was found that the opposing mirror surfaces of semiconductor wafers or the roughness of the mirror surface before oxide film formation significantly affects the bonding of the joint surfaces,
The present invention was achieved by discovering that void-free bonding can be achieved by reducing the roughness of the mirror surface to 0.5 n@ (5 people) or less in terms of average center roughness.

When bonding such mirror-finished silicon wafers, it is not necessarily necessary to perform hot pressing, and complete bonding can be achieved by simply lightly touching both mirror surfaces and applying pressure to the extent of pinching between fingers. In addition, trapping of atmospheric gas inside can be easily avoided by applying more pressure to the center of two wafers, or by applying pressure outward from the center after the two wafers are aligned. Can be done. Even if some remains, it can be removed in the later heating process.

When the overlay is performed in air, the gas composition trapped inside is air, so that a small amount of trapped gas is absorbed and diffused into the bulk of the wafer.

In this way, the bonding surface is in a kind of vacuum state, so atmospheric pressure is applied to the bonding surface via the outer surface of the wafer bonded body, and the bonding progresses without hot pressing as in the conventional method. It becomes a monolithic state.

After this bonding, heating without applying pressure will result in a stronger bond. When the tensile strength was measured, it was found that the bonding strength exceeded 150/9/c@'. This is <
100> approximately equal to that of the bulk in the direction. When such a wafer was cut into pieces several mm square, there was no peeling, and even when heat cycles were applied in the silicon device manufacturing process, there was no peeling of the bonded surface of the bonded wafer, and there was no decrease in tensile strength. This was found to be equivalent to a monolithic junction in the bulk of a silicon device.

Here, the present inventor has studied various methods for inspecting semiconductor wafers for voids, and has found that the use of X-ray diffraction is extremely effective. Conventional void inspection methods include infrared transmission methods, ultrasonic flaw detection methods, and destructive inspection methods. Although this infrared transmission method is preferable because it is a non-destructive method, it was found to be a fatally inferior method when compared with the X-ray diffraction method. That is, if a wafer determined to have no voids by an infrared transmission method is inspected by an X-ray diffraction method, voids often remain. The reason for this is thought to be that in the case of X-ray diffraction, when bonding is performed, primary distortion of the crystal always occurs, and this distortion is detected by the X-ray method.

Therefore, the present inventor further investigated the entire bonding surface of the wafer by X-ray diffraction and confirmed that no voids were formed. Furthermore, if the mirror surface roughness of the silicon wafer is large, for example exceeding 0.7 nm as shown above, voids often occur, and further void growth and partial peeling can be seen when the device is subjected to a thermal cycle process. I confirmed that.

Although it has not yet been investigated why semiconductor wafers with a surface roughness of 0.5 nm or less have good bonding and exhibit the same properties as monolithic ones, as in the case of fine powder molding, atoms near the surface This is thought to be due to the rearrangement of .

Bonding of silicon wafers via an oxide film involves thermally oxidizing the surface of one or both silicon wafers to form a thermal oxide film with a thickness of 1 μm or less, then stacking them together, and then applying an electrostatic voltage with alternating current or direct current. and join.

Regarding this surface roughness, if the surface roughness of the mirror-finished wafer before the oxide film is formed exceeds about 0.5 nm in terms of center line average roughness, the bonding will be incomplete due to voids. The reason for bonding in this case is thought to be that, unlike when silicon wafers are directly bonded, most of the bonding is made of silica, that is, 5i-0-3i bonds are formed at the interface. Originally, dangling bonds of Si or 0 remain on the surface of the thermal oxide film, and these are the cause of bonding.

The bonding between a silicon wafer and a compound semiconductor, or the bonding between compound semiconductors, is almost the same as that between silicon wafers, and in both cases, a necessary condition for bonding is to have a surface roughness of 0.51 or less. Become. The same applies even if the chemical composition of the compound semiconductor differs depending on the elements or their mixed crystal ratios. If the crystal structure or lattice spacing is different, it is natural that the bonded product will have crystal disorder, but according to the present invention, it is possible to achieve a void-free structure and to minimize crystal distortion. Although an amorphous layer of several n levels is partially formed on the bonding surfaces having different crystal structures and lattice spacings, in practical use there is no abnormal change in electrical resistance value, and ohmic properties are maintained.

[Example] Hereinafter, an example of the present invention will be described regarding bonding of silicon wafers.

(1) Direct joining First, a description will be given of a bond that does not involve an oxide film.

As a sample, P type <100> crystal, diameter 125 mm,
Sixteen silicon wafers with a thickness of approximately 500μ and a resistivity of 8Ω were prepared, and the polishing pressure and polishing speed were adjusted as shown in Table 1 below, and mechanical boring was performed to obtain different surface roughness as shown in Table 2 below. Four silicon wafers 71Δ to 71D were each produced.

Table 1 Table 2 The basic structure of the polishing machine is the same as that of a commercially available polishing machine, and the polishing pad is a commercially available polishing cloth under the trade name Seagull 7455.
The polishing liquid was manufactured by Dai-Russ Co., Ltd. and the product name was GC3250, which was manufactured by Fujimi Abrasives Co., Ltd.

When measuring surface roughness, the accuracy and method of expressing it are extremely important in icehouses. Therefore, YYKO CORPORATION (YYKO CORPORATION) using optical phase shift interferometry, which can measure the center line average roughness with a surface height resolution of 3 people and a horizontal resolution of 1.0 μm, was developed.
), model TOPO-3D, and an objective lens with a magnification of 40 were selected and used. Using this measuring device, the above wafer A-
For each wafer, calculate the surface roughness of D by 2 orthogonal at the center.
Measurements were made at positions spaced apart (radius)/2 from the center on the straight line and in 5 areas around the center (one area is 0.25ssXO, 25 mm), and the average value was determined.

In order to clarify the relationship between surface roughness and void generation,
All combinations of the above wafers A-D (AA%AB,
AC%AD, BH, BC%BD, CC, CD, DD), the mirror surfaces were brought into close contact with each other, and then 11
A bonded wafer was prepared by performing heat treatment at 00° C. for 120 minutes. Next, a void inspection was performed.

Here, when infrared transmission method is used as in conventional void inspection, due to limitations due to the wavelength of infrared rays, voids with a thickness of about 0.1 μm or less, which is an extremely large value compared to the crystal lattice spacing, can be detected. cannot be inspected.

Therefore, the inventor conducted a void inspection using a Lang camera. This Lang camera is a computer-controlled topographic imaging system manufactured by Rigaku Denki Co., Ltd. The characteristic X-ray used was the MoK1+ ray, and the set reflection crystal plane was (2,2,0). This rung
In principle, a camera can detect voids with a thickness of approximately atomic level, which is sufficient for void inspection.

Figure 1 (AA) to (DD) are the above combinations AA, respectively.
- shows a Lang camera radiograph for DD.

The total area of the void is AA>AB>BB>AC>AD>B
It is clear that the order is C>BD>CC.

Furthermore, it is clear that the combinations CG, CD, and DD have no voids and are significantly better than other combinations.

From this, it can be seen that when performing this without forming an oxide film on the mirror surface, it is extremely important to reduce the mirror surface roughness to a center line average roughness of 0.45n- or less in order to eliminate voids. .

In order to investigate the limit of mirror surface roughness to eliminate voids with good reproducibility, we conducted void inspection by changing the mirror surface roughness more finely, and found that this limit was 0.5 ns in centerline average roughness display. I understand.

(2) Bonding via oxide film Next, a case will be described in which an oxide film is formed on the mirror surfaces of two silicon wafers and then the two are bonded.

Using the same wafers as those described above as samples, a thermal oxide film of 1 μm thickness was formed on both wafers of each set, and bonded wafers of the same combination were prepared and subjected to void inspection.

The results show that when the mirror surface roughness is reduced to 0.5n1 or less in terms of center line average roughness, the voids that were present in large numbers at 0.5n- or more almost disappear with good reproducibility as described above, and it becomes 0.51- or less. was found to be extremely effective in eliminating voids.

[Effects of the Invention] As explained above, according to the semiconductor wafer bonding method according to the present invention, voids are substantially eliminated with good reproducibility, which is an excellent effect, and it is possible to increase the integration density and yield of semiconductor integrated circuits. It greatly contributes to improvement.

[Brief explanation of the drawing]

1 to 1O are X-ray photographs of bonded wafers taken with a Lang camera.

Claims (1)

[Claims] 1) A semiconductor wafer bonding method in which the mirror surfaces of two mirror-polished semiconductor wafers are brought into close contact with each other to bond the two semiconductor wafers, the method comprising: Line average roughness 0.
A semiconductor wafer bonding method characterized by bonding semiconductor wafers having a thickness of 5 nm or less. 2) The method according to claim 1, wherein the two semiconductor wafers are either a silicon wafer or a compound semiconductor wafer, or a combination thereof. 3) The semiconductor wafer bonding method according to claim 2, wherein the two compound semiconductor wafers are of the same type or different types. 4) The semiconductor wafer bonding method according to claim 3, wherein the two compound semiconductor wafers are of the same type and have the same or different mixed crystal ratios. 5) In a silicon wafer bonding method in which the mirror surfaces of two silicon wafers that have been mirror-polished and one or both of the mirror surfaces are oxidized are brought into close contact with each other to bond both silicon wafers, the surfaces of the mirror surfaces are bonded by mirror polishing. A silicon wafer bonding method characterized by bonding silicon wafers having a roughness of 0.5 nm or less in terms of center line average roughness.