JPH03228326A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03228326A
JPH03228326A JP2423790A JP2423790A JPH03228326A JP H03228326 A JPH03228326 A JP H03228326A JP 2423790 A JP2423790 A JP 2423790A JP 2423790 A JP2423790 A JP 2423790A JP H03228326 A JPH03228326 A JP H03228326A
Authority
JP
Japan
Prior art keywords
thickness
substrate
silicon
silicon substrate
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2423790A
Other languages
Japanese (ja)
Inventor
Juichi Sakamoto
坂本 樹一
Hiroshi Yasuda
洋 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2423790A priority Critical patent/JPH03228326A/en
Publication of JPH03228326A publication Critical patent/JPH03228326A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to form a SOI substrate provided with a semiconductor layer, which has a good crystal quality and is thin, by a method wherein the thickness, at an arbitrary position, of a first silicon substrate ground to a constant thickness is measured by a laser interferometric thickness measuring device, the thickness at other arbitrary position is ground by a grinder with pressing force being adjusted, the grinding and the measurement are repeated. CONSTITUTION:In the manufacturing method of an SOI substrate 5 with a process, wherein a second silicon substrate 2 is laminated on a first silicon substrate 1 via an insulating film (a SOG film) 3 and the substrate 1 is ground to form a thin silicon layer 13, the thickness at an arbitrary position of the substrate 13 ground to a constant thickness is measured by a laser interference thickness measuring device 6, the thick ness at other arbitrary position is ground by a grinder 7 with pressing force being adjusted, and while the grinding and the measurement are repeated, the above first silicon substrate 13 is formed into the thin silicon layer, whose whole surface has a prescribed thickness. Thereby, the SOI substrate having the silicon layer, which has a good crystal quality and has a very thin thickness of 0.1mum or thereabouts, can be formed and a semiconductor element having high performances, such as a high-speed operation and the like, can be formed using the SOI substrate.

Description

【発明の詳細な説明】 [概要] 半導体装置の製造方法のうち、SOI基板の形成方法に
関し、 結晶品質の良い薄い半導体層を設けたSOI基板を形成
することを目的とし、 第1シリコン基板と第2シリコン基板とからなる2枚の
シリコン基板を絶縁膜を介して張り合わせ、第1シリコ
ン基板を研削して薄いシリコン層を形成するSOI基板
の製造方法において、一定厚みまで研削した前記第1シ
リコン基板における任意位置の厚みをレーザ干渉厚み測
定器で測定し、且つ、他の任意位置を加圧力を調整しつ
つ研削器で研削し、該研削と測定を繰り返えしながら前
記第1シリコン基板全面を所定厚みをもった薄いシリコ
ン層に形成する工程が含まれることを特徴とする。
[Detailed Description of the Invention] [Summary] Of the methods for manufacturing semiconductor devices, this method relates to a method for forming an SOI substrate. In the method for manufacturing an SOI substrate, the first silicon substrate is ground to a certain thickness, and the first silicon substrate is ground to a certain thickness. Measure the thickness of an arbitrary position on the substrate with a laser interference thickness measuring device, and grind other arbitrary positions with a grinder while adjusting the pressing force, and repeat the grinding and measurement to remove the first silicon substrate. It is characterized in that it includes a step of forming a thin silicon layer with a predetermined thickness over the entire surface.

[産業上の利用分野] 本発明は半導体装置の製造方法のうち、SOI基板の形
成方法に関する。
[Industrial Application Field] The present invention relates to a method of forming an SOI substrate among methods of manufacturing a semiconductor device.

近年、益々ICの集積度と機能が向上し、産業全般に亙
り技術の核となってICが役割を果たしつつある。
In recent years, the degree of integration and functionality of ICs has been increasing, and ICs are playing a role as the core of technology in all industries.

従来、ICプロセス技術は微細加工による平面的な高集
積化であったが、リソグラフィの限界から三次元的に半
導体層を積層する三次元ICが要望されており、それは
−次元的な半導体層に形成した高密度素子は容量が附加
して高速動作が困難になってきたことにも原因がある。
Conventionally, IC process technology has focused on two-dimensional high integration through microfabrication, but due to the limitations of lithography, there is a demand for three-dimensional ICs in which semiconductor layers are stacked three-dimensionally. Another reason is that the high-density devices that have been formed have added capacitance, making it difficult to operate at high speed.

これに対し、絶縁層上に半導体層を形成すると容量が減
少して一層の高速化が可能になり、そのような構造とし
てS OI (Silicon On In5ulat
or)構造の半導体装置が検討されており、このような
SOI構造の半導体装置は高速動作の他に、耐放射線、
高温動作に有利な利点をも有している。しかし、SOI
構造の半導体装置を形成するためのSOI基板は、高性
能化・高品質化のためには出来るだけ薄い結晶品質の良
い基板である必要がある。
On the other hand, if a semiconductor layer is formed on an insulating layer, the capacitance will be reduced and higher speeds will be possible.
A semiconductor device with an SOI structure is being considered, and in addition to high-speed operation, a semiconductor device with an SOI structure has
It also has advantages in favor of high temperature operation. However, SOI
An SOI substrate for forming a structured semiconductor device needs to be as thin as possible and have good crystal quality in order to improve performance and quality.

[従来の技術と発明が解決しようとする問題点]従前、
著名なSOI基板としてS OS (Silic。
[Problems to be solved by conventional technology and invention] Previously,
SOS (Silic) is a famous SOI substrate.

n On 5appphire)基板が知られていたが
、母体となるサファイヤ基板が非常に高価で、且つ、サ
ファイヤとシリコンは類似の結晶構造を有しているとは
云うものの、結晶学的にはやはり相異があって格子のミ
スマツチが生じ、余り汎用されるには至らなかった。
However, the sapphire substrate that serves as the base material is very expensive, and although sapphire and silicon have similar crystal structures, they are crystallographically incompatible. This difference caused mismatching of the lattice, so it was not widely used.

そこで、近年、開発されてきた方法にビームアニールを
利用して作成するSOI基板がある。それはシリコン基
板上に酸化シリコン膜(SiOz )膜を熱酸化して生
成し、その上に多結晶シリコン膜(またはアモルファス
シリコン膜)を化学気相成長法によって被着する。次い
で、その多結晶シリコン膜を、例えば、レーザビーム(
その他の電子線ビーム、光ビームなどが用いられる)で
走査して加熱(アニール)溶融し、多結晶シリコン膜を
再結晶化して結晶シリコン膜を生成する。この結晶シリ
コン膜に半導体素子を形成するという方法である。
Therefore, a method that has been developed in recent years includes SOI substrates that are manufactured using beam annealing. It is produced by thermally oxidizing a silicon oxide (SiOz) film on a silicon substrate, and depositing a polycrystalline silicon film (or amorphous silicon film) thereon by chemical vapor deposition. Next, the polycrystalline silicon film is exposed to, for example, a laser beam (
The polycrystalline silicon film is heated (annealed) and melted by scanning with other electron beams, light beams, etc.), and the polycrystalline silicon film is recrystallized to produce a crystalline silicon film. This is a method of forming a semiconductor element on this crystalline silicon film.

しかし、この方法で作成したSOI基板は多結晶シリコ
ン膜を完全に単結晶化することが難しく、従って、やむ
なく欠陥が多く、品質の良くない結晶シリコン膜に半導
体素子を形成しなければならない欠点がある。
However, the SOI substrate created using this method has the disadvantage that it is difficult to completely convert the polycrystalline silicon film into a single crystal, and therefore semiconductor elements must be formed on a crystalline silicon film that has many defects and is of poor quality. be.

また、シリコン基板の深い位置に高加速電圧・大電流に
よって酸素イオンを注入し、次いで、熱処理して注入イ
オンを活性化して、表面の薄い半導体層の下にSiO□
膜層を形成する方法(SIMOX法(Separati
on by IMplanted OXygen))が
提案されている。この方法によれば、表面の薄い半導体
層は引上げ法によって作成した単結晶半導体層であり、
結晶品質が良い筈であるが、イオン注入時にかなりの結
晶欠陥を発生して、結晶欠陥や結晶転位の少ない半導体
層を得ることが困難である。
In addition, oxygen ions are implanted deep into the silicon substrate using high acceleration voltage and large current, and then the implanted ions are activated by heat treatment to form SiO□ under the thin semiconductor layer on the surface.
Method for forming film layers (SIMOX method (Separate)
on by Implanted OXygen)) has been proposed. According to this method, the thin semiconductor layer on the surface is a single crystal semiconductor layer created by a pulling method,
Although the crystal quality is supposed to be good, considerable crystal defects are generated during ion implantation, making it difficult to obtain a semiconductor layer with few crystal defects and crystal dislocations.

そこで、最近、シリコン基板(シリコンウェハー)面を
熱酸化してSi0g膜を生成し、2枚のシリコン基板面
の5iOz膜相互を張り合わせて酸素中(または窒素中
)で加熱して接合し、次いで、一方のシリコン基板を他
面より機械的に研削して薄い半導体層を形成する、所謂
、張り合わせ法が検討されている。この方法によれば結
晶品質の良い薄い半導体層を形成することができる利点
があるが、一方、研削の平面度制御性以上に均一で薄い
半導体層を形成することが難しく、例えば、膜厚2〜3
μm以下に薄い半導体層を形成することは困難である。
Therefore, recently, a silicon substrate (silicon wafer) surface is thermally oxidized to produce a Si0g film, the 5iOz films on the two silicon substrate surfaces are pasted together and bonded by heating in oxygen (or nitrogen), and then A so-called bonding method is being considered, in which one silicon substrate is mechanically ground from the other side to form a thin semiconductor layer. This method has the advantage of being able to form a thin semiconductor layer with good crystal quality, but on the other hand, it is difficult to form a uniform and thin semiconductor layer due to the flatness controllability of grinding. ~3
It is difficult to form a semiconductor layer as thin as μm or less.

他方、SOI構造の半導体装置は膜厚0.2μm以下に
薄くして半導体素子を形成することに附加容量の減少な
どのメリットがあり、上記のような膜厚2〜3μm程度
の厚い半導体層に素子を形成しても、高速動作などの素
子特性の改善が限定される欠点がある。
On the other hand, for semiconductor devices with an SOI structure, forming a semiconductor element with a thickness of 0.2 μm or less has the advantage of reducing additional capacitance, and it is difficult to form a semiconductor device with a thickness of about 2 to 3 μm as described above. Even if the device is formed, there is a drawback that improvement of device characteristics such as high-speed operation is limited.

本発明はこのような欠点を取り除いて、結晶品質の良い
薄い半導体層を設けたSOI基板を形成することを目的
とした半導体装置の製造方法を提案するものである。
The present invention proposes a method for manufacturing a semiconductor device with the purpose of eliminating such drawbacks and forming an SOI substrate provided with a thin semiconductor layer of good crystal quality.

[問題点を解決するための手段] その目的は、第1シリコン基板と第2シリコン基板とか
らなる2枚のシリコン基板を絶縁膜を介して張り合わせ
、第1シリコン基板を研削して薄いシリコン層を形成す
るSOI基板の製造方法において、 一定厚みまで研削した前記第1シリコン基板における任
意位置の厚みをレーザ干渉厚み測定器で測定し、且つ、
他の任意位置を加圧力を調整しつつ研削器で研削し、該
研削と測定を繰り返えしながら前記第1シリコン基板全
面を所定厚みをもった薄いシリコン層に形成する工程が
含まれる製造方法によって達成される。
[Means for Solving the Problem] The purpose is to bond two silicon substrates consisting of a first silicon substrate and a second silicon substrate with an insulating film interposed therebetween, and to grind the first silicon substrate to form a thin silicon layer. In the method of manufacturing an SOI substrate, the thickness of the first silicon substrate ground to a certain thickness is measured at an arbitrary position using a laser interference thickness measuring device, and
A manufacturing process that includes a step of grinding other arbitrary positions with a grinder while adjusting the pressing force, and forming a thin silicon layer with a predetermined thickness over the entire surface of the first silicon substrate while repeating the grinding and measurement. achieved by the method.

[作用] 即ち、本発明は、張り合わせ法における前期処理工程と
して、従来と同様に、一定厚み(例えば、2μmの厚み
)まで研削し、次いで、後期処理工程として微細に加圧
力を調整しながら第1シリコン基板(薄いシリコン層)
を研削し、その研削位置の厚みをレーザ干渉計で測定す
る。そのような測定と研削をくりかえして、薄いシリコ
ン層(例えば、0.2μmの厚み)に形成する。
[Function] That is, in the present invention, as an earlier treatment step in the bonding method, grinding is performed to a certain thickness (for example, 2 μm thickness) as in the past, and then, as a later treatment step, the second treatment step is performed while finely adjusting the pressing force. 1 Silicon substrate (thin silicon layer)
The thickness at the grinding position is measured using a laser interferometer. Such measurement and grinding are repeated to form a thin silicon layer (eg, 0.2 μm thick).

このようにして、SOI基板をサブミクロンの厚みに薄
く形成し、そのSOI基板を用いると、高速動作など高
性能な半導体素子を作成することができる。
In this way, by forming a thin SOI substrate to a submicron thickness and using the SOI substrate, it is possible to create a high-performance semiconductor device such as high-speed operation.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第4図(a)〜(e)はSOI基板の前期処理工程順断
面図を示しており、順を追って説明すると、第4図(a
)参照;シリコン基板11(厚さ数百μm)の表面に硼
素(B)を拡散、または、イオン注入して、厚さ200
0人程度0不純物層12を形成する。且つ、この不純物
層12の不純物濃度は10”/Cl113程度に高濃度
にする。
FIGS. 4(a) to 4(e) show cross-sectional views of the SOI substrate in the order of the initial processing steps.
) Reference: Boron (B) is diffused or ion-implanted into the surface of the silicon substrate 11 (thickness of several hundred μm) to a thickness of 200 μm.
A zero impurity layer 12 is formed. Further, the impurity concentration of this impurity layer 12 is set to be as high as about 10''/Cl113.

第4図(b)参照;次いで、不純物層12の上に気相エ
ピタキシャル成長法によって膜厚2μm程度のシリコン
層13(シリコン単結晶層)を形成する。
Refer to FIG. 4(b); Next, a silicon layer 13 (silicon single crystal layer) having a thickness of about 2 μm is formed on the impurity layer 12 by vapor phase epitaxial growth.

このシリコン基板11.不純物層12.シリコン層13
からなる基板を第1シリコン基板1とする。
This silicon substrate 11. Impurity layer 12. silicon layer 13
A substrate consisting of the following will be referred to as a first silicon substrate 1.

第4図(C)参照;次いで、そのシリコン基板1の表面
(シリコン層13の表面)にSOC(スピンオングラス
)膜3を塗布し、その上に第2シリコン基板2(厚さ数
百μm)を強く圧着し、加熱してSOG膜3を固化させ
る。この時、SOG膜3は熱処理によってSiO□膜化
する。
See FIG. 4(C); Next, a SOC (spin-on glass) film 3 is applied to the surface of the silicon substrate 1 (the surface of the silicon layer 13), and a second silicon substrate 2 (thickness of several hundred μm) is applied thereon. are firmly pressed together and heated to solidify the SOG film 3. At this time, the SOG film 3 is converted into a SiO□ film by heat treatment.

第4図(d)参照;次いで、第1シリコン基板1の裏面
(シリコン基板11の表出面)からエツチングしてシリ
コン基板11全部を除去する。この除去には、最初に弗
酸・硝酸の混合液を用いてその大部分をエツチング除去
し、次いで、シリコン基板11の残存厚みが数十μmに
なればアルカリエツチング液にてエツチングしてシリコ
ン基板11の全部を除去する。硼素をドーピングした不
純物層12はアルカリエツチング液ではエツチングされ
ないために、不純物層12がエツチングストッパーにな
って不純物層12でエツチングが停止する。
Refer to FIG. 4(d); next, the entire silicon substrate 11 is removed by etching from the back surface of the first silicon substrate 1 (the exposed surface of the silicon substrate 11). To remove this, first, most of the silicon substrate 11 is etched away using a mixed solution of hydrofluoric acid and nitric acid, and then, when the remaining thickness of the silicon substrate 11 reaches several tens of μm, the silicon substrate is etched using an alkaline etching solution. Remove all 11. Since the impurity layer 12 doped with boron is not etched by an alkaline etching solution, the impurity layer 12 acts as an etching stopper and etching is stopped at the impurity layer 12.

なお、この第4図(d)からは第4図(C)の図を逆さ
にした図を示している。
Note that FIG. 4(d) shows an inverted view of FIG. 4(C).

第4図(e)参照;次いで、酸化雰囲気中で高温度に加
熱すると不純物の多い不純物層12が素早く酸化してS
iO□膜になり、この5i02膜のみをエツチングして
除去すればシリコン層13が露出し、このようにして、
第2シリコン基板2上に絶縁膜(SOG膜3)を介して
シリコン層13を設けたSOI基板が完成する。
See FIG. 4(e); Next, when heated to a high temperature in an oxidizing atmosphere, the impurity layer 12 containing many impurities is quickly oxidized and S
It becomes an iO□ film, and if only this 5i02 film is etched and removed, the silicon layer 13 is exposed, and in this way,
An SOI substrate is completed in which a silicon layer 13 is provided on the second silicon substrate 2 via an insulating film (SOG film 3).

上記が張り合わせ法における前期処理工程であり、以上
は従来と同様の処理方法で本発明にかかる特徴ではない
。且つ、上記方法の他に、例えば、前記したように、2
枚のシリコン基板をSin、膜を介して張り合わせて接
合し、一方のシリコン基板を研削して薄いシリコン層を
形成する、所謂、オーツドックスなSOI基板の形成方
法を用いても良い。
The above is the first stage processing step in the lamination method, and the above processing method is the same as the conventional processing method and is not a feature of the present invention. In addition to the above method, for example, as described above, 2
A so-called orthodox method for forming an SOI substrate may be used, in which two silicon substrates are pasted and bonded via a Si film, and one silicon substrate is ground to form a thin silicon layer.

しかし、この前期処理工程が終了したSOI基板のシリ
コン層の厚みは精々2μm程度である。
However, the thickness of the silicon layer of the SOI substrate after this initial treatment step is approximately 2 μm at most.

従って、前期処理工程が終了した後、以下に説明する後
期処理工程を適用するのが本発明の特徴である。
Therefore, it is a feature of the present invention that the latter treatment step described below is applied after the first treatment step is completed.

第1図はSOI基板の後期処理工程図で、図中の記号5
は第2シリコン基板2とSOG膜3(絶縁膜)とシリコ
ン層13とからなるSOI基板、6はレーザ干渉厚み測
定器、7は研削器、8はXYステージ、9はレーザ干渉
計である。SOI基板5はXYステージ8上に真空チャ
ッキングされて、上下左右に微細に調整されながら移動
でき、その高さ位置はレーザ干渉計9で制御されている
。このようなXYステージ上のSOI基板5の上部に厚
み測定器6と研削器7とを固定させている。そして、x
Yステージ8を移動させてSOI基板5上のシリコン層
13面の測定と研削をくりかえす。
Figure 1 is a diagram of the latter stage processing process for SOI substrates, with symbol 5 in the figure.
1 is an SOI substrate consisting of a second silicon substrate 2, an SOG film 3 (insulating film), and a silicon layer 13; 6 is a laser interference thickness measuring device; 7 is a grinder; 8 is an XY stage; and 9 is a laser interferometer. The SOI substrate 5 is vacuum chucked on an XY stage 8 and can be moved vertically and horizontally while being finely adjusted, and its height position is controlled by a laser interferometer 9. A thickness measuring device 6 and a grinding device 7 are fixed above the SOI substrate 5 on such an XY stage. And x
The Y stage 8 is moved and the measurement and grinding of the surface of the silicon layer 13 on the SOI substrate 5 are repeated.

そうすれば、シリコン層13の厚みを0.1μm程度ま
で薄く研削することができる。
In this way, the thickness of the silicon layer 13 can be reduced to about 0.1 μm.

第2図はレーザ干渉厚み測定器を説明する図であって、
レーザ光源61からSOI基板にレーザ光を斜め方向か
ら照射し、SOI基板のシリコン層13の表面および裏
面(裏面はSOGOsO4面になる)から反射して交叉
するレーザ光の干渉縞をCCD検出器62で検出する。
FIG. 2 is a diagram illustrating a laser interference thickness measuring device,
A laser light source 61 irradiates the SOI substrate with laser light from an oblique direction, and a CCD detector 62 detects the interference fringes of the laser light reflected and intersecting from the front and back surfaces of the silicon layer 13 of the SOI substrate (the back surface becomes the SOGOsO4 surface). Detect with.

即ち、レーザ光の斜め方向からの入射角(θ)を変えて
、CCD検出器62で検出するレーザ光の干渉縞がちょ
うど消滅すると、シリコン層13が所要厚み(例えば0
.2μm)になるように設定し、シリコン層13の膜厚
の厚い初期にCCD検出器62によって複数の干渉縞が
検出されるが、研削が進むと干渉縞が次第に減少してち
ょうど消滅した時点で研削を中止する。
That is, when the interference fringes of the laser beam detected by the CCD detector 62 just disappear by changing the incident angle (θ) of the laser beam from the oblique direction, the silicon layer 13 has a required thickness (for example, 0
.. 2 μm), and a plurality of interference fringes are detected by the CCD detector 62 at the beginning when the silicon layer 13 is thick, but as the grinding progresses, the interference fringes gradually decrease until they just disappear. Stop grinding.

そうすれば、シリコン層13の厚みがちょうど所要厚み
になり、このようにしてサブミクロン程度の厚みに正確
に研削するものである。
By doing so, the thickness of the silicon layer 13 becomes exactly the required thickness, and in this way, the silicon layer 13 is precisely ground to a thickness of approximately submicron.

次に、第3図は研削器を説明する図であり、シリコン層
13(SOI基板)に接触する研削面71には研磨剤、
例えばダイヤモンドペーストを付着させである。そして
、研削器全体を数千rpmの高速で回転させて研削する
。その際、研削面71の背後にピエゾ素子72を配置し
ておき、そのピエゾ素子の印加電圧を変化させて研削面
の加圧力を微細に調整しながらシリコン層を研削する。
Next, FIG. 3 is a diagram illustrating a grinder, in which a grinding surface 71 that contacts the silicon layer 13 (SOI substrate) has an abrasive,
For example, by applying diamond paste. Then, the entire grinder is rotated at a high speed of several thousand rpm for grinding. At this time, a piezo element 72 is placed behind the grinding surface 71, and the silicon layer is ground while finely adjusting the pressure applied to the grinding surface by changing the voltage applied to the piezo element.

そうすれば、サブミクロン程度の薄いシリコン層に正確
に研削することが可能になる。なお、研削面の加圧力の
調整にはピエゾ素子の他、弾性密閉体に気体を封入し、
その気体を出入させて圧力を制御する方法を採っても良
い。
This makes it possible to precisely grind the silicon layer to a submicron thickness. In addition to the piezo element, the pressure applied to the grinding surface can be adjusted by filling an elastic body with gas.
A method may be adopted in which the pressure is controlled by letting the gas in and out.

上記が本発明にがかるSOI基板の形成方法で、このよ
うな方法で形成すれば、結晶品質の良い0゜1μm程度
の極めて薄いシリコン層を有するSOI基板が作成でき
る。
The above is the method for forming an SOI substrate according to the present invention, and by forming it by such a method, an SOI substrate having an extremely thin silicon layer of about 0.1 μm with good crystal quality can be created.

[発明の効果] 以上の実施例から明らかなように、本発明によれば結晶
品質の良い極めて薄いシリコン層をもったSOI基板が
作成され、そのようなSOI基板を用いたIC,LSI
などの半導体装置は附加容量が減少して高性能化でき、
且つ、三次元に積層すれば高密度化、高集積化できて一
層の高性能化が図れるものである。
[Effects of the Invention] As is clear from the above embodiments, according to the present invention, an SOI substrate having an extremely thin silicon layer with good crystal quality can be created, and ICs and LSIs using such an SOI substrate can be manufactured.
Semiconductor devices such as
In addition, if they are stacked three-dimensionally, it is possible to achieve higher density and higher integration, thereby achieving even higher performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はSOI基板の後期処理工程図、第2図はレーザ
干渉厚み測定器を説明する図、第3図は研削器を説明す
る図、 第4図(a)〜(e)はSOI基板の前期処理工程順断
面図である。 図において、 1は第1シリコン基板、 2は第2シリコン基板、 3はSOG膜、 5はSO■基板、 6はレーザ干渉厚み測定器、 7は研削器、 8はXYステージ、 9はレーザ干渉計、 11はシリコン基板、 12は不純物層、 13はシリコン層、 61はレーザ光源、 62はCCD検出器、 71は研削面、 72はピエゾ素子 を示している。 7簀
Figure 1 is a diagram of the later processing steps for SOI substrates, Figure 2 is a diagram explaining the laser interference thickness measuring device, Figure 3 is a diagram explaining the grinder, and Figures 4 (a) to (e) are SOI substrates. FIG. In the figure, 1 is the first silicon substrate, 2 is the second silicon substrate, 3 is the SOG film, 5 is the SO2 substrate, 6 is the laser interference thickness measuring device, 7 is the grinder, 8 is the XY stage, 9 is the laser interference In total, 11 is a silicon substrate, 12 is an impurity layer, 13 is a silicon layer, 61 is a laser light source, 62 is a CCD detector, 71 is a ground surface, and 72 is a piezo element. 7 screens

Claims (1)

【特許請求の範囲】[Claims] 第1シリコン基板と第2シリコン基板とからなる2枚の
シリコン基板を絶縁膜を介して張り合わせ、第1シリコ
ン基板を研削して薄いシリコン層を形成するSOI基板
の製造方法において、一定厚みまで研削した前記第1シ
リコン基板における任意位置の厚みをレーザ干渉厚み測
定器で測定し、且つ、他の任意位置を加圧力を調整しつ
つ研削器で研削し、該研削と測定を繰り返えしながら前
記第1シリコン基板全面を所定厚みをもった薄いシリコ
ン層に形成する工程が含まれてなることを特徴とする半
導体装置の製造方法。
In a method for manufacturing an SOI substrate, in which two silicon substrates consisting of a first silicon substrate and a second silicon substrate are bonded together via an insulating film, and the first silicon substrate is ground to form a thin silicon layer, the first silicon substrate is ground to a certain thickness. The thickness of the first silicon substrate at an arbitrary position is measured with a laser interference thickness measuring device, and other arbitrary positions are ground with a grinder while adjusting the pressing force, and the grinding and measurement are repeated. A method for manufacturing a semiconductor device, comprising the step of forming a thin silicon layer having a predetermined thickness over the entire surface of the first silicon substrate.
JP2423790A 1990-02-01 1990-02-01 Manufacture of semiconductor device Pending JPH03228326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2423790A JPH03228326A (en) 1990-02-01 1990-02-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2423790A JPH03228326A (en) 1990-02-01 1990-02-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03228326A true JPH03228326A (en) 1991-10-09

Family

ID=12132646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2423790A Pending JPH03228326A (en) 1990-02-01 1990-02-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03228326A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006106710A1 (en) * 2005-04-04 2006-10-12 Shin-Etsu Handotai Co., Ltd. Bonded wafer manufacturing method, bonded wafer, and plane polishing apparatus
JP2007059523A (en) * 2005-08-23 2007-03-08 Disco Abrasive Syst Ltd Method and apparatus for machining substrate
JP2009170694A (en) * 2008-01-17 2009-07-30 Disco Abrasive Syst Ltd Thickness measuring device and grinding device provided with the same
JP2012111008A (en) * 2010-11-25 2012-06-14 Disco Corp Grinding device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006106710A1 (en) * 2005-04-04 2006-10-12 Shin-Etsu Handotai Co., Ltd. Bonded wafer manufacturing method, bonded wafer, and plane polishing apparatus
JP2007059523A (en) * 2005-08-23 2007-03-08 Disco Abrasive Syst Ltd Method and apparatus for machining substrate
JP2009170694A (en) * 2008-01-17 2009-07-30 Disco Abrasive Syst Ltd Thickness measuring device and grinding device provided with the same
JP2012111008A (en) * 2010-11-25 2012-06-14 Disco Corp Grinding device

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