JPS5893266A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a crystal distrotion in a laminated structure by reducing the area of a semiconductor layer smaller toward the upper stage when forming the semiconductor layer having an electric circuit element in the interior or on the surface and an insulating layer having a passage which transmits a signal between the layers while laminating them, and forming an IC by superposing several stages of the structure. CONSTITUTION:A plurality of electric circuits 2 which are made of MOS type semiconductor elements are formed on the surface of an Si wafer 1, and the prescribed terminal 9 are mounted at both sides. Then, a polycrystalline or non- crystalline Si layer 4 is grown through an SiO2 film on the overall surface, electric circuits 5 corresponding to the circuits 2 are also formed thereat, and terminals 10 are similarly mounted at both sides. Subsequently, the layer 4 and the film 3 are etched to isolate the circutis 5, 2 in an insular shape on the wafer 1, the laminate of the similar configuration is formed on them, is cut and isolated between the islands, thereby forming many ICs. In this structure, the circuits 2, 5 are reduced in the area toward the upper part, thereby reducing the crystal distortion and providing an IC in which the characteristics are not lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit having a product+1 structure area of a semiconductor layer and an insulating layer.

Prior Art and its Problems In order to improve the degree of integration of semiconductor integrated circuits, conventional techniques have focused exclusively on reducing the geometrical plane dimensions, but a crystalline conductor layer t'/4 has been formed on an insulating film. With the development of semiconductor technology, there is a method of forming elements and three-dimensionally stacking constant semiconductor layers with insulating layers interposed therebetween to further increase the degree of integration.

On the other hand, a semiconductor layer on an insulating film generally tends to contain a large amount of crystal defects, as seen in SOS (single crystal thin film of silicon on single crystal sapphire).
- This is because the thermal expansion coefficients of each semiconductor layer are different, so plastic deformation occurs in the semiconductor layer during the process of changing mIf from crystal growth m degrees to room temperature, and a large number of specified dislocations occur. This trend is semiconductor! As the thickness of the insulating layer increases, the higher the layer, the more strain it causes and the number of crystal defects increases, and in extreme cases, cracks may appear in the structure itself.

From the point of view of semiconductor device characteristics, these defects a, a decrease in the degree of carrier transfer dIh, and an increase in electrical leakage of the junction lead to disadvantages such as a decrease in operating speed and an increase in power consumption.

Furthermore, an increase in the number of pieces increases the difficulty of dicing the formed Ueno 1 into element pieces,
In addition to the effect of strain during lamination, the laminated semiconductor layer and insulation I-
It becomes easy to cause peeling, etc.

The number of electrical signal input/output terminals of an integrated circuit increases as the degree of integration increases. In many cases, in order to store the entire element piece in a VC container (package) and finish it in a usage configuration, metal is connected between the electric signal input/output terminal of the element piece and the terminal of the container for signal input/output from the container to the outside. It is necessary to bond with a thin wire (wire bonding).

At this time, the output terminals of the element pieces are placed around the element pieces in order to prevent the thin metal wires from coming into contact with each other, but since the output terminals originally occupy a large area geometrically, There is a limit on the number of output terminals that can be placed (t/Ci), and it is impossible to place output terminals only around the top surface of the stacked structure due to the density of the integrated circuit due to the stacked structure. However, since Vc is essential, wire bonding using the above-mentioned thin metal wires is likely to cause contact accidents, especially between the thin metal wires.

Purpose of the Invention Purpose of the Invention The purpose of the present invention is to reduce the crystal strain associated with the porcelain structure, improve carrier mobility, and reduce electrical coke in the bonding process. fl
The object of the present invention is to provide a product of 1-purchased elements that enables the arrangement of terminals that facilitates the production of electric whistles from element pieces.

Summary of the Invention The present invention has a product structure of one semiconductor tank with no insulation or full valves, in which the area of the upper semiconductor layer is smaller than the bottom t*XO, and output terminals for electrical signals are arranged around each semiconductor layer. It is characterized by the presence of

Advantages of the invention Adoption of Vc processing in such a structure, improvement of the phenomenon that occurs in stacked conventional devices where electrical characteristics deteriorate as the upper layers go, and reduction of mechanical strain when all device pieces are cut from a silicon wafer. Suppression of propagation to the element region, and I/Cv: I element element pieces are all housed in a container and connected to the outside using thin metal wires, 1
Examples of the invention The present invention will be explained below using an example.

As shown in Fig. 1aK, an electric circuit Z made of MO8 type semiconductor elements is provided on the surface of a silicon wafer l using ordinary semiconductor element manufacturing techniques such as oxidation, diffusion, CVI), ion implantation, and lithography, and then an electric circuit Z is formed on the entire surface of the silicon wafer l using ordinary semiconductor element manufacturing techniques such as oxidation, diffusion, CVI), ion implantation, and lithography. For example, a silicon oxide film 3 is deposited as an interlayer insulating layer. After partially opening holes in this oxide film and exposing the entire surface of the silicon wafer 1C, a polycrystalline or amorphous silicon layer 3 is deposited, and this layer is further subjected to laser annealing or RT beam annealing. After all the treatments, the crystalline silicon layer 4 is obtained.

Opening portion a silicon 1i1 provided in this special interlayer insulating layer
Machine D to fully maintain crystal orientation alignment between 4 and the silicon wafer
At the same time, it also functions as a path for electrically connecting the electric circuit formed on the surface of the silicon wafer and the electric circuit 5 formed on the upper silicon layer 1-4 as shown in FIG. Is aluminum particularly heat-treated when forming a layer M on the silicon 1-4 surface? If necessary, conditions or means must be used that do not affect the electric circuits already formed on the 'F layer silicon wafer, and after the electric circuit 5 is formed, the semiconductor layer 4 and the interlayer #1 must be removed. -3 Partially etched away as shown in Figure 1C.

At this time, the area of the semiconductor layer 4 and the insulating layer to be left is set to be V'% smaller than the area of the electric circuit including the output terminal 9 formed on the surface of the underlying silicon wafer. After this Sara V
c As shown in FIG. 1 dVC, after depositing an interlayer insulating layer and a suitable insulating layer, such as a silicon oxide film 6, on the entire surface of the wafer, openings are formed in required parts on the electrical circuit 5, and then polycrystalline or amorphous After depositing the silicon layer 7, the characteristics of the electrical circuit 5 change by %.
For example, laser annealing or 1'J'!
The entire crystallization process is performed by beam annealing, etc. Thereafter, a desired circuit 8 is formed on the crystalline silicon layer 7. At this time, the electric circuit 'N1 is formed so as not to overlap the output terminal of the electric circuit 5, and after the electric circuit is formed, a crystalline silicon layer is formed so that the output terminal 10 of the electric circuit 5 is exposed as shown in FIG. 7 and the insulation film 6 are etched away leaving the electrical circuit 8. In this way, an integrated circuit element having a three-layer laminated structure of silicon, the area of which decreases toward the L-shaped upper layer shown in FIG. 2, is formed. Although it is a laminated structure of elements i-j 31-, the thickness between the element pieces is the same as that of a single-layer structure, so it can be cut normally! , method such as diamond scriber, laser scriber (etc.)
It becomes possible to cut into element pieces without giving any negative shadow to the elements around the area. In addition, the output terminal of the element is always in contact with each pressure, and after that, the silicon wafer 1 is exposed, but since the thickness of the original silicon wafer is relatively thin, cracks or mechanical distortion occur when cutting. The degree of expansion in the lateral direction is the same as that of conventional devices, and there is no particular expansion of the area that would cause device deterioration due to rough cutting, which would be expected due to the layered structure.

After the cut element pieces are housed and fixed in a package, the element output terminals arranged around each layer are connected to terminals of the container by wire bonding using thin aluminum wires. At this time, wire bonding is performed from the lowest element output terminal to the upper layer output terminals in order, thereby preventing the F-aluminum fine wires from coming into contact with each other. Characteristics of the laminated structure element thus completed When adding the gold side to the basic element -q MOS type transistor,
In a multilayer structure element in which the upper layer and the lower layer have the same area, the carrier mobility of the channel of the transistor formed in the third layer is about 50% of that of the first silicon substrate, whereas the upper layer is smaller in area than the lower layer 19. In the multilayer structure element of the present invention, the carrier mobility f[
! In about 80% of the -/- silicon substrates, the improvement effect achieved by adopting the structure of the present invention is clearly seen. Like Maku,
The unit of the junction formed in the third layer and the junction formed in the first layer substrate silico y VC Electrical leakage of laminated layer 9 When comparing the total, it is found that the upper layer and r layer have the same area and the product l-7 is approximately 2. While the deterioration is ~3 orders of magnitude, in the laminated structure of the present invention, such as a pebble-like structure with a soil layer below += C, the deterioration remains at 1 fvC by about one order of magnitude, and an improvement effect by suppressing crystal strain can be seen. .

Other Embodiments of the Invention In this embodiment, an example of a silicon oxide film as a silicon 1 insulating layer as a semiconductor t- was described, but germanium gallium arsenide, gallium phosphide, or silicon may be used as a semiconductor layer in addition to a1 silicon. In the case of a structure in which two or three types of these semiconductors are combined, t2 is also used as an insulating layer. Needless to say, even in the case of a structure in which one or two or four types are combined, the same effect as that of a canopy can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (e1g1) are sectional views of the manufacturing process of a semiconductor integrated circuit having the structure of the present invention, and FIG. 2 is a perspective view of the semiconductor integrated circuit having the structure of the present invention. ...Semiconductor I-13,6...Insulating layer, 2.5.8...'Electric circuit, 9,1
0...Terminal agent Noriyuki Chika
1 other personFigure 1

Claims (1)

[Claims] 1) A layered structure of a semiconductor layer and an insulating layer, the semiconductor layer includes an electric circuit element inside or on the surface, and the insulating layer VC includes a path for transmitting signals between the semiconductor layers. , a semiconductor integrated circuit characterized in that the area of the semiconductor I-P becomes smaller as one goes to an upper layer in the stacking order. 2. The semiconductor integrated circuit described in Patent No. 1, characterized in that terminals are attached to the surfaces exposed on the steps of each semiconductor layer.