JP3189055B2 - Compound semiconductor device wafer and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device wafer useful for inexpensively manufacturing a compound semiconductor device and a method suitable for manufacturing the compound semiconductor device wafer.

[0002] Group 3 or 5 or 2 or 4 compound semiconductors, such as GaAs, are used as constituent materials for high-speed and low-power-consumption integrated circuit devices or low-noise semiconductor devices. .

In order to use such compound semiconductor devices in a wider range in the future, cost reduction is the most important issue. However, this involves increasing the diameter of compound semiconductor device wafers and reducing the cost. Is necessary.

However, compound semiconductors are generally brittle, so that it is difficult to increase the diameter of the compound semiconductor. Moreover, there is a high possibility that the compound semiconductor will be damaged during the wafer process. For some reasons, it is not easy to reduce the price. Therefore, development and research in that respect are desired.

[0005]

2. Description of the Related Art Conventionally, in order to realize a large-diameter and low-cost compound semiconductor device substrate, a compound semiconductor layer is grown on a Si substrate which is easy and large in diameter and inexpensive. .

FIG. 12 is a cutaway side view of a main part of a conventional example of a wafer (hereinafter, referred to as a composite wafer) formed by growing a GaAs layer on a Si substrate. In the figure, 1 indicates a Si substrate, and 2 indicates a GaAs layer.

By the way, in this composite wafer, S
Since i and GaAs have different lattice constants, dislocation defects occur in GaAs. In addition, since the dislocation defects are generated not only due to the difference in lattice constant but also due to the difference in the coefficient of thermal expansion during the heat treatment in the process of forming the semiconductor device, the number thereof is considerably large. turn into.

Therefore, when an GaAs / AlGaAs superlattice is inserted at the interface between the Si substrate 1 and the GaAs layer 2 or when the GaAs layer 2 is grown, the initial temperature is lowered and the process is started. Means are taken such that the generation of dislocation defects is suppressed by increasing the temperature as the temperature increases.

[0009]

As described above,
Even if various measures are taken for the composite wafer, it is extremely difficult to alleviate warpage or distortion over the entire surface. According to the present invention, a compound semiconductor substrate is laminated on a Si substrate by a simple means so that a wafer having no bending or distortion and therefore having few dislocation defects can be obtained.

[0010]

Is In the compound semiconductor device wafer and a manufacturing method thereof according to the present invention, in order to solve the problems], multiple on (1) a silicon semiconductor substrate (e.g. a silicon substrate 21)
Compound semiconductor substrate divided into several pieces (for example, GaAs group
Plates 24A) are spaced from one another and the silicon semiconductor substrate
Metal film that adheres between the substrate and each compound semiconductor substrate
(For example, Ti / Pd film 27)
Or characterized in that it comprises, or,

(2) A plurality of recesses formed on the surface of the silicon semiconductor substrate
(For example, compound half divided into a plurality of portions in the recess 34A)
Conductor substrates (eg, GaAs substrate 31A) are separate
Characterized by being fitted and attached to the
Or,

(3) In the above (2), the inside of the recess of the silicon semiconductor substrate is formed.
A metal film is attached between the compound semiconductor substrate and the
Characterized by being attached by

[0013]

(5) A step of bonding and adhering the back surface of the compound semiconductor substrate to the front surface of the silicon semiconductor substrate, and then dividing the compound semiconductor substrate on the silicon semiconductor substrate into a plurality of parts and independent of each other at intervals. Or a process that shall be included, or

(6) A plurality of compound semiconductor substrates divided into a plurality of recesses formed on the surface of the silicon semiconductor substrate, each of which is individually made to correspond to each other, and fitted with a metal film interposed therebetween, and then heat treatment is performed. And bonding the silicon semiconductor substrate to each compound semiconductor substrate.

[0016]

According to the present invention, the compound semiconductor layer on the Si substrate is divided, so that the
Alternatively, warpage and distortion generated in the subsequent heat treatment step can be reduced, and therefore, generation of dislocation defects can be suppressed. Moreover, by making the divided region of the compound semiconductor layer the same as the divided region of the compound semiconductor device to be formed on the wafer, the subsequent formation process of the compound semiconductor device can proceed in exactly the same manner as when a compound semiconductor substrate is used. it can.

[0017]

1 to 4 are side views (FIG. 1) of a main part cut of a wafer at a process point for explaining a first embodiment of the present invention.
3 to 3) and a plan view (FIG. 4) of a main part.
The details will be described with reference to these figures.

FIG. 1 1- (1) A Ti film 22 and a Pd film 23 are sequentially formed on the surface of a Si substrate 21 by applying a vacuum evaporation method. Examples of main data in this case are as follows. About the Si substrate 21 Diameter: about 10 cm (4 inches) About the Ti film 22 Thickness: 500 [Å] About the Pd film 23 Thickness: 500 [Å]

1- (2) A Ti film 25 and a Pd film 26 are sequentially formed on the back surface of the GaAs substrate 24 by applying a vacuum evaporation method. Examples of main data in this case are as follows. About the GaAs substrate 24 Diameter: about 10 [cm] (4 [inch]) About the Ti film 25 Thickness: 500 [Å] About the Pd film 26 Thickness: 500 [Å] The steps 1- (1) and 1- It goes without saying that (2) may be reversed or simultaneous.

FIG. 2 2- (1) By applying the lamp annealing method, the Si substrate 21 and the GaAs substrate 24 are bonded together via the Ti / Pd film 27 to form a composite wafer. That is, when the front side of the Si substrate 21 and the back side of the GaAs substrate 24 are combined, and the temperature is increased to, for example, about 400 ° C. in a vacuum, the two can be bonded together.

3 and FIG. 4 3- (1) Only the GaAs substrate 24 and the Ti.Pd film 27 are cut along, for example, a divided region for dicing one chip of a compound semiconductor device. Note that the GaAs substrate cut into a die shape is indicated by a symbol 24A. For this cutting, a dicing saw may be used or an etching technique may be used.

3- (2) Thereafter, each GaAs substrate 24 is formed according to a usual technique.
A is a compound semiconductor device, for example, GaAs-MESFE
Complete by incorporating a T integrated circuit device and the like.

The composite wafer prepared according to the first embodiment does not warp or warp, and therefore the occurrence of dislocation defects in the compound semiconductor layer is reduced.
Therefore, when the compound semiconductor device is manufactured, the characteristics become good, and the photographic process at the time of manufacturing can be performed with high accuracy.

By the way, as a matter of course, in the first embodiment, it is impossible to obtain a wafer having a large diameter exceeding the diameter of the GaAs substrate 24, but a means for breaking through this problem is provided by the second embodiment of the present invention. Let me explain. Incidentally, the maximum diameter of a standard GaAs substrate which is frequently used at present is about 10 [cm] (4 as shown in the first embodiment).
[Inch]).

FIGS. 5 to 8 are cutaway side views of a main part of a wafer at important points in a process for explaining a second embodiment of the present invention, and will be described in detail with reference to these drawings. I do.

Referring to FIG. 5, 5- (1) a Ti film 32 and a Pd film 33 are sequentially formed on the back surface of a GaAs substrate 31 by applying a vacuum evaporation method. Examples of main data in this case are as follows. About GaAs substrate 31 Diameter: about 10 [cm] (4 [inch]) About Ti film 32 Thickness: 500 [Å] About Pd film 33 Thickness: 500 [Å]

6- (1) Ga having Ti film 32 and Pd film 33 laminated on the back surface
The As substrate 31 is cut into a die slightly larger than, for example, one chip of a compound semiconductor device. The die-shaped GaAs substrate is indicated by a symbol 31A. here,
The reason why the GaAs substrate 31 is cut to be slightly larger when it is formed into a die is that the GaAs substrate 3 which is formed into a die on the Si substrate 34 is formed.
This is because the accuracy in attaching 1A must be considered. For example, in the case of an integrated circuit chip of 5 [mm] × 5 [mm], it is preferable to divide it into a size of about 5.5 [mm] × 5.5 [mm].

FIG. 7 7- (1) By applying a resist process in lithography technology and a wet etching method in which an etchant is, for example, nitric acid + H ₂ O ₂ , the diameter is, for example, about 15 mm.
On the surface of the [cm] (6 [inch]) Si substrate 34, a recess having a size large enough to receive the GaAs substrate 31A and having a depth of, for example, about 10 [μm] is formed. The place 34A is selectively formed. Since the Ti film and the Pd film formed in the next step enter the recess 34A, the dimensions must be determined in consideration of the thickness thereof.

7- (2) A Ti film 35 and a Pd film 36 are sequentially formed on the surface of the Si substrate 34 by applying a vacuum evaporation method. In this case as well, it is optional whether to process the GaAs substrate 31 or the Si substrate 34 first or simultaneously.

8- (1) A GaAs substrate 31A, which has been die-formed, is placed in the recess 34A of the Si substrate 34, and the temperature is raised to about 400 ° C. in a vacuum to form a Ti.Pd film. 35 to the Si substrate 34 via
The As substrate 31A is bonded.

8- (2) Thereafter, each GaAs substrate 31 is formed according to a usual technique.
A is completed by incorporating the compound semiconductor device into A.

The composite wafer fabricated according to the second embodiment not only has the same advantages as the composite wafer fabricated according to the first embodiment, but also uses a Si substrate 34 having a larger diameter than the GaAs substrate 31. The effect of increasing the diameter can be sufficiently obtained even when considering that it is possible to use the GaAs substrate 31 </ b> A which has been die-bonded and to have a margin of accuracy when bonding the GaAs substrate 31 </ b> A.

In each of the first embodiment and the second embodiment, the thickness of the GaAs substrate is about 500 μm. This is because the GaAs substrate is polished after forming the Ti film and the Pd film. Alternatively, the thickness of the active layer may be reduced to about 100 [μm] by etching or the like.

In addition, for example, an MO
The thickness is, for example, 0.5 [μm] by CVD or MBE.
I-GaAs layer having a thickness of, for example, 400 nm, and an n-AlGaAs layer having a thickness of, for example, 100 nm, and a thickness of, for example, 100 nm.
After the n-GaAs layer is formed, if the first embodiment or the second embodiment is performed, AlGaAs / GaAs
An integrated circuit device composed of an s-based HEMT can be easily manufactured.

FIGS. 9 to 11 show side views of essential parts of a wafer at important points in the process for explaining a third embodiment of the present invention, and will be described in detail with reference to these figures. I do.

9- (1) A SiO ₂ film 42 having a thickness of, for example, about 200 [nm] is formed on the surface of the Si substrate 41 by applying the thermal oxidation method.

10- (1) Resist process in lithography technology and reactive ion etching (RI) using CHF ₃ as an etching gas
By applying the method E), the SiO ₂ film 42 is selectively etched to form an opening 42A corresponding to a semiconductor device formation region slightly larger than one chip of an integrated circuit device.
To form

11- (1) The SiO ₂ film 42 is formed by applying the MOCVD method.
A GaAs substrate 43A having substantially the same thickness as that described above is formed. In this case, a GaAs single crystal is grown on the Si substrate 41 exposed in the opening 42A formed in the SiO ₂ film 42. However, the GaAs single crystal does not grow on the SiO ₂ film 42. Selective growth is performed.

11- (2) Thereafter, each GaAs substrate 43 is formed according to a usual technique.
A is completed by incorporating the compound semiconductor device into A.

The composite wafer prepared according to the third embodiment differs from the composite wafer prepared according to the first or second embodiment in that the Si substrate 41 and the GaAs substrate 43A are not lattice-matched. The resulting dislocation defects cannot be reduced. However, as in the first embodiment and the second embodiment, since the entire surface is hardly bent or distorted, the number of dislocation defects caused by it is far less than that in the case of the prior art.

In this case, the GaAs substrate can be easily made to have a thickness of the active layer at the time of its growth. For example, like the first and second embodiments, for example, the MOCV
I-GaAs on a GaAs substrate by D method or MBE method
Layer, an n-AlGaAs layer, and an n-GaAs layer, and then forming an element isolation or electrode / wiring, the AlGa
An integrated circuit device composed of an As / GaAs HEMT can be easily manufactured.

In each of the above embodiments, the combination of the Si substrate and the GaAs substrate has been described.
InP substrate, InSb substrate, AlA instead of As substrate
Other compound semiconductor substrates, such as an s substrate, an InAs substrate, and a GaSb substrate, can be combined. Further, as a semiconductor device to be incorporated in the obtained composite wafer, MESF
Other than T and HEMT may be used.

[0043]

In the compound semiconductor device wafer and the method of manufacturing the same according to the present invention, a plurality of divided compound semiconductor substrates are mounted on a silicon semiconductor substrate at intervals.

According to the present invention, since the compound semiconductor layer on the Si substrate is divided, it is possible to reduce the warpage and distortion generated during the growth of the compound semiconductor layer or in the subsequent heat treatment step. Therefore, generation of dislocation defects can be suppressed. Moreover, by making the divided region of the compound semiconductor layer the same as the divided region of the compound semiconductor device to be formed on the wafer, the subsequent formation process of the compound semiconductor device can proceed in exactly the same manner as when a compound semiconductor substrate is used. it can.

[Brief description of the drawings]

FIG. 1 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a first embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part of a wafer at a key point in the process for explaining the first embodiment of the present invention.

FIG. 3 is a cutaway side view of a main portion of a wafer at a key point in a process for explaining the first embodiment of the present invention.

FIG. 4 is an explanatory plan view of a main part of a wafer at a key point in the process for explaining the first embodiment of the present invention;

FIG. 5 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a second embodiment of the present invention.

FIG. 6 is a sectional side view of a main part of a wafer at an important part of a process for explaining a second embodiment of the present invention.

FIG. 7 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a second embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a second embodiment of the present invention.

FIG. 9 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a third embodiment of the present invention.

FIG. 10 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a third embodiment of the present invention.

FIG. 11 is a cutaway side view of a main part of a wafer at a key point in a process for explaining a third embodiment of the present invention.

FIG. 12 is a cutaway side view of a main part of a conventional example of a wafer formed by growing a GaAs layer on a Si substrate.

[Explanation of symbols]

 Reference Signs List 21 Si substrate 22 Ti film 23 Pd film 24 GaAs substrate 24 A Divided GaAs substrate 25 Ti film 26 Pd film 27 Ti · Pd film

Continuation of front page (56) References JP-A-2-237021 (JP, A) JP-A-2-150020 (JP, A) JP-A-63-300511 (JP, A) JP-A-62-213117 (JP) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/02 H01L 27/12

Claims (5)

(57) [Claims] A compound semiconductor substrate divided into a plurality of parts is mounted on a silicon semiconductor substrate at intervals from each other and between a silicon semiconductor substrate and each compound semiconductor substrate with a metal film interposed therebetween bonding therebetween. A wafer for a compound semiconductor device, comprising: 2. A compound semiconductor device wafer wherein a plurality of divided compound semiconductor substrates are separately fitted and mounted in a plurality of recesses formed on a surface of a silicon semiconductor substrate. . 3. The compound semiconductor device wafer according to claim 2, wherein a metal film for bonding the both is interposed between the inside of the recess of the silicon semiconductor substrate and the compound semiconductor substrate. 4. A compound semiconductor on a surface of a silicon semiconductor substrate.
A step of bonding and bonding the back surface of the substrate, and then the compound semiconductor substrate on the silicon semiconductor substrate
Is divided into a plurality of
Compound semiconductor characterized by comprising the steps of:
Manufacturing method of device wafer. 5. A composite formed on a surface of a silicon semiconductor substrate.
The compound semiconductor substrate divided into a plurality of
A step of fitting each of them separately with a metal film interposed therebetween, and then performing a heat treatment to each compound with the silicon semiconductor substrate.
Bonding a compound semiconductor substrate and a compound semiconductor substrate .