JPH05166724A - Silicon substrate compound semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable fine working such as photolithography by improving surface shape (morphology) and to improve yield by improving characteristics of a semiconductor device. CONSTITUTION:After a single or a plurality of first compound semiconductor layers are grown on a silicon substrate 1, the surface of this first compound semiconductor layer 2 is mirror-polished, and further a single or a plurality of second compound semiconductor layers 3, 4, 5... are grown on it, thereby improving surface shape (morphology). Introducing In into a growing compound semiconductor layer relaxes dislocation to improve characteristics or prevents punchthrough of an etching stopper layer due to dislocation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon substrate compound semiconductor device having a compound semiconductor layer such as GaAs formed on a silicon substrate as an active layer or an electron transit layer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A silicon (Si) substrate is light in weight (density), thermal conductivity, price, mechanical strength, and mechanical strength, except that it is inferior in electron mobility as compared with a compound semiconductor substrate such as gallium arsenide (GaAs). The advantage is that it is easy to increase the diameter. Therefore, the substrate is Si and the operating layer is G
A compound semiconductor represented by aAs, for example, Ga
The development of As on Si substrate technology is drawing attention.

There are many problems to be solved in the manufacturing technology of GaAs on Si substrate, and among them, the following 3
Points are regarded as a particularly major issue.

(1) Crystal Defect Density Since GaAs to be the operating layer has a thermal expansion coefficient three times larger than that of Si of the substrate, the growth temperature (600 in the normal growth method).
° C. From the time of cooling to room temperature is often) between 700 ° C., the crystal defects in GaAs is generated by the thermal stress varies depending details growth sequence, the defect density of 10 ⁶ ~10 ⁹ cm ^- It also reaches ² , which adversely affects the characteristics of a semiconductor device manufactured using the same.

(2) Surface shape (morphology) FIG. 7 shows the surface A of the conventional silicon substrate compound semiconductor layer.
It is an FM micrograph.

This figure shows a 3 μm thick GaAs layer (GaAs o) grown on a silicon substrate by a conventional technique.
Atomic force microscope (Atomic)
Force Microscope-Digital
Instrument Nano Nano Scope I
Abbreviated as I AFM. ) Shows the state observed. As you can see in this figure, this GaAs on
The surface of the Si substrate is about 2000 nm in height and width, and the height is 20.
Since there are many irregularities of about nm, it is considered that there is a problem when a fine element is formed on this layer.

(3) Warp of Wafer The above-mentioned GaAs on Si substrate is a Ga serving as an operating layer.
Due to the difference between the thermal expansion coefficient of As and that of Si of the substrate, the concave shape is warped when the temperature is lowered from the growth temperature to room temperature. The warp of the wafer becomes more remarkable as the diameter of the substrate increases, which causes a problem such as a problem in exposure accuracy in the photolithography process.

Conventionally, various techniques have been studied to solve the above-mentioned problems, but the outline thereof can be summarized as follows within the limits related to the present invention.

[Basic Technique] FIGS. 8A to 8F are explanatory views of a conventional process for manufacturing a compound semiconductor layer of a silicon substrate. In this figure, 31 is a tilted silicon substrate, 32 is an amorphous GaAs island, and 33 is amorphous Ga.
As layer, 34 is the first GaAs layer, and 35 is the second GaAs
The layer 36 is a third GaAs layer.

Hereinafter, a basic manufacturing method of a silicon substrate compound semiconductor layer will be described with reference to FIGS.

First Step (Refer to FIGS. 8A and 8B) The silicon tilted substrate 31 is heated to about 1000 ° C. in a hydrogen atmosphere, and SiO ₂ existing on the surface of the silicon tilted substrate is heated.
The layer is reduced and removed. By this step, a step structure having a step of two atomic layers is formed on the surface of the tilted silicon substrate 31.

Second step (see FIGS. 8C and 8D) Next, GaAs is grown on the silicon gradient substrate 31 by MOCVD at a low temperature of about 500 ° C. (low temperature buffer layer). In this step, first, the amorphous GaAs islands 32 grow on the stepped portion on the silicon tilted substrate 31, and then the adjacent GaAs islands 32 are united to cover the surface of the silicon tilted substrate 31. The GaAs layer 33 grows.

Third step (see FIG. 8 (E)) The amorphous GaAs layer 33 of the low temperature buffer layer is crystallized by raising the temperature to a normal growth temperature of about 600 ° C.
The GaAs layer 34 is formed.

Fourth step (see FIG. 8 (F)) A second GaAs layer 35 and a third GaAs layer 36 are grown thereon by a conventionally known growth method.

The above-mentioned series of manufacturing steps is often called a 2-step growth method, and it is the most standard manufacturing method of a silicon substrate compound semiconductor device at present. However, what has been described here is merely a basic manufacturing process, and various other manufacturing processes have been studied.

[Method of Reducing Crystal Defects (Dislocation Density)] As a method of reducing the crystal defects of a GaAs crystal layer grown on a silicon substrate, the following method has been conventionally known. The temperature is raised or lowered during the growth of the GaAs layer, and crystal defects (dislocations) due to the thermal stress generated in the GaAs layer due to the difference in thermal expansion coefficient are forced to escape in the lateral direction of the grown layer. A material layer (eg, InGaAs) having a difference in lattice constant that causes strain in the lateral direction during the growth of the GaAs layer.
Layer) to force dislocations generated in the lateral direction of the growth layer due to dislocations caused by strain due to the difference in lattice constant.

[Improvement of Surface Morphology] A compound semiconductor such as GaAs is formed on a silicon substrate by using a material such as AlAs and AlP having a bond energy with silicon as large as possible for the first low temperature buffer layer. Suppresses island-like island growth. In addition to the above, various methods such as selective growth and annealing performed after the growth of the semiconductor layer are being studied.

[0018]

However, as far as it can be judged from the papers published so far, the data possessed by the inventors, and the commercial products, GaAs having a good surface shape (morphology) is obtained.
It can be said that the manufacture of the on Si substrate is extremely difficult. This is due to the crystal growth mechanism of the basic GaAs on Si substrate described with reference to FIGS. 8A to 8F, and it is extremely difficult to prevent the occurrence of irregularities of about 10 nm to 20 nm. is there.

When the surface is uneven as described above, when a fine pattern is formed by the photolithography technique, the surface cannot be uniformly focused, and the processing accuracy is significantly deteriorated. In particular, it is essential to form a submicron-order fine pattern in order to improve the operating characteristics of electronic devices, and the application of GaAs on Si substrates to these electronic devices is impossible unless the current surface shape is improved. Is.

It is an object of the present invention to provide a silicon substrate compound semiconductor device (GaAs on Si substrate) having excellent characteristics by improving the surface shape (morphology) among the problems mentioned above.

[0021]

In a silicon substrate compound semiconductor device according to the present invention, a silicon substrate and a first or a plurality of first compound semiconductor layers having a mirror-polished uppermost layer surface formed thereon are provided. A second compound semiconductor layer formed on the first compound semiconductor layer, and a second compound semiconductor layer formed on the first compound semiconductor layer.
The surface shape of the compound semiconductor layer can be improved.

In this case, the first layer of the second compound semiconductor layer is an AlGaAs layer, and GaAs / AlGaA is formed on the AlGaAs layer.
By stacking the selective doping structure made of s or GaAs / InGaP, the resistance of the lower layer of the selective doping structure can be increased.

In this case, the AlGaAs layer of the first layer of the second compound semiconductor layer or the Ga layered thereon is formed.
Selectively doped GaAs composed of As / AlGaAs
10 ¹⁹ cm ^{-3 on at} least one of the layers and the AlGaAs layer
By containing In as described above and preventing the film thickness from exceeding the critical film thickness, dislocations in the layer can be relaxed and the surface shape can be improved.

In this case, AlGa having a selectively doped structure of GaAs / AlGaAs and having a gate electrode formed therein.
Leakage current from the gate electrode can be reduced by not containing In at least 2 nm or more on the surface of the As layer.

In this case, a GaAs cap layer including an etching stopper layer composed of one or more AlGaAs layers is laminated on the selectively doped structure, and the etching stopper layer is made to contain In of 10 ¹⁹ cm ⁻³ or more, By preventing the film thickness from exceeding the critical film thickness, it is possible to prevent etching through.

In this case, Ga constituting the selective doping structure
Between As / AlGaAs or GaAs / InGaP, the InAs composition ratio is 0.1 or more at the critical film thickness or less I
A large current high speed device can be formed by inserting the nGaAs layer.

In the method of manufacturing a silicon substrate compound semiconductor device according to the present invention, a step of growing one or a plurality of first compound semiconductor layers on a silicon substrate, and mirror polishing the surface of the first compound semiconductor layer. And a step of further growing a single or plural second compound semiconductor layers on the mirror-polished first compound semiconductor layer. The surface shape can be improved.

In this case, a flat surface can be obtained by making the first compound semiconductor layer have a thickness of 0.5 μm or more after being mirror-polished.

In this case, the flatness of the surface can be improved by forming the second compound semiconductor layer by the metal organic chemical vapor deposition method and setting the atmospheric pressure during the growth to 500 Torr or less.

In this case, by setting the film thickness of the second compound semiconductor layer to 1 μm or less, deterioration of the surface shape can be suppressed.

[0031]

The basic concept of the present invention is extremely simple. In short, after a part of the semiconductor layer of the GaAs on Si substrate is once grown, the surface is mirror-polished and a semiconductor layer for device formation is regrown on the surface. The surface shape of the regrown layer is improved.

However, when the above-mentioned experiment was actually conducted, it was found that the surface shape of the regrown semiconductor crystal layer was significantly different depending on the growth conditions.

FIG. 9 shows the measurement results of the surface roughness of a GaAs layer grown on a silicon substrate by MOCVD to a thickness of 0.6 μm. In this figure, the horizontal axis indicates the growth temperature (° C) and the vertical axis indicates the roughness (Å).

The curve a in this figure shows the result of measuring the surface roughness by AFM when the pressure of the atmosphere during growth is 76 Torr, and the curve b shows the pressure of the atmosphere during growth of 760.
The surface roughness in the case of Torr (atmospheric pressure) is shown. The surface roughness of the semiconductor crystal layer varies greatly depending on the pressure of the atmosphere during growth, and the smaller the pressure of the atmosphere, the smaller the unevenness and the more the surface roughness is improved.

From the experimental results at the intermediate values of the curves a and b, and the intermediate values of the curves a and b, the semiconductor layer for forming a normal semiconductor element was formed by metal organic chemical vapor deposition (MOCVD). When growing, an atmosphere lower than atmospheric pressure (760 Torr), especially 500 To
It has been found that it is preferably rr or less. However, it has been found that when the semiconductor layer is regrown by the molecular beam epitaxial method (MBE), the surface roughness or the surface shape is deteriorated in an ultrahigh vacuum.

FIG. 10 is an AFM micrograph of the surface of the GaAs layer grown by ultra-high vacuum MBE. As is clear from this figure, G grown by ultra-high vacuum MBE
It was found that the surface shape of the aAs layer has a honeycomb structure, and the surface shape is not necessarily determined only by the pressure of the atmosphere during growth.

FIG. 11 is an AFM micrograph of the surface of the GaAs layer on the silicon substrate grown by ultra-high vacuum MBE. According to this figure, it is found that irregularities having a size of about 100 nm are formed in the plane of the crystal layer grown by this method.

FIG. 12 shows a sectional shape taken along line XX 'in FIG. According to this figure, it is found that unevenness having a height of about 50 nm is formed in the cross-sectional shape taken along the line XX ′.

The cause of such irregularities has not yet been completely investigated at present, but the MOC
Considering the difference between VD and MBE and the pressure dependence of the atmosphere during the MOCVD growth, the concentration of As atoms bonded to hydrogen has a strong influence on the arrangement of atoms in the regrown crystal layer (second compound semiconductor layer). It is speculated that it is for giving. It was also found that the surface shape of the second compound semiconductor layer also varies depending on the remaining film thickness after mirror polishing the surface of the GaAs layer which is the first compound semiconductor layer formed on the silicon substrate.

FIG. 13 is an AFM micrograph of the surface of the GaAs layer on the silicon substrate grown by MOCVD.
According to a series of experiments according to this figure, when the remaining film thickness of the GaAs layer which is the first compound semiconductor layer formed on the silicon substrate becomes thinner than about 0.5 μm, the re-grown crystal (second compound semiconductor layer) There was a large dent on the surface of. Therefore, after mirror polishing the first compound semiconductor layer,
It can be said that it is necessary to have a film thickness of 0.5 μm or more.

This is GaA which is the first compound semiconductor layer.
It is considered that, when s is grown, the dislocation density is extremely high in the initial stage of its growth, and when the second compound semiconductor layer is grown thereon, the growth rate is different between the region above this transition and the region other than this transition. Density is also believed to affect surface topography.

Therefore, the film thickness of GaAs, which is the first compound semiconductor layer grown on the silicon substrate, is set to 0.5 μm, and the composition ratio of InAs is set to 0.01 (10 ²⁰ cm 2).
^-3 ) InGaAs is grown and the crystal surface shape is shown in FIG.
A series of experiments were performed to compare with the above.

FIG. 14 is an AFM micrograph of the surface of a silicon substrate InGaAs layer grown on a 0.5 μm GaAs layer. From this figure, it can be seen that the depth of the recess on the surface of the InGaAs layer is significantly reduced. It is considered that this is because In having a large atomic radius easily enters dislocations and vacancies near the dislocations and relaxes the dislocations. By doping In in this way, it is possible to form a GaAs / AlGaAs selective doping structure having good flatness.

As the film thickness of the second compound semiconductor layer becomes thicker, the unevenness on the surface grows, so that the total thickness is 1 μm.
It is desirable to suppress it to a certain degree.

Generalizing the above experimental results, the surface shape of the regrown crystal layer (second compound semiconductor layer) is affected by As species (As-species) reaching the substrate and dislocations in the grown layer. It is considered that the specific method of improving the surface shape of the regrown crystal is as follows.

(1) Reduced pressure MOCV of 500 Torr or less
As species (As-spe) when growing a crystal layer by D
Cies). (2) GaA of mirror-polished GaAs on Si substrate
The remaining film thickness of the s layer (first compound semiconductor layer) is 0.5 μm
Make it as large as possible. (3) Compensating for dislocations generated by introducing In into the compound semiconductor layer. (4) The thickness of the second compound semiconductor layer is made as thin as 1 μm or less.

[0047]

EXAMPLES Examples of the present invention will be described below.

(First Embodiment) FIG. 1 is a schematic structural explanatory view of a silicon substrate semiconductor device of the first embodiment. In this figure, 1 is a Si substrate, 2 is a GaAs buffer layer, and 3 is Al _0.35.
Ga _0.65 As buffer layer, 4 i-GaAs: In electron transit layer, 5 i-Al _0.28 Ga _0.72 As spacer layer, 6
Is n-Al _0.28 Ga _0.72 As electron supply layer, 7 is n-Ga
As cap layer, 8 is a gate electrode, 9 is a source electrode, 1
Reference numeral 0 is a drain electrode.

An outline of a method of manufacturing the semiconductor device having the GaAs on Si type selectively doped structure shown in this figure will be described.

First Step (GaAs on Si Substrate) The Si substrate 1 is heated to 1000 ° C. in a hydrogen atmosphere to remove the oxide film on the surface, and then the substrate temperature is lowered to 500 ° C.
Amorphous GaAs layer 500 by OCVD
Å Grow and raise the substrate temperature to 650 ° C to single-crystallize this amorphous GaAs layer to form a 3 μm thick GaAs layer.
Form the layer buffer 2.

This MOCVD method is well known in this technical field, and is described in, for example, the literature (M. Akiyama, Y. K.
awarada and K.K. Kaminishi: J
apanese Journal of Applie
d Physics 23L843 1984).

Second Step (Mirror Polishing of GaAs on Si) The surface of the single-crystallized GaAs buffer layer 2 is mirror-polished to the same degree as the surface polishing usually performed at the final stage when manufacturing a GaAs substrate for growth. That is, buffing is performed while applying an aqueous solution of sodium hypochlorite to the surface. By this mirror polishing, the surface of the GaAs buffer layer 2 is 0.5 μm.
m, and smoothed by etching, and the remaining thickness is 2.5 μm.

Third Step (Growth of Selectively Doped Structure) On the mirror-polished GaAs buffer layer 2, a reduced pressure MOC is formed.
A plurality of second compound semiconductor layers were grown by VD under the following conditions to form a selectively doped structure. Then n-
A gate electrode 8 is formed on the n-Al _0.28 Ga _0.72 As electron supply layer 6 exposed by etching the gate region of the GaAs cap layer 7, and the n-G is sandwiched by the gate electrode 8.
The source electrode 9 and the drain electrode 10 are formed on the aAs cap layer 7 to complete the HEMT.

The growth conditions are as follows. Growth temperature 630 ° C. Growth pressure 76 Torr Raw material gas GaAs TEGa (Triethylgallum) AsH ₃ AlGaAs TMAl (Trimethylgalluinum) TEGa (Triethylgallumium) AsH ₃ dopant Si ₂ H ₆ TMI (Trimethylindyl)

The flow rate of each raw material gas was set to a growth rate of 3
It was set to be ~ 4Å / sec. The slower the growth rate, the more flattened the surface. Also, TMGa
The surface of TEGa tends to be flatter than that of TEGa.

The main materials and design values of the configuration of FIG. 1 are as follows. 7. n-GaAs cap layer 100 nm thickness Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 6. n-Al _0.28 Ga _0.72 As electron supply layer Thickness 50 nm Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 5. i-Al _0.28 Ga _0.72 As spacer layer 2 nm thick 4. i-GaAs: In electron transit layer 100 nm thickness In concentration 10 ²⁰ cm ^-3 3. Al _0.35 Ga _0.65 As buffer layer Thickness 300 nm 2. GaAs buffer layer thickness 2.5 μm 1. Si substrate

In this structure, the thickness of the GaAs buffer layer 2 formed on the Si substrate 1 is 2. after mirror polishing.
5 μm, which is a thickness at which large unevenness occurs 0.5
Since it is thicker than μm, A grown on it
The flatness of the surface of the _0.35 Ga _0.65 As buffer layer 3 was good.

The n-Al _0.28 Ga _0.72 As electron supply layer 6, the i-Al _0.28 Ga _0.72 spacer layer 5 and the i-GaA
A selective doping structure is formed by the s: In electron transit layer 5. The i-GaAs: In electron transit layer is
Dislocations are relaxed by In introduced at a concentration of 10 ²⁰ cm ⁻³ or more in this layer.
It has been confirmed that the introduction of In at a concentration of about ¹⁹ cm ⁻³ causes a dislocation relaxation effect.

It has also been confirmed that the n-Al _0.28 Ga _0.72 As electron supply layer 6, the i-Al _0.28 Ga _0.72 spacer layer 5 and the like also have a dislocation relaxation effect due to the introduction of In described above. When introducing In into the n-Al _0.28 Ga _0.72 As electron supply layer 6, it is desirable that the leakage current of the gate electrode be suppressed by preventing In from being contained in at least 2 nm on the upper surface thereof.

The uppermost G of the first compound semiconductor layer
The surface of the aAs buffer layer 2 is contaminated by mirror polishing, and if the second compound semiconductor layer is grown as it is,
Since a conductive layer may be formed on the regrowth interface, AlGa that easily increases the resistance of the first layer of the second compound semiconductor layer.
It is desirable to insert the As layer so as to cancel this conductive layer.

In introduced GaAs layer or AlG
In the process of laminating a plurality of aAs layers, dislocations can be prevented by inserting a GaAs layer or an AlGaAs layer which has the same lattice constant and does not contain In as appropriate.

The selective doping structure composed of the n-Al _0.28 Ga _0.72 As electron supply layer 6 and the i-Al _0.28 Ga _0.72 spacer layer 5 has an n-InGaP electron supply layer and an i-GaAs spacer layer. It can also be configured with.

FIG. 2 is an AFM micrograph of the surface of the silicon substrate compound semiconductor layer of the first embodiment. According to this figure, the size of the unevenness on the surface of the semiconductor layer is about 2 to 3 nm, which is greatly improved compared to the case where the surface of the GaAs layer is not polished to be about 20 nm. ..

In this embodiment, the total thickness of the regrown layer is 55.
However, according to other experimental results, the size of the irregularities on the surface of the semiconductor layer increases as the growth film thickness increases, so that the thickness is as thin as possible within the range in which the characteristics of the two-dimensional electron gas are not deteriorated. When manufacturing a normal HEMT, the thickness needs to be 1 μm or less.

The semiconductor device of this example was subjected to hole measurement, and the mobility and sheet electron density were measured. The results shown in the following table were obtained. For comparison with the measurement result, the measurement result when the GaAs layer having the same structure is grown on the GaAs substrate without using the Si substrate is also shown.

Room temperature 77K Mobility on Si 5280 21400 (cm ² / Vs) on GaAs 5690 30300 Sheet electron concentration on Si 9.6 × 10 ¹¹ 8.0 × 10 ¹¹ (cm ⁻² ) on GaAs 9.4 × 10 ¹¹ 8.2 × 10 ¹¹

The carrier mobility of GaAs on Si according to this example is GaAs on Ga at room temperature.
At 93% of the carrier mobility of As, the sheet electron concentrations were almost the same, and there was no problem as far as room temperature operation was considered.

When the GaAs on Si substrate of this embodiment is applied to MESFET, the above GaAs: In is used.
The electron transit layer 4 may be Si-doped GaAs: In, and no semiconductor layer above the i-AlGaAs spacer layer 5 is formed.

The present invention is also applicable to other material systems such as Ga.
As and InGaP or InAlAs and InGa
It is also possible to apply to the structure which combined As. Further, it goes without saying that this embodiment can be similarly applied to the HEMT having an inverted structure in which the n-AlGaAs electron supply layer is arranged below and the carrier transit layer is arranged thereon.

In addition, GaAs which constitutes the selective doping structure
/ AlGaAs or GaAs / InGaP with a critical film thickness or less and an InAs composition ratio of 0.1 or more
By inserting the aAs layer, it is possible to form a HEMT capable of large current and high speed operation. The reason is that when In is added to the InGaAs layer near the electron transit layer, a large amount of electrons are likely to stay in that portion, the electron concentration is increased, and the transit speed of electrons in this InGaAs layer is high. is there.

(Second Embodiment) FIGS. 3, 4, 5 and 6
[FIG. 6] is a step explanatory view of the method for manufacturing the silicon substrate compound semiconductor device of the second example. In this figure, 11 is Si
Substrate, 12 GaAs first buffer layer, 13 Al _0.35
Ga _0.65 As: In second buffer layer, 14 is Al _0.28 G
a _0.72 As third buffer layer, 15 is i-GaAs: In
Electron transit layer 16, 16 i-Al _0.28 Ga _0.72 As: In spacer layer, 17 n-Al _0.28 Ga _0.72 As electron supply layer, 18 n-GaAs first cap layer, 19 n-A
l _0.28 Ga _0.72 As: In etching stopper layer, 20
Is an n-GaAs second cap layer, 21 and 22 are resist layers, 23 is an E mode gate electrode, and 24 is a D mode gate electrode.

This embodiment is an example in which the present invention is applied to a semiconductor integrated circuit device. The growth conditions in this example are:
Although it is similar to the first embodiment, the manufacturing process thereof will be described below.

First Step (See FIG. 3) On the Si substrate 11, the GaAs first buffer layer 12, A
l _0.35 Ga _0.65 As: In second buffer layer 13, Al
_0.28 Ga _0.72 As Third buffer layer 14, i-GaAs:
In electron transit layer 15, i-Al _0.28 Ga _0.72 As: In
Spacer layer 16, n-Al _0.28 Ga _0.72 As electron supply layer 17, n-GaAs first cap layer 18, n-Al _0.28
Ga _0.72 As: In etching stopper layer 19, n-G
The aAs second cap layer 20 is formed.

Second step (see FIG. 4) A resist layer 21 is formed on the n-GaAs second cap layer 20.
Then, an opening is formed in the E-mode gate region, and dry etching is performed in the CCl ₂ F ₂ + He gas through the opening to remove the n-GaAs second cap layer 20 in the E-mode gate region. This etching is n-A below
l _0.28 Ga _0.72 As: In Stop at the surface of the etching stopper layer 19. After that, NH ₃ OH: HO ₂ = 1: 5
N-Al _0.28 Ga _0.72 in the E-mode gate region by wet etching for about 1 minute using an ammonia diluting solution of 0
The As: In etching stopper layer 19 is removed.

Third Step (see FIG. 5) The resist layer 21 is removed, a new resist layer 22 is formed, and openings are formed in the E mode gate region and the D mode gate region. Through these openings, as in the second step, C
The n-GaAs first cap layer 18 and D in the E mode gate region after dry etching in Cl ₂ F ₂ + He gas
The n-GaAs second cap layer 20 in the mode gate region is removed. This etching is stopped at the surface of the n-Al _0.28 Ga _0.72 As electron supply layer 17 in the E-mode gate region and the n-Al _0.28 Ga _0.72 As: In etching stopper layer 19 in the D-mode gate region thereunder.

Fourth Step (see FIG. 6) After that, wet etching is performed using NH ₃ OH: HO ₂ = 1: 50 to form n-Al _{0.28 in the} E mode gate region.
A part of the Ga _0.72 As electron supply layer 17 and the n-Al _0.28 Ga _0.72 As: In etching stopper layer 19 in the D mode gate region are removed. Al is vapor-deposited through the openings of the resist layer 22 to form an E-mode gate electrode 23 and a D-mode gate electrode 24. After removing the resist layer 22, a source electrode and a drain electrode are respectively formed on the n-GaAs second cap layer 20 with the E-mode gate electrode 23 and the D-mode gate electrode 24 formed previously interposed therebetween to complete the process. ..

The main materials and design values of the structure of FIG. 6 are as follows. 20. n-GaAs second cap layer 60 nm thick Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 19. n-Al _0.28 Ga _0.72 As: In etching stopper layer 3 nm thick Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 18. n-GaAs first cap layer 7 nm thick Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 17. n-Al _0.28 Ga _0.72 As electron supply layer Thickness 35 nm Donor concentration 1.5 × 10 ¹⁸ cm ⁻³ 16. i-Al _0.28 Ga _0.72 As: In spacer layer 2 nm thick 15. i-GaAs: In electron transit layer thickness 100 nm In concentration 10 ²⁰ cm ^-3 14. Al _0.28 Ga _0.72 As Third buffer layer 100 nm thick 13. Al _0.35 Ga _0.65 As: In second buffer layer thickness 200 nm 12. GaAs first buffer layer thickness 2.5 μm 11. Si substrate

The difference between this embodiment and the first embodiment is that E
The point is that mode HEMTs and D-mode HEMTs are integrated. Therefore, the number of semiconductor layers into which In is introduced increases,
That is, the AlGaAs layer containing In was introduced as an etching stopper layer on the upper part of the selectively doped structure.
By increasing the position of the In-doped layer,
There is an effect that the surface morphology is further improved.

Multi-layer grown AlGa as in this example
In the etching stopper layers such as the As layer and the GaAs layer, dislocation density often remains considerably, and since etching easily progresses at this dislocation point, there is a possibility of punch-through. If In is introduced into the etching stopper layer in such a case, In easily enters the dislocation point and In is not etched, so that penetration of etching can be prevented.

[0080]

As described above, according to the present invention,
The surface shape (morphology) of the compound semiconductor crystal for device formation grown on the silicon substrate is remarkably improved, making it possible to form a fine electrode structure and eliminating defects in the photolithography process and improving the electrical characteristics. A silicon substrate compound semiconductor device having high reliability can be obtained, which largely contributes to cost reduction of an element capable of operating at high speed.

[Brief description of drawings]

FIG. 1 is a schematic configuration explanatory view of a silicon substrate compound semiconductor device of a first embodiment.

FIG. 2 is an AFM micrograph of the surface of the silicon substrate compound semiconductor layer of the first example.

FIG. 3 is a process explanatory view (1) of the method for manufacturing the silicon substrate compound semiconductor device according to the second embodiment.

FIG. 4 is a process explanatory view (2) of the method for manufacturing the silicon substrate compound semiconductor device according to the second embodiment.

FIG. 5 is a process explanatory view (3) of the method for manufacturing the silicon substrate compound semiconductor device according to the second embodiment.

FIG. 6 is a process explanatory view (4) of the method for manufacturing the silicon substrate compound semiconductor device according to the second embodiment.

FIG. 7: A of the surface of a conventional silicon substrate compound semiconductor layer
It is an FM micrograph.

FIGS. 8A to 8F are explanatory views of a conventional manufacturing process of a silicon substrate compound semiconductor layer.

FIG. 9: 0.6 μm on a silicon substrate by MOCVD
It is the measurement result of the surface roughness of the grown GaAs layer.

FIG. 10 is an AFM micrograph of the surface of a GaAs layer on a silicon substrate grown by ultra-high vacuum MBE.

FIG. 11 is an AFM micrograph of the surface of a GaAs layer on a silicon substrate grown by ultra-high vacuum MBE.

FIG. 12 shows a cross-sectional shape taken along the line XX ′ in FIG.

FIG. 13: Silicon substrate Ga grown by MOCVD
It is an AFM micrograph of the surface shape of an As layer.

FIG. 14 is an AFM micrograph of the surface of a silicon substrate InGaAs layer grown on a 0.5 μm GaAs layer.

[Explanation of symbols]

1 Si substrate 2 GaAs buffer layer 3 Al _0.35 Ga _0.65 As buffer layer 4 i-GaAs: In electron transit layer 5 i-Al _0.28 Ga _0.72 As spacer layer 6 n-Al _0.28 Ga _0.72 As electron supply layer 7 n-GaAs cap Layer 8 Gate electrode 9 Source electrode 10 Drain electrode

Claims (10)

[Claims] 1. A silicon substrate, a single or a plurality of first compound semiconductor layers having a mirror-polished top surface formed thereon, and a single or a plurality of compound semiconductor layers formed on the first compound semiconductor layer. A silicon substrate compound semiconductor device comprising a plurality of second compound semiconductor layers. 2. The first layer of the second compound semiconductor layer is AlG
2. The silicon substrate compound semiconductor device according to claim 1, wherein the silicon substrate compound semiconductor device is an aAs layer, and a selective doping structure made of GaAs / AlGaAs or GaAs / InGaP is laminated thereon. 3. AlG of the first layer of the second compound semiconductor layer
aAs layer or GaAs / A laminated on it
Selectively doped GaAs layer composed of 1 GaAs and Al
I of 10 ¹⁹ cm ^-3 or more in any one or more of the GaAs layers
3. The silicon substrate compound semiconductor device according to claim 2, wherein n is included and the film thickness does not exceed the critical film thickness. 4. The silicon substrate compound semiconductor according to claim 3, wherein In is not contained in at least 2 nm or more of the surface of the AlGaAs layer in which the gate electrode is formed, of the selectively doped structure of GaAs / AlGaAs. apparatus. 5. A GaAs cap layer including an etching stopper layer made of one or more AlGaAs layers is laminated on the selectively doped structure, and the etching stopper layer contains 10 ¹⁹ cm ⁻³ or more of In, and its film is formed. 5. The silicon substrate compound semiconductor device according to claim 2, wherein the thickness does not exceed the critical film thickness. 6. GaAs / A constituting a selectively doped structure
InGaA having a InGaAs composition ratio of 0.1 or more with a critical film thickness or less between 1 GaAs or GaAs / InGaP
The silicon substrate compound semiconductor device according to claim 2, wherein an s layer is inserted. 7. A step of growing one or a plurality of first compound semiconductor layers on a silicon substrate, a step of mirror-polishing a surface of the first compound semiconductor layer, and the mirror-polished first compound. A method of manufacturing a silicon substrate compound semiconductor device, further comprising the step of growing a single or a plurality of second compound semiconductor layers on the semiconductor layer. 8. The method for manufacturing a silicon substrate compound semiconductor device according to claim 7, wherein the first compound semiconductor layer has a thickness of 0.5 μm or more after being mirror-polished. 9. The second compound semiconductor layer is formed by metalorganic vapor phase epitaxy, and the atmospheric pressure during growth is 500.
9. The method for manufacturing a silicon substrate compound semiconductor device according to claim 7 or 8, characterized in that it is less than Torr. 10. The film thickness of the second compound semiconductor layer is 1 μm.
10. The method for manufacturing a silicon substrate compound semiconductor device according to claim 7, wherein: