JP3670130B2 - Method for manufacturing group III-V compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, a plurality of semiconductor elements (high electron mobility transistors, pin diodes, Schottky diodes, resonant tunneling diodes, etc.) are stacked on a semiconductor substrate, and a semiconductor element separation layer (between these semiconductor elements) The present invention relates to a method for manufacturing a group III-V compound semiconductor device using a separator layer.
[0002]
[Prior art]
Generally, a III-V compound semiconductor device is formed on a III-V compound semiconductor substrate. Recently, for high-speed operation, a structure has been proposed in which InP is used for the semiconductor substrate and a plurality of semiconductor elements made of InAlAs, InGaAs, InP, etc. are stacked on the same semiconductor substrate. For example, a structure in which a pin diode is stacked on a high electron mobility transistor, a structure in which a Schottky diode is stacked on a high electron mobility transistor, and a structure in which a resonant tunnel diode is stacked on a high electron mobility transistor are proposed. . An n-InGaAs contact layer doped with Si at a concentration of 1 × 10 ¹⁹ / cm ³ or more is formed on the top layer of the high electron mobility transistor structure in order to form source and drain electrodes without heat treatment. In general. Conventionally, n-InP doped with Si at a concentration of 1 × 10 ¹⁹ / cm ³ or more is used as a separator layer so as to have selectivity during etching and electrical connection between the upper and lower semiconductor devices. After the growth, the next semiconductor element is grown. In general, pin diodes, Schottky diodes, and resonant tunneling diodes are formed of a III-V group compound semiconductor layered structure in which the V group is As. For example, when a sulfuric acid-based etchant or a citric acid-based etchant is used, the etching rate of the n-InP layer is about 1/200 (selection ratio is 200) compared to the etching rate of the As-based material. . Therefore, only the semiconductor element formed of the As-based material can be removed by etching, and the etching can be stopped with n-InP. Further, when a hydrochloric acid-based etchant is used, n-InGaAs has a characteristic that is hardly etched, so that the n-InP layer can be selectively removed and the etching can be stopped at the n-InGaAs layer. When processing a semiconductor element, it is common to use the selective etching characteristics as described above.
[0003]
Usually, metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) is used for crystal growth of compound semiconductors, but MOVPE is used when crystal material containing P is required to grow. There are many common cases. In the case of the MOVPE method, group III source gases include trimethylindium (TMI), triethylindium (TEI), trimethylaluminum (TMA), triethylaluminum (TEA), trimethylgallium (TMG), and triethylgallium (TEG). Metal is used. On the other hand, as the group V source gas, an organic metal such as tertiary butyl arsine (TBA) or tertiary butyl phosphine (TBP) may be used in addition to a hydride of arsine (AsH ₃ ) and phosphine (PH ₃ ).
[0004]
[Problems to be solved by the invention]
However, when the above-described structure in which a plurality of semiconductor elements are stacked is grown using this MOVPE method, the growth temperature is 600 ° C. or higher in the MOVPE method, and therefore n-InP is grown on n-InGaAs. At this time, As re-evaporates from the InGaAs layer attached to the reaction furnace, As is mixed into the n-InP layer. That is, since As is mixed in the n-InP layer grown as the separator layer, there is a problem of “etching omission” that etching does not stop at this layer even when a sulfuric acid-based or citric acid-based etchant is used. In addition, etching loss of the n-InP layer due to As mixing usually occurs in a pinhole shape. That is, although the upper semiconductor device is selectively removed from the n-InP separator layer, the semiconductor device below the separator layer is actually partially etched. In order to suppress the mixing of As into the n-InP separator layer, a method of lowering the growth temperature has been devised, but in order to grow a high-purity crystal at a practical level using the MOVPE method, it is 600 ° C. The above growth temperature is required, and the above problems have not been solved.
[0005]
The high electron mobility transistor is a semiconductor element characterized in that a current flows in the lateral direction with respect to the semiconductor substrate, and a current flowing between the source and the drain is controlled by a voltage applied to the gate. In other words, when etching omission occurs in the form of pinholes through the separator layer as described above, the electrical characteristics of the grown crystal are significantly different from the desired characteristics in the vicinity of these pinholes. For example, when etching omission occurs in the gate, source, and drain portions, the resistance value increases. That is, there are problems that desired transistor characteristics cannot be obtained, variation within the wafer occurs, and the yield in manufacturing the semiconductor element is significantly reduced.
[0006]
The present invention has been made to solve the above-described problems, and improves the selective etching characteristics during etching of a separator layer inserted between a plurality of semiconductor elements stacked on a semiconductor substrate and prevents etching omission. An object of the present invention is to provide a method for manufacturing a group III-V compound semiconductor device with a high yield.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a plurality of semiconductor elements made of a III-V group compound semiconductor are stacked on a semiconductor substrate via a separator layer, and the separator layer is a III-V group compound. the method of manufacturing a group III-V compound semiconductor device including a P only as it and a group V element from the semiconductor, forming a contact layer containing as only as a group V element to the top of the semiconductor device in the lower layer, III group After growing an As evaporation suppression layer made of a III-V group compound semiconductor containing at least Al as an element and only As as a group V element, the separator layer is stacked.
[0008]
InP is used as the semiconductor substrate, InP is used as the separator layer, and InAlAs is used as the As evaporation suppression layer.
InP is used as the semiconductor substrate, InP is used as the separator layer, and AlAs is used as the As evaporation suppression layer.
The thickness of the InAlAs layer that is the As evaporation suppression layer is set to 1 to 10 nm.
Further, the thickness of the AlAs layer which is the As evaporation suppression layer is set to 0.3 to 10 nm.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
As described above, the decrease in the InP selection ratio during wet etching is caused by the incorporation of As during InP growth. That is, when the lower layer of the InP layer as the separator layer is an InGaAs layer, InGaAs adheres to the inner wall of the reactor in the step before the separator layer formation, and As is re-evaporated from the deposited InGaAs. . This is because the MOVPE method requires high temperature growth of 600 ° C. or higher. In order to suppress the mixing of As into the InP layer, it is considered effective to lower the growth temperature. However, as described above, high temperature growth is indispensable for epitaxial growth of high-purity crystals in the MOVPE method, and thus the growth temperature cannot be lowered. On the other hand, it is known that the evaporation of the group V element from the group III-V compound semiconductor depends on the bonding force between the group III atom and the group V atom. Further, the bonding strength increases in the order of InAs, GaAs, and AlAs. Therefore, when InAlAs or AlAs is grown instead of InGaAs, it is possible to reduce As desorption from the surface. This is the same for both the substrate surface and the reactor inner wall.
[0010]
Usually, the thickness of one semiconductor device is about 200 nm. In addition, etching of this semiconductor device is usually performed by etching twice as thick as the film thickness. In order to stop etching at the n-InP separator layer after removing the semiconductor device by etching, when the etching selectivity of the separator layer is 200, the thickness of the n-InP separator layer is designed to be at least 1 nm. There is a need to. However, in practice, the n-InP thickness is generally designed to be 10 to 50 nm with a margin. The thicknesses of n-InAlAs and n-AlAs grown under the n-InP layer are 3 molecular layers (about 1 nm) and 1 molecular layer (about 0.3 nm) or more, respectively. The effect of suppressing evaporation became remarkable. When n-InAlAs is used for the evaporation suppression layer of As grown under the n-InP layer, the lattice constant is matched to InP, and thus the thickness is not limited. However, when n-AlAs is used for the As evaporation suppression layer, since the lattice constant of AlAs is different from InP, misfit dislocation occurs at a thickness greater than the critical thickness. Therefore, when n - AlAs is used, it is necessary to form the As evaporation suppression layer with a film thickness equal to or less than the critical film thickness (10 nm). Further, the etch rate of n-InP of an etchant (for example, hydrochloric acid: phosphoric acid: acetic acid: water = 1: 1: 2.5: 1) used for removal of n-InP is about 60 nm / min, but InAlAs, The etching rate of AlAs is as slow as about 2 nm / min. Therefore, when removing the separator layer and the As evaporation suppression layer simultaneously by etching, it is desirable that the thickness of the As evaporation suppression layer of InAlAs or AlAs is designed to about 10 nm from a practical viewpoint.
[0011]
Whereas the prior art attempts to suppress the incorporation of As by lowering the growth temperature, the present invention forms an As-layer by forming a stacked structure of n-InP / n-InAlAs and n-InP / n-AlAs. This is different in that the contamination of the separator layer is suppressed and the selectivity of the separator layer during etching is improved.
[0012]
The present invention relates to a method of manufacturing a group III-V compound semiconductor device, wherein two or more types of semiconductor elements are stacked and grown on a semiconductor substrate, and a separator layer inserted between these semiconductor devices is subjected to wet etching. The present invention relates to a layer structure manufacturing method for improving selective etching characteristics. In other words, the present invention can stabilize the wet etching technique when processing a structure in which a high electron mobility transistor expected to operate at high speed and a semiconductor element such as a pin diode, a Schottky diode, and a resonant tunnel diode are stacked. In addition, the manufacturing yield of the semiconductor element can be improved.
[0013]
FIG. 1 is a diagram showing a first embodiment of a method for manufacturing a III-V compound semiconductor device according to the present invention. That is, after forming a high electron mobility transistor composed of InAlAs crystals and InGaAs crystals on an InP substrate, an As evaporation suppression layer and a separator layer made of InP are formed, and an InAlAs Schottky diode structure is formed thereon. The layer structure is shown. In the figure, 101 is an InP substrate, 102 is an InAlAs buffer layer, 103 is an InGaAs channel layer, 104 is an InAlAs spacer layer, 105 is a carrier supply layer doped with Si in InAlAs, 106 is a barrier layer of InAlAs, and 107 is Si. This is a doped n-InGaAs contact layer, in which a high electron mobility transistor is formed in the layers 102 to 107, and the contact layer 107 contains only As as a group V. Reference numeral 108 denotes a Si-doped n-InAlAs As evaporation suppression layer which is laminated before the separator layer is laminated, and contains at least Al as a group III element and only As as a group V element. Reference numeral 109 denotes an n-InP etch stopper layer doped with Si as a separator layer, which contains only P as a group V element. Further, 110 is an n-InAlAs layer doped with Si, 111 is an InAlAs layer, and a Schottky diode structure is formed in the layers 110 to 111.
[0014]
FIG. 2 shows that the n-InP layer thickness of the etch stopper layer 109 is constant at 30 nm, and the etching loss density of pinholes generated on the n-InP surface when the Schottky diode is etched using a citric acid-based etchant. The result of having measured using a microscope is shown. At this time, in FIG. 1, the layer thickness of n-InAlAs of the As evaporation suppression layer 108 is changed. From the figure, it can be seen that the growth density of etching is drastically reduced by the growth of n-InAlAs. Further, it was confirmed that the growth density of n-InAlAs of 1 nm or more reduced the pinhole-shaped etching drop density to 3000 / cm ^{2, which} was reduced to a level having no practical problem.
[0015]
FIG. 3 is a diagram showing a second embodiment of a method for manufacturing a III-V compound semiconductor device according to the present invention. That is, when a high electron mobility transistor composed of InAlAs crystal and InGaAs crystal is grown on an InP substrate, an As evaporation suppression layer and a separate layer composed of InP are formed, and a resonant tunnel diode structure is formed thereon The layer structure of is shown. In the figure, 301 is an InP substrate, 302 is an InAlAs buffer layer, 303 is an InGaAs channel layer, 304 is an InAlAs spacer layer, 305 is a carrier supply layer doped with Si in InAlAs, 306 is an InAlAs barrier layer, and 307 is Si. This is a doped n-InGaAs contact layer, in which a high electron mobility transistor is formed in the layers 302 to 307, and the contact layer 307 contains only As as a group V. Reference numeral 308 denotes an As evaporation suppression layer of n-AlAs doped with Si, which contains Al as a group III element and only As as a group V element. Reference numeral 309 denotes an n-InP etch stopper layer doped with Si as a separator layer, which contains only P as a group V element. Further, 310 is an n-InGaAs layer doped with Si, 311 is an InGaAs spacer layer, 312 is an InAlAs barrier layer, 313 is an InGaAs well layer, 314 is an InAlAs barrier layer, 315 is an InGaAs spacer layer, and 316 is an InGaAs spacer layer. An n-InGaAs layer doped with Si, and a resonant tunnel diode structure is formed in the above-described layers 310 to 316.
[0016]
FIG. 4 shows that the n-InP layer thickness of the etch stopper layer 309 is constant at 30 nm, and using a citric acid-based etchant, the pinhole-like etching omission density generated on the surface when the resonant tunnel diode is etched in the same manner as described above. The result measured using is shown. At this time, the layer thickness of n-AlAs of the As evaporation suppression layer 308 was changed. From the figure, it can be seen that in the case of growth of n-AlAs, the etching drop density is further drastically reduced from the result of n-InAlAs shown in FIG. This indicates that the increase in the composition of AlAs suppresses the evaporation of As. In the case of n-AlAs, it was confirmed that the pinhole-shaped etching drop density was reduced to a level that had no practical problem even in the growth of one molecular layer.
[0017]
In the above embodiment, the case where the thicknesses of the n-InP etch stopper layers 109 and 309 are constant at 30 nm is shown, but similar results were obtained even at a film thickness of 10 to 50 nm. Similar results were confirmed even in a layer structure in which a pin diode was formed on the top. Moreover, although the case where n-InAlAs and n-AlAs are used for the As evaporation suppression layers 108 and 308 is shown, the same effect is expected with InAlGaAs. In addition, n-GaP or n-AlP can be used for the P-based compound semiconductor instead of n-InP. Furthermore, in order to stabilize the recess etching of the gate of the high electron mobility transistor, even when an etch stop layer composed of a P-based III-V compound semiconductor layer is formed on the barrier layer, the growth of the P-based compound semiconductor is also improved. Immediately before, it has been confirmed that the performance of the P-type compound semiconductor etch stopper layer is improved by growing several layers of compound semiconductor containing AlAs.
[0018]
【The invention's effect】
As described above, in the method for manufacturing a group III-V compound semiconductor device according to the present invention, when a plurality of semiconductor elements are stacked and grown on a semiconductor substrate, a separator layer inserted between these semiconductor elements is formed. The selective etching characteristics at the time of wet etching can be improved. This means that the wet etching technology can be stabilized when processing a structure in which a high-electron mobility transistor, which is expected to operate at high speed, and a semiconductor element such as a pin diode, a Schottky diode, or a resonant tunnel diode is processed. It is possible to obtain desired device characteristics with high reproducibility in the manufacture of elements. That is, it means that a device as designed can be manufactured with a high yield, and has a great effect of promoting the practical application and application of various semiconductor devices.
[0019]
More specifically, the above effect can be realized by using InP as the semiconductor substrate, InP as the separator layer, and InAlAs as the As evaporation suppression layer.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a method for manufacturing a III-V compound semiconductor device according to the present invention.
FIG. 2 is a diagram showing the relationship between the density of etching omission generated by wet etching and the thickness of an As evaporation suppression layer in FIG. 1;
FIG. 3 is a diagram showing a second embodiment of a method for manufacturing a group III-V compound semiconductor device according to the present invention.
4 is a diagram showing the relationship between the density of etching omission generated by wet etching and the thickness of an As evaporation suppression layer in FIG. 3; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... InP substrate 102 ... InAlAs buffer layer 103 ... InGaAs channel layer 104 ... InAlAs spacer layer 105 ... InAlAs doped Si supply layer 106 ... InAlAs barrier layer 107 ... Si doped n-InGaAs contact layer 108 ... N-InAlAs As evaporation suppression layer 109 doped with Si ... n-InP etch stopper layer 110 doped with Si ... n-InAlAs layer 111 doped with Si ... InAlAs layer 301 ... InP substrate 302 ... InAlAs buffer layer 303 ... InGaAs channel layer 304 ... InAlAs spacer layer 305 ... InAlAs doped carrier supply layer 306 ... InAlAs barrier layer 307 ... Si doped n InGaAs contact layer 308... Si doped n-AlAs As evaporation suppression layer 309... Si doped n-InP etch stopper layer 310... Si doped n-InGaAs layer 311... InGaAs spacer layer 312. Barrier layer 313 ... InGaAs well layer 314 ... InAlAs barrier layer 315 ... InGaAs spacer layer 316 ... Si-doped n-InGaAs layer

Claims (5)

A plurality of semiconductor elements made of a group III-V compound semiconductor are stacked on a semiconductor substrate via a separator layer, and the separator layer is made of a group III-V compound semiconductor and contains only P as a group V element III- the method of manufacturing a V compound semiconductor device, a contact layer containing as only as a group V element to the top of the semiconductor device in the lower layer, including a least includes V group element Al as the group III element as only A method for producing a group III-V compound semiconductor device, comprising: growing an As evaporation suppression layer made of a group III-V compound semiconductor; and laminating the separator layer.   The method for manufacturing a III-V compound semiconductor device according to claim 1, wherein InP is used as the semiconductor substrate, InP is used as the separator layer, and InAlAs is used as the As evaporation suppression layer.   2. The method for manufacturing a III-V compound semiconductor device according to claim 1, wherein InP is used as the semiconductor substrate, InP is used as the separator layer, and AlAs is used as the As evaporation suppression layer.   3. The method of manufacturing a group III-V compound semiconductor device according to claim 2, wherein the InAlAs layer serving as the As evaporation suppression layer has a thickness of 1 to 10 nm. Method.   The III-V group compound semiconductor device according to claim 3, wherein the AlAs layer as the As evaporation suppression layer has a thickness of 0.3 to 10 nm. Manufacturing method.

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