TWI755746B - Semiconductor substrate and method of forming the same - Google Patents

Abstract

A semiconductor substrate includes a low-resistance substrate, a high-resistance substrate, and an epitaxial layer. The low-resistance substrate has a first resistance value between 0.0001 to 1 Ohm-cm. The high-resistance substrate is disposed on the low-resistance substrate, and the high-resistance substrate is in direct contact with the low-resistance substrate. The high-resistance substrate has a second resistance value between 1 to 10000 Ohm-cm. The epitaxial layer is disposed on the high-resistance substrate.

Description

Semiconductor substrate and method of forming the same

The present disclosure relates to a semiconductor substrate and a method of forming the semiconductor substrate.

With the advancement of the semiconductor integrated circuit (IC) industry, manufacturers need to optimize and improve the process to produce products with smaller size and better performance. In the semiconductor manufacturing process, the performance of the substrate will affect the subsequent manufacturing process and the quality of IC products. For example, Silicon on Insulator (SOI) substrate has the advantages of reducing leakage current, increasing saturation current and low power consumption, and has been widely studied and applied.

In the process technology of using a silicon substrate to grow an epitaxial layer to form a semiconductor substrate, the stress may be concentrated on the silicon substrate due to the lattice defects of the epitaxial layer. When the stress is released, the epitaxial layer will be dislocated. As a result, the silicon substrate is deformed or twisted, or even broken. In addition, the lattice constants of the epitaxial layer and the silicon substrate are greatly different, and the thermal expansion coefficients of the epitaxial layer and the silicon substrate are also greatly different, so the semiconductor substrate is easily warped and the quality of the epitaxial layer is poor.

In view of the above, there is an urgent need for a semiconductor substrate and a method for forming the semiconductor substrate that can solve the above problems.

The present disclosure provides a semiconductor substrate, including a low-resistance substrate, a high-resistance substrate, and an epitaxial layer. The low-resistance substrate has a first resistance value ranging from 0.0001 to 1 Ohm-cm; the high-resistance substrate is disposed on the low-resistance substrate and directly contacts the low-resistance substrate, and the high-resistance substrate has a resistance of 1-10000 Ohm. The second resistance value of -cm; the epitaxial layer is arranged on the high resistance value substrate.

In some embodiments, the low-resistance substrate is a super-heavy doped wafer.

In some embodiments, the material of the low resistance substrate includes boron, phosphorous, arsenic, antimony, or a combination thereof.

In some embodiments, the epitaxial layer includes gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium gallium phosphide, indium gallium antimonide, or combinations thereof.

m的厚度。 In some embodiments, the high-resistance substrate has between 10 nm and 10

m thickness.

The present disclosure provides a method of forming a semiconductor substrate including the following steps. A composite substrate is received. The composite substrate includes a low-resistance substrate and a high-resistance substrate. The high-resistance substrate is disposed on the low-resistance substrate. The low-resistance substrate has a first resistance value ranging from 0.0001 to 1 Ohm-cm. The resistance value substrate has a second resistance value ranging from 1 to 10000 Ohm-cm. An epitaxial layer is formed on the high-resistance substrate.

In some embodiments, receiving the composite substrate includes the following operations. Bonding the low-resistance substrate with the high-resistance substrate, and thinning the high-resistance substrate.

m的厚度。 In some embodiments, the high-resistance substrate has between 10 nm and 10

m thickness.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further description of the invention as claimed.

For a more detailed and complete description of the present disclosure, reference may be made to the accompanying drawings and the various embodiments described below, wherein the same numerals in the drawings represent the same or similar elements.

Several embodiments of the present invention will be disclosed in the drawings below, and for the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the invention, these practical details are unnecessary. In addition, for the purpose of simplifying the drawings, some well-known structures and elements will be shown in a simple and schematic manner in the drawings.

Although a series of operations or steps are used below to describe the methods disclosed herein, the order in which these operations or steps are shown should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Furthermore, not all illustrated operations, steps and/or features must be performed in order to practice embodiments of the present invention. Furthermore, each operation or step described herein may contain several sub-steps or actions.

In the semiconductor manufacturing process, the semiconductor substrate can be formed by direct bonding of a handle wafer and a device wafer, and then the device wafer is processed to form a device layer. An epitaxial layer is formed thereon.

The present disclosure provides a method of forming a semiconductor substrate, please refer to FIG. 1 to FIG. 4 . FIG. 1 illustrates a method 100 of forming a semiconductor substrate according to some embodiments of the present disclosure. Method 100 includes operation 110 and operation 120 . FIGS. 2 to 4 are schematic cross-sectional views of a semiconductor substrate at different stages of formation according to some embodiments of the present disclosure.

Please refer to Figures 1 to 3. In some embodiments, in operation 110, as shown in FIG. 2, a composite substrate 230 is received, the composite substrate 230 includes a low-resistance substrate 210 and a high-resistance substrate 220, and the high-resistance substrate 220 is disposed on the low-resistance substrate 210 , the high-resistance substrate 220 is thinned to form the composite substrate 330 as shown in FIG. 3 . After the high-resistance substrate 220 shown in FIG. 2 is thinned, the high-resistance substrate 220 a shown in FIG. 3 is formed. In some embodiments, receiving the composite substrate 230 includes the step of bonding the low-resistance substrate 210 to the high-resistance substrate 220 .

In some embodiments, the low-resistance substrate 210 has a first resistance of 0.0001 to 1 Ohm-cm. The first resistance value is, for example, 0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001, 0.01, 0.02, 0.03, 0.04, 0.05, 0.08, or 1 Ohm-cm. In some embodiments, the high resistance substrate 220 has a second resistance value ranging from 1 to 10,000 Ohm-cm. The second resistance value is, for example, 1, 10, 100, 500, 1000, 3000, 5000, 7000, 8000, 9000 or 10000 Ohm-cm. It should be noted that when the resistance value of the high-resistance substrate 220 and the resistance of the low-resistance substrate 210 are significantly different, for example, the resistance of the high-resistance substrate 220 is 1000 times that of the low-resistance substrate 210, the high-resistance The insulating effect of the value substrate 220 may be similar to that of the silicon dioxide (SiO ₂ ) layer in the SOI substrate.

Please refer to Figures 1 and 3. In other embodiments, in operation 110, as shown in FIG. 3, a composite substrate 330 is received. The composite substrate 330 includes a low-resistance substrate 210 and a high-resistance substrate 220a, and the high-resistance substrate 220a is set at a low-resistance value. on the substrate 210 . In some embodiments, receiving the composite substrate 330 includes the step of bonding the low-resistance substrate 210 to the high-resistance substrate 220a.

m的厚度。厚度例如是10 nm 、100nm、1000nm、0.5

m、0.8

m、1

m、1.2

m、1.5

m、1.8

m、2

m、2.5

m、3

m、5

m、8

m或10

m。 In some embodiments, the high-resistance substrate 220a has a thickness between 10 nm and 10 nm.

m thickness. Thickness is, for example, 10 nm, 100 nm, 1000 nm, 0.5

m, 0.8

m, 1

m, 1.2

m, 1.5

m, 1.8

m, 2

m, 2.5

m, 3

m, 5

m, 8

m or 10

m.

Please refer to Figures 1 and 4. In operation 120, an epitaxial layer 410 is formed on the high resistance substrate 220a. In other words, the epitaxial layer 410 is formed on the composite substrate 330 . In some embodiments, the epitaxial layer 410 includes, but is not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium gallium phosphide, indium gallium antimonide, or combinations thereof.

The present disclosure provides a semiconductor substrate 400 . The semiconductor substrate 400 includes a low-resistance substrate 210 , a high-resistance substrate 220 a and an epitaxial layer 410 . The low-resistance substrate 210 has a first resistance ranging from 0.0001 to 1 Ohm-cm. The high-resistance substrate 220 a is disposed on the low-resistance substrate 210 and directly contacts the low-resistance substrate 210 . The high resistance value substrate 220a has a second resistance value ranging from 1 to 10000 Ohm-cm. The epitaxial layer 410 is disposed on the high-resistance substrate 220a.

In some embodiments, the low-resistance substrate 210 has a first resistance of 0.0001 to 1 Ohm-cm. The first resistance value is, for example, 0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001, 0.01, 0.02, 0.03, 0.04, 0.05, 0.08, or 1 Ohm-cm. In some embodiments, the high resistance substrate 220a has a second resistance value ranging from 1 to 10,000 Ohm-cm. The second resistance value is, for example, 1, 10, 100, 500, 1000, 3000, 5000, 7000, 8000, 9000 or 10000 Ohm-cm. It is worth noting that when the resistance value of the high-resistance substrate 220a and the resistance of the low-resistance substrate 210 are significantly different, for example, the resistance of the high-resistance substrate 220a is 1000 times that of the low-resistance substrate 210, the high-resistance The insulating effect of the value substrate 220a would be similar to that of _SiO2 in the SOI substrate.

In some embodiments, the low-resistance substrate 210 is a super-heavy doped wafer. In some embodiments, the material of the low resistance substrate 210 includes boron, phosphorus, arsenic, antimony, or a combination thereof. In some embodiments, the epitaxial layer 410 includes gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium gallium phosphide, indium gallium antimonide, or a combination thereof. In some embodiments, the epitaxial layer 410 is a gallium nitride epitaxial layer.

The higher the dopant concentration in the low-resistance substrate 210 is, the lower the resistance of the low-resistance substrate 210 is. Since the low-resistance substrate 210 of the present disclosure has the characteristics of low resistance, the low-resistance substrate 210 has high mechanical strength, and therefore, the semiconductor substrate 400 is not easily warped.

m的厚度。厚度例如是10 nm、100nm、1000nm、0.5

m、0.8

m、1

m、1.2

m、1.5

m、1.8

m、2

m、2.5

m、3

m、5

m、8

m或10

m。值得注意的是，當高阻值基板220a的厚度越薄，複合基板330也越薄，因此磊晶層410對複合基板330造成的應力也會越小。換句話說，磊晶層410對高阻值基板220a造成的應力也會越小。此外，因為低阻值基板210的阻值極低，所以基板機械強度較高，因此能夠抵抗磊晶層410造成的應力，進而提升磊晶層410之品質，以及減少磊晶層差排所造成的缺陷，進一步避免晶片翹曲或斷裂。 In some embodiments, the high-resistance substrate 220a has a thickness between 10 nm and 10 nm.

m thickness. Thickness is, for example, 10 nm, 100 nm, 1000 nm, 0.5

m, 0.8

m, 1

m, 1.2

m, 1.5

m, 1.8

m, 2

m, 2.5

m, 3

m, 5

m, 8

m or 10

m. It should be noted that, when the thickness of the high-resistance substrate 220a is thinner, the composite substrate 330 is also thinner, so the stress caused by the epitaxial layer 410 to the composite substrate 330 is also smaller. In other words, the stress caused by the epitaxial layer 410 to the high-resistance substrate 220a will be smaller. In addition, because the resistance value of the low-resistance substrate 210 is extremely low, the mechanical strength of the substrate is relatively high, so it can resist the stress caused by the epitaxial layer 410 , thereby improving the quality of the epitaxial layer 410 and reducing the dislocation caused by the epitaxial layer. defects, further avoiding wafer warpage or breakage.

In some embodiments, silicon substrates with different crystal orientations can be selected as the low-resistance substrate 210 according to design requirements. For example, the crystal orientation of the low-resistance substrate 210 is (100), but not limited thereto. In some embodiments, silicon substrates with different crystal orientations can be selected as the high-resistance substrate 220a according to design requirements. For example, the crystal orientation of the high-resistance substrate 220a is (111), but not limited thereto.

In some embodiments, the method of forming the epitaxial layer 410 includes, but is not limited to, a chemical vapor deposition (CVD) epitaxial process or a molecular beam epitaxy (MBE) process.

The semiconductor substrate of the present disclosure includes a composite substrate and an epitaxial layer. The composite substrate includes a low-resistance substrate and a high-resistance substrate. Due to the large difference in resistance between the low-resistance substrate and the high-resistance substrate, the insulating effect of the high-resistance substrate is similar to that of the silicon dioxide (SiO ₂ ) layer in the SOI substrate. Since the thickness of the high-resistance substrate is thinner, the stress caused by the epitaxial layer to the high-resistance substrate is also smaller. The low-resistance substrate has high mechanical strength, so it can resist the stress caused by the epitaxial layer, can improve the quality of the epitaxial layer and reduce the stress caused by the dislocation of the epitaxial layer. Therefore, the semiconductor substrate of the present disclosure is not easy to warp characteristics.

Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of the present invention that fall within the scope of the appended claims.

100 : method 110 : Operation 120 : Operation 210 : Low Resistance Substrate 220 : High Resistance Substrate 230 : Composite substrate 220a : High Resistance Substrate 330 : Composite Substrate 400 : Semiconductor substrate 410 : Epitaxial layer

The detailed description of the present disclosure will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a method of forming a semiconductor substrate according to some embodiments of the present disclosure. FIGS. 2 to 4 are schematic cross-sectional views of a semiconductor substrate at different stages of formation according to some embodiments of the present disclosure.

Domestic storage information without Overseas storage information without

210 : Low Resistance Substrate 220a : High Resistance Substrate 330 : Composite Substrate 400 : Semiconductor substrate 410 : Epitaxial layer

Claims (8)

A semiconductor substrate, comprising: a low-resistance substrate having a first resistance between 0.0001-1 Ohm-cm; a high-resistance substrate disposed on the low-resistance substrate and in direct contact with the low-resistance substrate, the high-resistance substrate having a second resistance value ranging from 1 to 10,000 Ohm-cm; and An epitaxial layer is disposed on the high-resistance substrate. The semiconductor substrate of claim 1, wherein the low-resistance substrate is a super-heavy doped wafer. The semiconductor substrate of claim 1, wherein the material of the low-resistance substrate comprises boron, phosphorus, arsenic, antimony or a combination thereof. The semiconductor substrate of claim 1, wherein the epitaxial layer comprises gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium gallium phosphide, indium gallium antimonide, or a combination thereof. The semiconductor substrate of claim 1, wherein the high-resistance substrate has a thickness between 10 nm and 10

m thickness. A method of forming a semiconductor substrate, comprising: A composite substrate is received, the composite substrate includes a low-resistance substrate and a high-resistance substrate, the high-resistance substrate is disposed on the low-resistance substrate, wherein the low-resistance substrate has a value between 0.0001~1 Ohm-cm a first resistance value, the high resistance value substrate has a second resistance value ranging from 1 to 10000 Ohm-cm; and An epitaxial layer is formed on the high-resistance substrate. The method of claim 6, wherein receiving the composite substrate comprises the steps of: bonding the low-resistance substrate to the high-resistance substrate; and The high resistance substrate is thinned. The method of claim 6, wherein the high-resistance substrate has a thickness between 10 nm and 10

m thickness.

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