WO2022179615A1

WO2022179615A1 - Method for manufacturing semiconductor-on-insulator structure

Info

Publication number: WO2022179615A1
Application number: PCT/CN2022/077979
Authority: WO
Inventors: 黄河; 丁敬秀; 向阳辉
Original assignee: 中芯集成电路（宁波）有限公司上海分公司
Priority date: 2021-02-26
Filing date: 2022-02-25
Publication date: 2022-09-01

Abstract

The present invention relates to a method for manufacturing a semiconductor-on-insulator structure. The method comprises: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite each other, and forming a semiconductor layer on the side of the first surface; forming a first oxide bonding layer on the semiconductor layer by means of an in-situ steam generation process; providing a second wafer, and forming a second oxide bonding layer on a surface of the second wafer; bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer; and removing the first wafer from the side of the second surface until the semiconductor layer is exposed. In the present invention, a first oxide bonding layer is formed on a first wafer by means of an ISSG process to shorten the time of the ISSG process and limit a degree of diffusion of impurities, and internal stress of the first wafer is reduced by means of a high temperature, so as to eliminate free bonds and polarization induced by free bonds.

Description

Methods of fabricating semiconductor-on-insulator structures

technical field

The present invention relates to the field of semiconductor device manufacturing, in particular to a method for manufacturing a semiconductor-on-insulator structure.

Background technique

Semiconductors on insulators, such as silicon-on-insulator (SOI), germanium-on-insulator, silicon-germanium-on-insulator, etc., all have a unique three-layer structure of "bottom semiconductor layer/buried insulating layer/top semiconductor layer" Semiconductor material, which realizes full dielectric isolation of the device (formed in the top semiconductor layer) and the substrate (that is, the bottom semiconductor layer) through an insulating buried layer (usually silicon dioxide SiO ₂ ), which can completely eliminate the formation of bulk silicon The parasitic latch-up effect in the CMOS circuit, and the circuit based on the semiconductor-on-insulator substrate also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short-channel effect, and is especially suitable for low-voltage and low-power circuits. and other advantages. Therefore, semiconductor-on-insulator substrates are widely used in the field of microelectronics.

technical problem

However, the semiconductor-on-insulator substrate manufactured by the traditional technology has problems such as a thick top semiconductor layer and surface defects, which cannot meet the demand for further improvement of device performance, and therefore needs to be improved.

technical solutions

The object of the present invention is to provide a method for manufacturing a semiconductor-on-insulator structure, which can make the film thickness of the semiconductor in the semiconductor-on-insulator structure thinner, so as to meet the manufacturing requirements of high-performance devices.

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor-on-insulator structure, comprising: providing a first wafer, the first wafer has an opposite first surface and a second surface, on the first surface forming a semiconductor layer on the side; forming a first oxidative bonding layer on the semiconductor layer by an in-situ vapor generation process; providing a second wafer, and forming a second oxidative bonding layer on the surface of the second wafer; bonding the first oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer; removing the first wafer from the second surface side wafer until the semiconductor layer is exposed.

beneficial effect

The beneficial effect of the present invention is: by adopting the in-situ steam generation process (ISSG process) to form the first oxide bonding layer on the semiconductor layer, so as to shorten the time for forming the first oxide bonding layer, limit the degree of impurity diffusion, and pass the high temperature Reduce the internal stress of the first wafer; through the strong oxidation environment of ISSG, generate a dense and low defect density first oxide bonding layer, reduce the free bond between the semiconductor layer and the BOX interface after removing the first wafer, and eliminate as much as possible The polarization caused by the free bond reduces the influence of the polarization on the normal operation of the PN junction in the semiconductor layer after the first wafer is removed.

In addition, by making the first wafer and the semiconductor layer have different ion doping concentrations, when the first wafer is removed by a wet etching process, the wet etching rate for the first wafer is higher than the wet etching rate for the semiconductor layer. The first wafer is an etching enhancement layer, which can be quickly removed without causing unnecessary damage to the semiconductor layer, so that the semiconductor layer that finally forms the semiconductor-on-insulator structure is thinner and the film thickness is more uniform. , the process is simple and easy to implement; or, by using the depth and thickness of the first ion doping layer to define the thickness of the first wafer between the first ion doping layer to be formed and the first oxidative bonding layer, namely The thickness of the semiconductor layer of the semiconductor-on-insulator structure, so as to form a thinner and more uniform semiconductor layer, and also in the process of etching the first wafer until the first ion-doped layer is removed, using the first The ion-doped layer serves as a stop layer and a protective layer to avoid unnecessary damage to the semiconductor layer of the semiconductor-on-insulator structure in the process of removing the first ion-doped layer.

Further, by using nitrogen or deuterium doping, nitrogen or deuterium gas is injected into the interface between the polysilicon gate and silicon dioxide, thereby increasing the physical thickness of the first oxide bonding layer; in addition, it can also avoid increasing the interface state while , significantly improved the NBTI effect.

Further, since the compactness and flatness of the first oxide bonding layer formed by the ISSG process are good, the first oxide bonding layer is bonded to the second oxide bonding layer by fusion bonding, which can improve the first oxide bonding layer. The bonding strength of the first oxide bonding layer and the second oxide bonding layer.

Further, the etching process such as wet etching process can remove quickly and avoid unnecessary damage to the semiconductor layer, so that the semiconductor layer is thinner and the film thickness is more uniform.

Further, after removing the first wafer, the thickness of the semiconductor layer is also measured, and according to the measurement result, the entire surface or partial surface of the semiconductor layer is ion bombarded with an ion beam, so that the surface of the semiconductor layer is trimmed to make the semiconductor layer The thickness of the layer is further reduced, and the uniformity of the film thickness is further improved.

Further, after removing the first wafer to expose the semiconductor layer/after removing the first ion-doped layer, a surface oxidation treatment process and/or anisotropic etching process are also used to remove damage on the surface of the semiconductor layer, so as to It is beneficial to improve the performance of a device formed based on the semiconductor-on-insulator structure.

Further, a microcrystalline layer is provided under the second oxide bonding layer on the surface of the second wafer provided, and the microcrystalline layer can form a trap rich layer in the second wafer. layer) to hinder the flow of free carriers in the semiconductor-on-insulator structure, thereby reducing parasitic phenomena in the semiconductor-on-insulator structure and improving the electrical performance of the semiconductor-on-insulator structure.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

FIG. 1 shows a flowchart of a method for manufacturing a semiconductor-on-insulator structure provided by an embodiment of the present invention.

FIGS. 2-8 are schematic structural diagrams corresponding to different steps of the manufacturing method of the semiconductor-on-insulator structure according to Embodiment 1 of the present invention.

9-14 are schematic structural diagrams corresponding to different steps of the manufacturing method of the semiconductor-on-insulator structure according to Embodiment 2 of the present invention.

10-first wafer; 10a-first surface; 110-pad oxide layer; 100-base wafer layer; 101-first ion-doped layer; 11-semiconductor layer; 12-first Oxidation bonding layer; 13-regenerated oxide layer; 20-second wafer; 200-single crystal silicon layer; 201-microcrystalline layer; 21-second oxidation bonding layer.

Embodiments of the present invention

Because the SOI wafer with the traditional thin-film silicon layer has many free bonds at the interface between the thin-film silicon and the BOX, polarization characteristics will occur, which will affect the normal operation of the PN junction in the thin-film silicon layer. Therefore, a rapid heat treatment process is used to form the underlying oxide bonding layer. , to eliminate free bonds and polarization.

The manufacturing method of the semiconductor-on-insulator structure of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and accompanying drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various forms, and is not limited to the specific implementation described here. example. The accompanying drawings are all in a very simplified form and in an inaccurate scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The terms "first," "second," and the like, in the specification and claims are used to distinguish between similar elements, and are not necessarily used to describe a particular order or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances, eg, to enable the embodiments of the invention described herein to operate in other sequences than described or illustrated herein. Similarly, if a method described herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and/or some not described herein Additional steps can be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.

实施例Example 11

An embodiment of the present invention provides a method for fabricating a semiconductor-on-insulator structure. FIG. 1 is a flowchart of a method for fabricating a semiconductor-on-insulator structure according to Embodiment 1 of the present invention. Please refer to FIG. 1 . The manufacturing method includes: providing a first wafer having opposing first and second surfaces, forming a semiconductor layer on the side of the first surface; and forming a semiconductor layer on the semiconductor layer by an in-situ vapor generation process forming a first oxide bonding layer; providing a second wafer, and forming a second oxide bonding layer on the surface of the second wafer; bonding the first oxide bonding layer and the second oxide bond the first wafer is bonded to the second wafer; the first wafer is removed from the second surface side until the semiconductor layer is exposed. The above steps do not represent a sequential order.

Among them, there are at least two methods for forming the semiconductor layer. Method 1, providing a first wafer with a first ion doping concentration; forming the semiconductor layer with a second ion doping concentration on the first surface side, the first ion doping concentration being greater than the first ion doping concentration Diion doping concentration. Method 2, providing a first wafer; performing P-type ion implantation on the first wafer along the first surface to form a first ion-doped layer at a preset depth of the first wafer, the The semiconductor layer is the first wafer between the first ion-doped layer and the first surface.

Referring to FIG. 2 to FIG. 8 , the method for fabricating the semiconductor-on-insulator structure provided by this embodiment is described in detail by taking the first method as an example.

Referring to FIG. 2, step S01 is performed to provide a first wafer 10 having a first ion doping concentration. The material of the first wafer 10 may be any well-known substrate material in the art, such as silicon, germanium, silicon germanium, and the like. In this embodiment, the material of the first wafer 10 is monocrystalline silicon, and is doped with first ions as a whole, and the ions doped with the first ions are N-type or P-type ions, wherein the N-type ions include phosphorus, Arsenic, antimony, etc., P-type ions include boron, indium, gallium, etc., the first ion doping concentration ranges from 5E+17 cm ^-3 to 5E+19 cm ^-3 , for example, 1E+18 cm ^-3 . The surface of the first wafer 10 may be mechanically polished, and its thickness is, for example, 10 μm˜80 μm. In other embodiments, a first silicon wafer with a second ion doping concentration is provided, and in a subsequent step, ion doping is performed on the first silicon wafer to form a first silicon wafer with the first ion doping concentration The first wafer 10 .

Continuing to refer to FIG. 2 , step S02 is performed to form a semiconductor layer 11 having a second ion doping concentration on the first surface side of the first wafer 10 , and the first ion doping concentration is greater than the second ion doping concentration. In a possible implementation manner, the method for forming the semiconductor layer 11 with the second ion doping concentration on the first wafer 10 includes: depositing and forming the semiconductor layer 11 on the first wafer 10; The ions are doped to have a second ion doping concentration, and the second ion doping concentration is smaller than the first ion doping concentration. It should be noted that the deposition method includes chemical vapor deposition or physical vapor deposition. A semiconductor layer 11 is formed on the surface of the first wafer 10 , and the thickness of the semiconductor layer 11 may be slightly higher than that required by the semiconductor-on-insulator structure to be formed, eg, 200 angstroms to 80 microns. In another possible implementation manner, the method for forming the semiconductor layer 11 with the second ion doping concentration on the first wafer 10 includes: epitaxially growing the semiconductor layer 11 with the second ion doping concentration on the first wafer 10 the semiconductor layer 11. The epitaxial growth process may be an epitaxial growth process such as molecular beam epitaxy (MBE), chemical vapor deposition (CVD) or liquid phase deposition (LPE). Optionally, N-type ions or P-type ions may be doped during the epitaxial growth of the semiconductor layer 11 and further annealed to form the second ion lightly doped semiconductor layer 11 , or the epitaxial growth of the semiconductor layer 11 may be terminated. Then, N-type ions or P-type ions are implanted into the semiconductor layer 11 and further annealed to form the second ion-lightly doped semiconductor layer 11 . The concentration range of the second ion light doping is 5E+14 cm ^-3 ~5E+16 cm ^-3 . In this step, by using the epitaxial growth process to form the semiconductor layer 11 , the thickness of the semiconductor layer 11 can be precisely controlled, and finally a semiconductor-on-insulator structure that meets the requirements can be formed. In addition, the main material of the semiconductor layer 11 determines the material of the semiconductor layer of the semiconductor-on-insulator structure to be formed. For example, when the main material of the semiconductor layer 11 is monocrystalline silicon, the semiconductor-on-insulator structure fabricated in this embodiment is an insulator For the silicon-on-silicon structure, when the main material of the semiconductor layer 11 is germanium, the semiconductor-on-insulator structure fabricated in this embodiment is a germanium-on-insulator structure. When the main material of the semiconductor layer 11 is silicon-germanium, the semiconductor-on-insulator structure fabricated in this embodiment is The semiconductor structure is a silicon germanium-on-insulator structure.

In addition, after the semiconductor layer 11 is formed, the surface of the semiconductor layer 11 with the second ion doping concentration can be further polished to make its film thickness uniformity meet the requirements, and the thickness of the polished semiconductor layer 11 is, for example, 200 angstroms~ 80 microns. As an example, the thickness of the polished semiconductor layer 11 is 5 micrometers to 20 micrometers, and a thicker semiconductor layer 11 is beneficial to prevent the semiconductor layer 11 from being completely ground off during mechanical thinning. The ion doping type of the semiconductor layer 11 and the first wafer 10 is the same, that is, both are N-type ion-doped or both are P-type ion-doped, so that the efficiency of epitaxial growth of the semiconductor layer 11 can be improved, and the semiconductor layer can be prevented from being doped. 11 and the dopant ions in the first wafer 10 diffuse each other to affect the etching selection ratio of the two in the subsequent step S6, which is conducive to the removal of the first wafer 10 in the subsequent steps, and finally ensures the formation of the semiconductor-on-insulator. Properties of the semiconductor layers in the structure.

Referring to FIG. 3, step S03 is performed to form a first oxide bonding layer on the semiconductor layer through an in-situ vapor generation process.

Before performing step S03, in-situ sputtering is used to remove native oxides, where native oxides refer to oxides naturally oxidized by air. In this embodiment, the in-situ removal of the native oxide may be performed by sputtering without changing the original environment, such as bombarding the first surface with argon gas under high-energy acceleration to remove the native oxide layer.

The in-situ steam generation technology is a low-pressure wet rapid thermal oxidation method with high reproducibility. The in-situ steam generation technique can be performed in a single-wafer RTP reactor, such as the Applied Materials Co. RTP XEplus Centura model, which is equipped with 15 to 25 parallel tungsten halogen heating lamps ( tungsten halogen lamp), to rapidly heat the chip to the required high temperature, pass hydrogen and oxygen into the RTP reactor, and carry out an oxidative manufacturing process containing oxygen radicals and hydroxyl radicals, thereby forming an oxide layer on the surface of the chip. It should be noted that the in-situ steam generation process adopts In-Situ Steam Generation process, referred to as ISSG process.

Specifically, during the ISSG process, the surface of the first wafer 10 is oxidized through an oxidation reaction to generate the first oxidized bonding layer 12, wherein the reaction temperature of the in-situ steam generation process is 900°C- 1200°C, reaction pressure 700-2000 Pa, flow rate of doping gas: 10-1000sccm. In the actual operation process, oxygen can also be doped with hydrogen to generate high-density gas-phase oxygen radicals, which can easily react with silicon to generate a high-quality, high-density first oxide bonding layer 12 . In addition, in the oxidation process, it is necessary to control the content of hydrogen to avoid high hydrogen content so that its ability to combine with oxygen to generate water is enhanced, so as to avoid the generation of less oxygen radicals to avoid the situation of poor oxidation rate and density. In addition, by controlling the process temperature, the internal stress of the first wafer 10 can be reduced; by controlling the reaction pressure and gas flow rate, the reaction rate can be increased.

In an alternative embodiment of the present invention, the first oxide bonding layer 101 is an XEplus The total flow in the Centura model RTP reactor (total Gas flow rate, TGF) is formed under the conditions of hydrogen and oxygen of about 10SLM. Wherein the hydrogen flow ratio (%H2 of TGF) is 2%, the pressure of the RTP reactor should be controlled below 700-2000 Pa, 1000 Pa, 1400 Pa, 1800 Pa and so on can be selected. During the reaction, the first surface of the first wafer 10 is rapidly heated to 900°C to 1200°C by a tungsten filament halogen heating lamp, which can be 1000°C, 1100°C, etc., and maintained at this temperature for about 20 to 25 seconds. Since the reaction pressure is controlled in the range of 700-2000 Pa, the ISSG high temperature rapid oxidation reaction is in a mass transport controlled state (mass transport controlled regime), and changes in pressure directly affect the mass transfer rate (mass) during the oxidation process. transport rate). Due to the short heating time of the ISSG technique, the concentration profile of the doped region is not affected.

After the first oxide bonding layer 12 is formed by the ISSG process, nitrogen or deuterium are doped at the interface between the first oxide bonding layer 12 and the first wafer 10 to increase the physical thickness of the first oxide bonding layer 12 , and significantly improve the NBTI effect without increasing the interface state. When doping nitrogen, a nitrogen-containing gas is selected for doping, and the nitrogen-containing gas includes NO, N ₂ O, NO ₂ , N ₂ or NH ₃ ; when doping with deuterium, a deuterium-containing gas is selected for doping, and the hydrogen-containing gas is selected for doping. Including _D2 . In addition, the gas flow rate of nitrogen or deuterium is 10 to 1000 sccm. In the actual doping process, a dedicated DPN (Decoupled Plasma Nitridation) chamber is often used.

The material of the first oxide bonding layer 12 may be a dielectric material, and the dielectric material includes silicon dioxide, or a combination of silicon dioxide and silicon oxynitride. The oxide layer generated by the ISSG process is relatively thin, so multiple oxidation treatments can be performed by the ISSG process to form the first oxide bonding layer 12 that meets the thickness requirement. The in-situ steam generation process is performed at least once, so that the thickness of the generated first oxide bonding layer 12 is in the range of 10-50 angstroms, so as to facilitate the subsequent better bonding of the first oxide bonding layer 12 and the second oxide bonding layer. . It should be noted that if the thickness is too thin, a sufficient bonding phase fusion interface cannot be provided; if the thickness is too thick, the bonding strength will be reduced to varying degrees. For example, at least two ISSG processes may be performed, each time the thickness is at least 10-25 angstroms, and the final thickness is in the range of 10-50 angstroms. Alternatively, one ISSG process may be selected to form the first oxide bonding layer 12 with a thickness of 10-50 angstroms.

4 , step S04 is performed, a second wafer 20 is provided, and a second oxide bonding layer 21 is formed on the surface of the second wafer 20 .

First, a second wafer 20 is provided, and the second wafer 20 may be any suitable base material known to those skilled in the art, such as monocrystalline silicon, germanium, silicon germanium, and the like. In this embodiment, the second wafer 20 includes a monocrystalline silicon layer 200 on the bottom and a microcrystalline layer 201 on the surface of the monocrystalline silicon layer 200 , wherein the microcrystalline layer 201 may include a polycrystalline silicon layer, a silicon germanium alloy layer, a metal At least one of silicide, metal germanide, and germanium layers. The grain size of the microcrystalline layer 201 is 1 nanometer to 10 micrometers, and the thickness of the microcrystalline layer 201 needs to be controlled to be more than 1 nanometer, so that a trap rich layer can be formed in the second wafer 20 . layer), which can hinder the flow of free carriers in the subsequently formed semiconductor-on-insulator structure, reduce parasitic phenomena in the semiconductor-on-insulator structure, and improve the electrical properties of the semiconductor-on-insulator structure. 201 has problems with the stability and yield of the manufacturing process. The formation process of the microcrystalline layer 201 may adopt a low pressure chemical vapor deposition polysilicon process or an ion implantation process.

Next, a second oxide bonding layer 21 is formed on the second wafer 20 using a vapor deposition process, thermal oxidation or an in-situ vapor generation process. The vapor deposition process specifically includes: using an atomic layer deposition process or a chemical vapor deposition process with a process temperature lower than 600° C. to form the second oxide bonding layer 21 on the surface of the microcrystalline layer 201 . For the ISSG process, reference may be made to the foregoing process for forming the first bonding oxide layer, which will not be repeated here. The thickness of the second oxide bonding layer 21 is 10 angstroms˜50 angstroms. If the thickness is too thin, it cannot provide enough bonding phase fusion interface; if the thickness is too thick, the bonding strength will be reduced to varying degrees. In addition, the material of the second oxidative bonding layer 21 can be set with reference to the material of the first oxidative bonding layer 12 , which will not be repeated here. The thermal oxidation process uses oxygen to react with the microcrystalline layer 201 to form the second oxidative bonding layer 21 .

It should be noted that both the first oxide bonding layer 12 and the second oxide bonding layer 21 can be formed by the ISSG process, and the thickness of the oxide layer formed by the vapor deposition process and the thermal oxidation process is relatively uniform, which can limit the degree of diffusion of impurities , and reduce the internal stress of the first wafer and the second wafer through high temperature, reduce the free bond of the top silicon and the bonding interface, so as to eliminate the polarization caused by the free bond.

It should be noted that step S04 may be performed after step S03, may be performed after step S01 and before step S03, may be performed simultaneously with step S03, or may be performed prior to step S01. Optionally, after step S02, the first wafer 10 and the second wafer 20 with the semiconductor layer 11 formed on the surface are put into the same deposition process equipment to adopt the same process conditions, and simultaneously form the first oxide The bonding layer 12 and the second oxide bonding layer 21 are formed, thereby simplifying the process and improving the efficiency, that is, at this time, the steps S04 and S03 are performed simultaneously, and the first oxide bonding layer 12 and the second oxide bonding layer are formed. The thickness and performance of 21 are basically the same, which is beneficial to improve the bonding performance in step S05.

Referring to FIG. 5 , step S05 is performed to bond the first oxide bonding layer 12 and the second oxide bonding layer 21 to bond the first wafer to the second wafer 20 .

In this embodiment, the bonding process of the first oxide bonding layer 12 and the second oxide bonding layer 21 includes fusion bonding. After bonding the first oxide bonding layer 12 and the second oxide bonding layer 21, the entire structure after bonding is annealed and strengthened, the annealing temperature is 300 ° C ~ 1100 ° C, and the annealing time is 30 minutes ~ 180 minutes, The annealing gas includes at least one of nitrogen, argon, and hydrogen. It should be noted that if the annealing temperature is too high, ion redistribution will occur between the first wafer 10 and the semiconductor layer 11 , while the annealing temperature is too low to cause the first oxide bonding layer 12 and the second oxide bonding layer 21 are securely bonded together. In addition, if the annealing temperature is too high and the annealing time is too long, the ion doping in the semiconductor layer 11 will diffuse vertically, which will affect the control of the ion diffusion depth. Thickness is uncontrollable. On the other hand, the annealing process can further “smooth” the uneven doping band in the semiconductor layer 11 to form a uniform ion doping layer, which is beneficial to removing the first wafer 10 in the subsequent step S06 and is beneficial to The thickness of the remaining semiconductor layer 11 is controlled. Therefore, choosing an appropriate annealing temperature and annealing time is critical. Therefore, choosing an appropriate annealing temperature and annealing time is critical. In this embodiment, the annealing temperature is 300° C.˜1000° C., and the annealing time is 30 minutes˜180 minutes. The annealing gas includes at least one inert gas among helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), nitrogen (N ₂ ), and the like. As an example, the annealing temperature may be 300° C.˜500° C., and the annealing time may be 30 minutes˜150 minutes.

Referring to FIG. 6, step S06 is performed to remove the first wafer from the second surface side until the semiconductor layer is exposed.

The method for removing the first wafer includes: removing the first wafer by a wet etching process to expose the semiconductor layer 11, and the wet etching rate of the wet etching process for the first wafer is higher than that for the semiconductor layer. etching rate. It should be noted that the first wafer is thinned before the selective wet etching process is used to remove the first wafer. Specifically, a fine chemical mechanical polishing (CMP) process can be used to thin the first wafer until it is thinned to a suitable thickness, for example, to 70 microns. The fine chemical mechanical process can improve the overall thickness of the first wafer. removal efficiency, and can provide a good process surface for the subsequent selective wet etching process. Then, a selective wet etching process in which the first wafer has a high etching selectivity ratio relative to the semiconductor layer 11 is used to etch and remove the first wafer to expose the semiconductor layer 11 . In the wet etching process, the ion doping concentrations in the first wafer and the semiconductor layer 11 are different, so the two layers of materials can have a relatively high etching selectivity ratio, and the wet etching selectivity ratio range is, for example, 20-50 , so that the wet etching rate of the wet etching process for the first wafer is greater than the wet etching rate for the semiconductor layer 11 , the first wafer can be easily removed, and the etching can stop at the semiconductor layer 11 surface without causing serious damage to the semiconductor layer 11 . In this embodiment, the etchant used in the wet etching process includes at least one of nitric acid, hydrofluoric acid and acetic acid, for example, a mixed solution of nitric acid, hydrofluoric acid and acetic acid. The molar ratio to acetic acid is 1:10:60~1:1:1, specifically 15:25:60, the process temperature is 25°C to 45°C, and the etching time is 1 minute to 10 minutes. This mixed solution has a fast etching rate for high-concentration doped P+Si (greater than 10 μm/min), and a very low etching rate for low-concentration doped P-Si (less than 0.01 μm/min), so that it can be etched to When the semiconductor layer 11 is formed, the self-stop of the etching reaction is realized.

In addition, after removing the first wafer, the surface of the semiconductor layer 11 may be further polished by a fine chemical mechanical polishing process, so as to remove the residues on the semiconductor layer 11 after the selective wet etching process, and further polish the semiconductor layer 11. Layer 11 is reduced in thickness. After polishing and thinning, the thickness of the semiconductor layer 11 is measured, and according to the measurement result, ion reaction treatment is performed on the entire surface or partial surface of the semiconductor layer 11 by using an ion beam, so as to further trim the surface of the semiconductor layer 11, thereby further reducing the thickness of the semiconductor layer 11. The thickness of the semiconductor layer 11 is improved and the uniformity of the film thickness is improved. The process of thickness measurement and surface trimming can be performed in multiple cycles until the overall thickness and uniformity of the semiconductor layer 11 meet the requirements. Furthermore, according to the measurement results, an "ion beam surface treatment machine" is used to perform ion reaction treatment on the entire surface or partial surface of the semiconductor layer 11 to further surface trim the semiconductor layer 11, and the ion beam gas contains NF3, CF4, CHF3 , at least one of oxygen, nitrogen and argon, the energy is 5 watts to 500 watts, and the processing time of a single wafer is 1 minute to 30 minutes. It should be noted that the amount of energy and the length of processing time can be adjusted according to actual requirements, which will not be repeated here. In addition, the process of using ion beams to trim the surface of the semiconductor layer 11 has higher precision than the existing fine chemical mechanical polishing, so The remaining semiconductor layer 11 (ie, the top layer silicon of the silicon-on-insulator structure) can be controlled to be thinner and the film thickness is more uniform.

Referring to FIGS. 7 and 8 , after further surface trimming of the semiconductor layer 11, a semiconductor-on-insulator structure is formed, wherein the second wafer 20 is the underlying semiconductor layer of the semiconductor-on-insulator structure, the second oxide bonding layer 21 and the first The oxide bonding layer 12 is an insulating buried layer of a semiconductor-on-insulator structure, and the semiconductor layer 11 after surface trimming is a semiconductor layer of a semiconductor-on-insulator structure. The thickness of the semiconductor layer of the semiconductor-on-insulator structure can reach 200 angstroms to 10 microns.

In this embodiment, in order to remove and repair the damage on the surface of the semiconductor layer 11, a surface oxidation treatment process and/or an anisotropic etching process may be used. In a possible implementation manner, the semiconductor layer 11 is first subjected to high temperature oxidation treatment to form the regenerated oxide layer 13 , the process temperature is 700° C. to 1100° C., and the thickness of the regenerated oxide layer is 100 angstroms to 500 angstroms. Refer to FIG. 7 . , the process temperature in this range can facilitate the growth and regeneration of the oxide layer, and simultaneously strengthen the bonding interface, and the thickness of the oxide takes into account the depth of the surface damage layer. Referring to FIG. 8 , at least one process including wet etching, dry etching or chemical mechanical polishing is used to remove the regenerated oxide layer. In another possible implementation manner, an alkaline solution is used to anisotropically etch the surface of the semiconductor layer to remove the damaged layer on the surface of the semiconductor layer. Specifically, anisotropic etching is performed on the surface of the semiconductor layer 11 using an alkaline solution such as tetramethyl ammonium hydroxide TMAH, the etching time is 15 seconds to 2 minutes, and the etching temperature is normal temperature, for example, 25°C to 45°C, In order to remove and repair the surface damage of the semiconductor layer 11 . The characteristics of anisotropic etching of silicon by alkaline solution make the wafer surface form regular crystal planes distributed according to the crystal orientation, so as to obtain a more perfect wafer surface after removing the surface damage layer.

After the first wafer is removed and the semiconductor layer 11 is exposed, the method further includes: wet cleaning the semiconductor layer 11 by using a cleaning solution such as deionized water to remove surface contamination.

实施例Example 22

The difference between this embodiment and Embodiment 1 is that the formation method of the semiconductor layer is different. The semiconductor layer in this embodiment is formed by the second method. The following briefly describes the manufacturing method of the semiconductor-on-insulator structure provided in this embodiment.

9, step S01, providing a first wafer 10. For the material of the first wafer 10, refer to Embodiment 1. The first wafer 10 may be a wafer lightly doped with P-type ions or N-type ions as a whole, or may be composed of an undoped substrate at the bottom and an undoped base material at the bottom. A wafer composed of a lightly doped layer on an undoped substrate, the lightly doped layer may be the area between the subsequently divided first ion-doped layer and the first surface 10a of the first wafer 10, or It can be a region jointly formed by the region and the first ion-doped layer, and the lightly-doped layer is doped with N-type ions or P-type ions. The N-type ions include phosphorus, arsenic, antimony, etc., and the P-type ions include boron, indium, gallium, etc., and the doping concentration of the N-type ions or P-type ions doped in the lightly doped region in the first wafer 10 is low at 1E+16 cm ^-3 .

The first surface of the first wafer 10 may be mechanically polished. Then, chemical reagents (such as SC1, SC2, SPM, DHF, organic solvents, etc.), deionized water and other cleaning solutions can be used to clean the surface of the first wafer 10, and the cleaning process can be accompanied by ultrasonic vibration, heating, pumping, etc. Physical measures such as vacuum to remove surface impurities and defects. Among them, SC1 solution is a mixed solution composed of NH ₄ OH, H ₂ O ₂ and H ₂ O, SC2 solution is a mixed solution composed of HCl, H ₂ O ₂ and H ₂ O, or HCl solution, and SPM solution is A mixed solution consisting of H ₂ SO ₄ , H ₂ O ₂ and H ₂ O, DHF is an HF solution, or a mixed solution consisting of HF, H ₂ O ₂ and H ₂ O. Then, a pad oxide layer 110 can be formed on the first surface 10a of the first wafer 10 through a thermal oxidation process. The pad oxide layer 110 can prevent the surface of the first wafer 10 from being contaminated and can be used in the subsequent ion implantation process. The first wafer 10 is protected in the middle, and the tunnel penetration effect during ion implantation is improved. The temperature of the thermal oxidation process is 700° C.˜1100° C., and the thickness of the pad oxide layer 110 is 100 angstroms˜500 angstroms. Compared with the vapor deposition process, the thermal oxidation process has the advantages of high density and less ionic contamination.

Referring to FIG. 10, in step S02, P-type ion implantation is performed on the first wafer 10 along the first surface of the first wafer 10 to form a first ion-doped layer 101 at a predetermined depth of the first wafer.

While the first ion-doped layer 101 is formed, the first wafer 10 is divided into a sandwich structure composed of the base wafer layer 100 , the first ion-doped layer 101 and the semiconductor layer 11 . In this embodiment, P-type ions are used to form the first ion-doped layer 101 , except that the first wafer 10 can be divided into a base wafer layer 100 , a first ion-doped layer 101 and a semiconductor layer 11 that are stacked in sequence In addition, the thickness of the semiconductor layer 11 (that is, the thickness of the semiconductor layer of the semiconductor-on-insulator structure to be formed) can also be precisely defined, which is conducive to the formation of a thinner and more uniform semiconductor layer, and can avoid the use of oxygen, When other ions such as nitrogen and hydrogen are implanted, they diffuse into the semiconductor layer 11 and affect the performance of the semiconductor layer in the finally formed semiconductor-on-insulator structure. The preset depth in this embodiment is 10 μm, 5 μm, 1 μm or less.

When the initially provided first wafer 10 is lightly doped as a whole or the region formed by the semiconductor layer 11 and the first ion-doped layer 101 is lightly doped, ions of the same type as the first wafer 10 can be selected to Ion implantation is performed to form the first ion-doped layer 101 , thereby improving the efficiency of forming the first ion-doped layer 101 . For example, when the first wafer 10 initially provided is lightly doped with P-type ions, the P-type ion-doped layer is used. Ion implantation is performed on the first wafer 10 to form a first ion-doped layer 101 heavily doped with P-type ions. Wherein, the doping concentration of P-type ions in the semiconductor layer 11 and the base wafer layer 100 is lower than the doping concentration of P-type ions in the first ion-doped layer 101, and the first ion-doped layer 101 is heavily doped Yes, the ion doping concentration is higher than 1E+17 cm ^-3 , for example, 5E+17 cm ^-3 ~5E+19 cm ^-3 .

In this embodiment, in order to ensure the thickness of the first ion-doped layer 101 formed, different ion implantation parameters can be used to perform multi-step P-type ion implantation on the first wafer 10, including: each step of P-type ion implantation Ions are implanted into the first wafer 10 to form P-type ion-doped layers with different depths; the first wafer 10 is annealed to diffuse all the P-type ion-doped layers to form the first ion-doped layer 101 . It should be noted that each step of ion implantation is implemented with high energy, high dose and an implantation angle of 0 to 7 degrees; the energy of the ion implantation in the adjacent two steps of P rows can be different, and the implantation dose is the same, so that the adjacent two steps The depths of the two P-type ion doping layers formed by the ion implantation of the P rows are different, but the thicknesses are the same.

In addition, after the last step of P-type ion implantation is completed, the first wafer 10 is annealed at high temperature. ), argon (Ar), krypton (Kr), xenon (Xe), nitrogen (N ₂ ) and other at least one inert gas atmosphere, so that the implanted P-type ions are diffused in place, and adjacent two-step P row ion implantation forms The two P-type ion-doped layers can be connected up and down, so that the P-type ion-doped layers of different depths formed by the P-type ion implantation in each step are connected together after diffusion to form the first ion-doped layer 101 . And the distribution of P-type ions in the first ion-doped layer 101 is uniform. The thickness of the first ion-doped layer 101 is 5 μm˜20 μm, and the first ion-doped layer 101 within the thickness range is beneficial to prevent the first ion-doped layer 101 from being completely ground off during mechanical thinning.

Referring to FIG. 11, step S03, a first oxide bonding layer 12 is formed on the semiconductor layer 11 by an in-situ vapor generation process. If the pad oxide layer 110 is formed on the surface of the first wafer 10 in the foregoing steps, before step S03 is performed, the pad oxide layer 110 is removed by wet etching or dry etching, for example When the pad oxide layer 110 is removed by wet etching, the etchant is selected from hydrofluoric acid, the etching temperature is room temperature, and the etching time is 10 seconds to 100 seconds, for example, 60 seconds. Then, in-situ sputtering is used to remove the native oxide, which refers to the oxide that is naturally oxidized by air. In this embodiment, the in-situ removal of the native oxide may be performed by sputtering without changing the original environment, such as bombarding the first surface with argon gas under high-energy acceleration to remove the native oxide layer. The material of the first oxidative bonding layer 12 and the specific process of forming the first oxidative bonding layer 12 on the first surface through the in-situ steam generation process refer to Embodiment 1, which will not be repeated here.

Referring to FIGS. 12 to 14 , in step S04 , a second wafer 20 is provided, and a second oxide bonding layer 21 is formed on the surface of the second wafer 20 . The material of the second wafer 20 , the material of the second oxidative bonding layer 21 and the method of forming the second oxidative bonding layer 21 on the surface of the second wafer 20 refer to Embodiment 1, and are not repeated here. In step S05 , the first oxide bonding layer 12 and the second oxide bonding layer 21 are bonded, so that the first wafer 10 is bonded to the second wafer 20 . Specific reference is made to Example 1. Step S06, the first wafer 10 is etched along the second surface opposite to the first surface until the first ion-doped layer is removed.

The method for etching the first wafer 10 includes: grinding and flattening the first wafer 10 along the second surface. In this embodiment, the first wafer is firstly thinned to 30 microns by a grinding process, and then the first wafer is flattened by a chemical mechanical polishing process, so that the thickness is maintained at about 10 microns, so as to facilitate the subsequent wet process When etching the first wafer in the etching process, it is ensured that the thickness of the first wafer after etching is relatively uniform. The first wafer is etched along the second surface by wet etching until the first ion-doped layer is removed. In this step, a certain degree of over-etching may be performed to further thin the semiconductor after the first ion-doped layer is removed. Layer 11. Since the materials of the semiconductor layer 11 and the first ion-doped layer are different, the first ion-doped layer can be used as a stop layer for the backside thinning process to avoid damage to the semiconductor layer 11 caused by the backside thinning process. For the etchant and process conditions of the wet etching process, refer to Embodiment 1, which will not be repeated here.

After the first ion doping layer is removed, chemical mechanical polishing is further performed on the surface of the semiconductor layer 11 through a fine chemical mechanical polishing process to remove residues on the semiconductor layer 11 after the wet etching process, and the semiconductor layer 11 is further cleaned. Layer 11 is reduced in thickness. After removing the first ion-doped layer, the method includes: measuring the thickness of the remaining first wafer, and using ion beam gas according to the measurement result to perform ion beam gas on the entire surface or partial surface of the remaining first wafer. Ion reactive treatment to surface trim the remaining first wafer. Therefore, the thickness of the remaining first wafer 10 , that is, the thickness of the semiconductor layer 11 can meet the requirements, and the uniformity of the film thickness is further improved. The procedure of thickness measurement and surface modification refers to Example 1.

Continuing to refer to FIG. 14 , the semiconductor-on-insulator structure and the semiconductor layer 11 are formed, and the remaining steps refer to Embodiment 1.

To sum up, the first oxide bonding layer is formed on the semiconductor layer by adopting the in-situ steam generation process (ISSG process) to shorten the formation time of the first oxide bonding layer, limit the degree of impurity diffusion, and reduce the first crystal by high temperature. The internal stress of the circle; through the strong oxidation environment of ISSG, a dense and low defect density first oxide bonding layer is generated, which reduces the free bond between the semiconductor layer and the BOX interface after removing the first wafer, and eliminates the free bond as much as possible. Therefore, the influence of the polarization on the normal operation of the PN junction in the semiconductor layer after the removal of the first wafer is reduced.

It should be noted that each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. . In particular, for Example 2, since it is basically similar to Method Example 1, the description is relatively simple, and for related parts, please refer to the partial description of Example 1.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims

A method for manufacturing a semiconductor-on-insulator structure, comprising: providing a first wafer, the first wafer having an opposite first surface and a second surface, and forming a semiconductor layer on the side of the first surface; A first oxide bonding layer is formed on the semiconductor layer by an in-situ vapor generation process; a second wafer is provided, and a second oxide bonding layer is formed on the surface of the second wafer; An oxide bonding layer and the second oxide bonding layer to bond the first wafer to the second wafer; the first wafer is removed from the second surface side until exposed out the semiconductor layer.
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein the method for forming the semiconductor layer comprises: providing a first wafer having a first ion doping concentration; forming on the first surface side The semiconductor layer has a second ion doping concentration, the first ion doping concentration being greater than the second ion doping concentration.
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein the method for forming the semiconductor layer comprises: providing a first wafer; performing a P-type process on the first wafer along the first surface ion implantation to form a first ion-doped layer at a predetermined depth of the first wafer, and the semiconductor layer is the first crystal between the first ion-doped layer and the first surface round.
The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the in-situ vapor generation process selectively doped at least one of nitrogen or deuterium; when doping nitrogen, a nitrogen-containing gas is selected Doping is performed, and the nitrogen-containing gas includes NO, N 2 O, NO 2 , N 2 or NH 3 ; when doping with deuterium, a deuterium-containing gas is selected for doping, and the deuterium-containing gas includes D 2 .
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein the in-situ steam generation process comprises: a reaction temperature of 900-1200 degrees Celsius, a reaction pressure of 700-2000 Pa, and a flow rate of doping gas: 10- 1000sccm.
The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the in-situ steam generation process is performed at least once, so that the thickness of the generated first oxide bonding layer is in the range of 10-50 angstroms.
The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the method for bonding the first oxide bonding layer and the second oxide bonding layer comprises fusion bonding.
8. The method of claim 1, wherein the native oxide is removed by in-situ sputtering before forming the first oxide bonding layer on the first surface.
9. The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the second oxidative bonding layer is formed by a vapor deposition process, thermal oxidation or in-situ steam generation process.
The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the material of the first oxide bonding layer and/or the second oxide bonding layer comprises silicon dioxide or silicon dioxide and nitrogen Silicone combination.
The method of manufacturing a semiconductor-on-insulator structure according to claim 2, wherein the method of forming the semiconductor layer having the second ion doping concentration on the first surface side comprises: forming on the first wafer A semiconductor layer; performing ion doping on the semiconductor layer to make it have a second ion doping concentration; or, epitaxially growing a semiconductor layer with a second ion doping concentration on the first wafer.
The method for manufacturing a semiconductor-on-insulator structure according to claim 2, wherein the first ion doping concentration ranges from 5E+17 cm -3 to 5E+19 cm -3 ; the second ion doping concentration ranges from 5E+17 cm-3 to 5E+19 cm-3; The concentration range is 5E+14 cm -3 to 5E+16 cm -3 .
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein after bonding the first oxide bonding layer and the second oxide bonding layer, the entire structure after bonding is annealed For the reinforcement treatment, the annealing temperature is 300°C to 1100°C, the annealing time is 30 minutes to 180 minutes, and the annealing gas includes at least one of nitrogen, argon and hydrogen.
The method for manufacturing a semiconductor-on-insulator structure according to claim 2, wherein the method for removing the first wafer comprises: removing the first wafer by a wet etching process to expose the semiconductor layer, the wet etching rate of the wet etching process for the first wafer is greater than the wet etching rate for the semiconductor layer.
The method for manufacturing a semiconductor-on-insulator structure according to claim 14, wherein in the wet etching process, the wet etching selection ratio of the first wafer and the semiconductor layer is in the range of: 20~50; the etchant of the wet etching process comprises at least one of nitric acid, hydrofluoric acid and acetic acid, and the molar ratio of nitric acid, hydrofluoric acid and acetic acid in the solution is 1:10:60~1: 1:1, the process temperature is 25℃~45℃, and the etching time is 1 minute to 10 minutes.
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein after exposing the semiconductor layer, the method comprises: measuring the thickness of the semiconductor layer, and according to the measurement result, using an ion beam to The entire surface or partial surface of the semiconductor layer is subjected to ion reaction treatment, so as to further modify the surface of the semiconductor layer.
The method for manufacturing a semiconductor-on-insulator structure according to claim 1, wherein after exposing the semiconductor layer, the method further comprises: removing the semiconductor through a surface oxidation treatment process and/or an anisotropic etching process damage on the surface of the layer; wherein, the anisotropic etching process step includes: using an alkaline solution to anisotropically etch the surface of the semiconductor layer to remove the damaged layer on the surface of the semiconductor layer; the surface The step of oxidizing treatment includes: performing high-temperature oxidation treatment on the semiconductor layer to form a regenerated oxide layer, the process temperature is 700°C to 1100°C, and the thickness of the regenerated oxide layer is 100 angstroms to 500 angstroms; At least one process of dry etching or chemical mechanical polishing is used to remove the regenerated oxide layer.
The method for fabricating a semiconductor-on-insulator structure according to claim 1, wherein the second wafer comprises a single-crystal silicon layer and a silicon-on-insulator layer between the single crystal silicon layer and the second oxide bonding layer. Microcrystalline layer; the microcrystalline layer includes at least one of polycrystalline silicon, silicon germanium alloy and germanium.
The method for fabricating a semiconductor-on-insulator structure according to claim 3, wherein the multi-step P-type ion implantation is performed on the first wafer by using different ion-implantation parameters, comprising: each step of P-type ion implantation implanting into the first wafer to form P-type ion-doped layers of different depths; annealing the first wafer to diffuse all the P-type ion-doped layers to form the first ion-doped layers Miscellaneous layers.
The method for manufacturing a semiconductor-on-insulator structure according to claim 3, wherein a pad oxide layer is formed on the first surface before the P-type ion implantation is performed on the first wafer; Before removing the first oxide bonding layer, the pad oxide layer is removed.