JP2001135805A - Semiconductor member and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a preferable semiconductor member for forming an integrated circuit at high integration, and a method for manufacturing a semiconductor device in which a functional element is formed in such semiconductor member. SOLUTION: This method for manufacturing a semiconductor member comprises the steps of: forming a porous silicon layer on the surface of a first substrate; forming oxidization layers on the surface of the porous silicon layer and inside a hole; removing the oxidization layer formed on the surface of the porous silicon layer; thermally treating the porous silicon layer under a hydrogen ambiance; epitaxially growing a monocrystalline semiconductor layer on the porous silicon layer; laminating a second substrate in the monocrystalline semiconductor layer on the first substrate via an insulation layer therebetween; and eliminating the first substrate and the porous silicon layer from the laminated first and second substrates, to transfer the monocrystalline semiconductor layer onto the second substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor member, particularly to a semiconductor member suitable for forming a highly integrated circuit, and to a method of manufacturing a semiconductor device having a functional element formed on such a semiconductor member.

[0002]

2. Description of the Related Art Semiconductor members typified by single-crystal Si wafers are used as members for forming integrated circuits, and those having higher crystal quality are being developed.

On the other hand, with the increase in information handled by system equipment, higher integration and higher speed operation of integrated circuits are strongly required. Also, as the degree of integration increases, the dimensions of elements such as transistors in an integrated circuit become smaller, and the reliability of each element increases in maintaining or improving the chip yield in a semiconductor device manufacturing process at a certain level or higher. It is becoming very important. The reliability of each element such as a transistor and a diode is greatly affected by the surface flatness and crystallinity of a semiconductor member on which an integrated circuit is formed. For example, in a DRAM, 256 Mbits to 1 G
In order to achieve a bit-level integration degree, the thickness of the insulating layer formed on the semiconductor surface needs to be extremely thin, 1.0 to 1.5 nm. The refresh cycle is 64
A semiconductor member having good crystallinity capable of forming a DRAM of about msec to 128 msec is required.

Furthermore, in order to further enhance the reliability of the transistor, not only the above points but also the removal of metal or organic contaminants and particles existing on the surface of the semiconductor member is essential. For this reason, several surface cleaning methods have been proposed, but one of the cleaning methods currently considered to be effective for removing metal or organic contamination and particles is ammonia hydrogen peroxide (NH ₄ OH: H ₂ O ₂ :
H ₂ O) washing.

However, the conventional semiconductor member is cleaned with a generally used ammonia hydrogen peroxide solution (composition having a volume ratio of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5). Although the treatment removes contamination, the surface unevenness was as flat as 0.2 nm before cleaning, but the surface unevenness was about 0.5 nm or more after cleaning, and the surface was roughened after cleaning.
For example, when a MOS-FET is formed, the dielectric strength of the gate oxide film does not satisfy the design requirements.

On the other hand, as a semiconductor member different from a bulk, a silicon-on-insulator (SOI) type wafer, which is more excellent in the following points, has attracted attention. The reason is that it has the following features.

[0007] 1. 1. Dielectric separation is easy and high integration is possible. 2. Excellent radiation resistance. 3. Higher speed due to reduced stray capacitance. 4. Well step can be omitted. 5. Latch-up can be prevented. 6. A fully depleted field-effect transistor is possible by thinning. The short channel effect can be suppressed even in a fine transistor. An SOI wafer (bonded SOI wafer) formed by bonding a Simox wafer and two Si wafers to the most widely used SOI type semiconductor member There is.

[0008] SIMOX: Separation b
y ion-implanted oxygen) A wafer in which oxygen is implanted into a Si single-crystal semiconductor substrate by ion implantation to form a SiO ₂ layer inside the Si single-crystal semiconductor substrate and a Si single-crystal semiconductor thin layer is provided on the surface. It is. The simox wafer having such a configuration is relatively well used at present in SOI type semiconductor members because of its relatively good compatibility with the Si semiconductor process.

However, in order to form the SiO ₂ layer inside the Si single crystal semiconductor substrate, it is necessary to implant oxygen ions at a rate of 10 ¹⁸ ions / cm ² or more into the Si single crystal semiconductor substrate. However, the productivity is not high industrially, and the wafer cost is high. Furthermore, the Si single crystal semiconductor thin layer provided on the surface has many crystal defects generated in the process of ion implantation. For this reason, SIMOX wafers are, for example, industrially
Essentially, it does not have sufficient crystal quality to produce highly integrated circuits with good yields. In addition, when the above-described cleaning with ammonia hydrogen peroxide is applied to the surface of the SIMOX wafer, the surface irregularities become several nm or more, which is not suitable for forming a highly integrated circuit.

[0010] On the other hand, the bonded SOI wafer means that two Si wafers are prepared, the surface of the first Si wafer is oxidized to form an SiO ₂ layer, and the second wafer is used as the first wafer. After bonding to the surface of the SiO ₂ layer, the free surface of the second wafer is polished to form a Si single crystal thin layer on the SiO ₂ layer. Although the bonded SOI wafer has better crystallinity than the SIMOX wafer described above, it is necessary to strictly control the thickness of the Si single crystal thin layer during polishing. However, at present, it is very difficult to control the layer thickness to several percent or less in the layer thickness distribution over the entire surface of the wafer. Furthermore, when the above-described cleaning with an aqueous solution of ammonia and hydrogen peroxide is applied to the surface of the bonded SOI wafer, the surface of the wafer has a surface unevenness of 0.5 to 0.5 mm.
The surface is roughened to 8 nm, and there is a problem that the excellent characteristics inherent in the SOI type wafer cannot be used.

[0011]

However, conventional semiconductor members are not always sufficient in terms of surface flatness and crystallinity to form a highly integrated and high-speed operable semiconductor device with good mass productivity. . Then, in a method for manufacturing an SOI wafer including a step of forming a single crystal semiconductor layer on a porous silicon layer, it is necessary to form an extremely flat single crystal semiconductor layer.

An object of the present invention is to provide a semiconductor member capable of solving the above problems and forming a high-speed and high-integration integrated circuit at each stage with high productivity in comparison with the related art, and using such a semiconductor member. It is an object to provide a semiconductor device.

[0013]

In order to achieve the above object, a semiconductor member according to the present invention comprises a step of forming a porous silicon layer on a surface of a first substrate; Forming an oxide layer inside, removing the oxide layer formed on the surface of the porous silicon layer, heat treating the porous silicon layer in a hydrogen atmosphere, and forming a single layer on the porous silicon layer. Epitaxially growing a crystalline semiconductor layer, bonding a second substrate to the single crystal semiconductor layer on the first substrate via an insulating layer, bonding the first and second substrates together Removing the first substrate and the porous silicon layer from each other, and transferring the single crystal semiconductor layer over the second substrate.

Then, the removal of the porous silicon layer is performed by:
It is preferable that the etching be performed by selective etching using an etching solution containing HF and H ₂ O ₂ .

Further, the method of manufacturing a semiconductor device includes a step of preparing a semiconductor member manufactured by the method of manufacturing a semiconductor member, and manufacturing a functional element on the single crystal semiconductor layer of the semiconductor member. I do.

[0016]

According to the present invention, a flat single-crystal semiconductor layer can be formed on a porous silicon layer.
Wafers can be manufactured. Further, since the single crystal semiconductor layer has very good crystallinity, a semiconductor device which can operate at a higher speed in each stage and has an extremely high degree of integration can be formed by using this semiconductor member. . Further, in terms of productivity, it can be produced with a high yield, and the effect of mass production can be remarkably exhibited.

FIG. 1 is a schematic sectional view showing a semiconductor member.

In FIG. 1, reference numeral 1 denotes a Si single crystal substrate, the surface of which is usually inclined by 4 ° ± 0.5 ° from the (100) plane.
A so-called 4 ° off substrate is used. The conductivity type is p-type or n-type. On the surface of the substrate 1, an n ⁺ or p ⁺ ion-implanted layer serving as a buried layer in the later formation of a functional element may be provided. Reference numeral 2 denotes a Si epitaxial layer grown on the single crystal substrate 1, and the layer thickness is preferably 0.01
The thickness may be from μm to several tens of μm, and the impurity concentration contained in the layer may be selected according to the form of the device formed on this Si epitaxial layer. The main surface of the single crystal substrate 1 on which at least the Si epitaxial layer 2 is provided is polished using a high-precision polishing technique, and the unevenness of the surface has a center line average roughness Ra defined by JIS standard X “B0601”. It is desirable that the thickness be 0.2 nm or less.

[0019] The semiconductor member shown in FIG. 1, NH ₄ by volume
OH: H ₂ O ₂ : H ₂ O = 1: 1: 5 Ammonia hydrogen peroxide solution (evaluation cleaning solution) for 10 minutes under a cleaning condition of a cleaning temperature of 85 ° C., and ultrapure temperature adjusted to room temperature The center line average roughness Ra of the surface when washed with water (dissolved oxygen content: 40 ppb or less) for 10 minutes is 0.2 nm or less.
The cleaning liquid used in the present invention has a relatively high grade available as an aqueous ammonia hydrogen peroxide cleaning liquid used in the production of recent highly integrated circuit devices for the purpose of obtaining a strict cleaning evaluation. It is desirable to use Among them, for example, as NH ₄ OH, “29 wt% EL +” manufactured by Sankyo Chemical Co., Ltd., and as H ₂ O ₂ ,
Santoku Chemical Co., Ltd. of "30wt% Haigure - do", H ₂
As O, those prepared using ultrapure water (dissolved oxygen amount: 40 ppb or less) are more preferably used.

A semiconductor member having the same structure as the semiconductor member shown in FIG. 1 was manufactured according to the steps described below.

Surface roughness of less than 0.2 nm 4
The off-type n-type 10 ¹⁵ cm ^-3 substrate (S) was mixed with a mixed solution of sulfuric acid H ₂ SO ₄ and hydrogen peroxide solution H ₂ O ₂ (H ₂ SO ₄ : H _{2 in} volume ratio).
O ₂ = 4: 1) (hereinafter referred to as “H ₂ SO ₄ / H ₂ O ₂ mixture”) for 5 minutes, and rinsed with ultrapure water for 5 minutes in the same manner as described above. Next, an oxide film and metal impurities formed on the surface are treated with hydrofluoric acid aqueous solution of hydrogen peroxide (weight ratio of HF: H
₂ O ₂ : H ₂ O = 0.05: 0.1: 9). Thereafter, in order to remove particles, aqueous ammonia hydrogen peroxide (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1 in volume ratio)
1: 5). Thereafter, the substrate is washed with the same ultrapure water as described above, and is further heated under a N ₂ atmosphere in warm ultrapure water (100 ° C.).
(The temperature was adjusted to a predetermined value.), Dried by a spin dryer in an N ₂ atmosphere, and loaded into a reduced pressure CVD apparatus. Next, the inside of the reduced pressure CVD apparatus is set to 10 ^-6 Torr
The pressure was reduced to not more than r, and high-purity hydrogen gas (residual moisture concentration was not more than 10 ppb) was introduced into the apparatus via a catalyst for radicalization. Then, with the substrate (S) heated to 300 ° C., the surface of the substrate (S) is exposed to a hydrogen radical atmosphere for 30 minutes.
Exposure for a minute. Thus, the surface of the substrate (S) was hydrogenated. The heating temperature of the substrate (S) at this time is appropriately selected according to other conditions.
It is desirable that the temperature be set to an arbitrary temperature in the range of 00 ° C.
The degree of the hydrogenation state of the surface of the substrate (S) was determined by leaving the surface of the hydrogenated substrate (S) in the air for one week,
The evaluation was performed by measuring the thickness of the natural oxide film formed on the surface by the S apparatus. The degree of the hydrogenation state of the surface of the substrate (S) whose surface was hydrogenated by the above procedure is that the thickness of the native oxide film on the surface is 0.2 nm or less, and almost no growth of the native oxide film is observed. From this, it is estimated that the surface of the substrate (S) is almost terminated with hydrogen. The reaction gas SiH ₂ Cl ₂ , its flow rate was 1000 SCCM,
Under the conditions of a pressure of 80 Torr and a temperature of 950 ° C., epitaxial growth of Si was performed on the hydrogenated surface of the substrate (S).

As described above, the irregularities on the surface of the Si substrate (S) before the epitaxial growth are controlled to 0.2 nm or less in Ra.
Since the surface of the substrate (S) is terminated with hydrogen and the contaminant does not adhere to the surface of the Si substrate (S), a high-quality Si single crystal is
It was able to grow on the substrate (S) surface.

The semiconductor member manufactured in this manner was replaced with 85
Ammonia hydrogen peroxide solution (NH ₄ OH: H _{2 in} volume ratio)
(O ₂ : H ₂ O = 1: 1: 5) for 10 minutes, washing with ultrapure water at room temperature as described above for 10 minutes, and washing with warm pure water as described above for 10 minutes. According to observation by a scanning tunneling microscope (STM), it was confirmed that the roughness of the surface of the epitaxial layer after the cleaning was 0.2 nm or less in Ra.

Here, in addition to the surface flatness of the Si epitaxial layer, its crystallinity was evaluated by the method described below. That is, the surface of the Si epitaxial layer after the above-described cleaning with the ammonia hydrogen peroxide solution, the room temperature pure water and the warm pure water was subjected to wet oxidation at 1000 ° C. for 4 hours (by oxygen bubbling in water) and the above-described ammonia hydrogen peroxide. Etching was removed by repeated washing with water, and the relationship between the progress of etching and the surface irregularities was examined. The surface irregularities increase with the progress of etching up to an etching depth of about 40 nm, but thereafter approach a substantially constant value. The etched surface of the Si epitaxial layer when the semiconductor member of the present invention was etched away from its main surface to 40 nm had an extremely flat surface roughness Ra of 0.3 nm or less. This indicates that the crystallinity of the epitaxial layer is extremely good.

A semiconductor member having a structure as shown in FIG. 1 having an epitaxial layer formed in this manner is provided with a fine MOS-FET having a gate length of 0.3 μm.
An SRAM device with M integration was formed. At this time, the yield was 70%, and it could be formed with a high yield. The access time of the obtained SRAM device is 5 to 6 nsec.
Thus, a high-speed operation SRAM device was realized. It is presumed that the technical reason is that the interface between the gate insulating layer and the Si epitaxial layer is extremely flat and the interface mobility is as high as that of bulk Si.

[0026]

(Embodiment 1) FIG. 2 shows a schematic cross section of an embodiment of a semiconductor member according to the present invention.

In FIG. 2, reference numeral 11 denotes a substrate whose surface is polished to have a center line average roughness Ra of about 0.2 nm, and a Si substrate or the like can be used. The conductivity type of the Si substrate 11 may be n-type or p-type, and the impurity concentration is usually 10 ¹⁵ to 10 ¹⁶ cm ⁻³ depending on a device formed on a single-crystal Si thin film described later.
Is good. Reference numeral 12 denotes an SiO ₂ layer having a thickness of usually 0.1
However, when a MOS-FET with a high withstand voltage is formed, the thickness may be increased to several μm to several tens μm. 1
3 is a single-crystal Si thin film having a thickness of usually 0.01 to several tens μm.
m. As shown in FIG. 2, the single-crystal Si thin film 13 has a structure in which the end is located inside the ends of the substrate 11 and the SiO ₂ layer 12. The surface of the single-crystal Si thin film 13 is flat, and the center line average roughness Ra after cleaning with the above-described ammonia hydrogen peroxide solution is 0.4 nm or less.

When forming a functional element on the semiconductor member shown in FIG. 2, it is necessary to form an oxide layer such as a gate oxide film.

An oxide film was formed according to the following procedure.

First, after washing in a mixed solution of H ₂ SO ₄ / H ₂ O ₂ for 5 minutes, washing with ultrapure water similar to that described above for 5 minutes, the oxide film formed on the surface and mixed in the oxide film Metal impurities were removed by the same mixed solution of hydrofluoric acid and hydrogen peroxide as described above. Thereafter, aqueous ammonia hydrogen peroxide (by volume ratio, NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 1) for particle removal.
The surface was cleaned using 5). As a result, particles on the surface were almost completely removed. Thereafter, the semiconductor member was washed with room temperature ultrapure water and warm ultrapure water as described above.
At this time, the center line average roughness Ra of the surface of the single crystal Si thin film was 0.4 nm or less. Next, an integrated circuit device of 200,000 gates of a MOS-FET was prepared using the single crystal Si thin film. The gate oxide film of the MOS-FET was formed to a thickness of 100 ° by dry oxidation (1000 ° C.). The electric withstand voltage of the formed oxide film is all MOS-FET
, An excellent performance of 12 MV / cm or more could be realized.

The semiconductor member shown in FIG. 2 was manufactured by the steps shown in FIG.

A p-type first substrate 14 having an impurity concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3 and a platinum electrode are formed by using HF: H ₂ O: C ₂ H _5.
It was immersed in a solution of OH = 1: 1: 1 (volume ratio), and a positive voltage was applied to the former and a negative voltage was applied to the latter to flow a current of 30 mA / cm ² . As a result, the surface of the substrate 14 is
The porous Si layer 15 shown in FIG. The holes in the porous Si layer 15 were extremely fine with a diameter of about several nm, and the interval between the holes was about several tens of nm. Then the solution is H
The solution was changed to a solution of ₂ O: C ₂ H ₅ OH = 1: 1 (volume ratio), a current was applied with the polarity reversed, and hydrofluoric acid taken into the porous layer was extracted. Then, H ₂ SO ₄ : H ₂ O ₂ = 4: 1
(Volume ratio) The mixture was washed for 5 minutes and rinsed with pure water for 10 minutes. Thereafter, the substrate was heated at 400 ° C. in an N ₂ atmosphere, baked in a vacuum, and purged with an inert gas such as N ₂ . Further, heat treatment was performed at 400 ° C. for 30 minutes in an O ₂ atmosphere to fill the inside of the pores of the porous layer with an oxide layer, and an oxide layer was formed on the surface. After heat treatment in O ₂ atmosphere,
The thin oxide film formed on the surface is converted into HF: H ₂ O ₂ : H ₂ O =
The solution was removed with a 0.05: 0.1: 9 (weight ratio) solution and heat-treated at 900 ° C. for 10 minutes in a hydrogen atmosphere. Thereby, the irregularities on the surface of the porous layer 15 were flattened. Instead of heat treatment in a hydrogen atmosphere, hydrogen ECR plasma by heating the substrate (S) to 200 to 400 ° C. (10 mTorr, 200 W) may be irradiated with, also the surface treatment by ultraviolet excitation F ₂ gas diluted with H ₂ You may go. In the latter case, O ₂ : 0.03
Volume% added, H ₂ : 50 volume% dilution F ₂ : 0.5 volume%
When a mixed gas is used, the flattening effect is remarkable.

On the flattened porous layer 15, a molecular beam epitaxial growth method, a bias sputtering method,
By performing the epitaxial growth at a low growth rate (preferably maintaining the epitaxial growth surface at a temperature in the range of 300 to 900 ° C.) by a VD method or the like at a low temperature,
A Si single crystal layer 13 having a thickness of 0.1 to 1 μm is grown on the flattened porous layer 15 (FIG. 3B). In this embodiment, a bias sputtering method is employed. Then, the temperature of the epitaxial growth surface is maintained at 350 ° C., and the Si epitaxial layer 13 is grown on the flattened porous layer 15 in an Ar plasma atmosphere at a base pressure of 10 ⁻¹⁰ Torr and 3 mTorr to produce the semiconductor member (I). Obtained.

The surface unevenness of the Si epitaxial layer 13 thus grown has a center line average roughness Ra of about 0.3 nm.
(Measured by STM and evaluated).

It is assumed that the reason why the surface of the Si epitaxial layer 13 thus grown is extremely flattened is that the surface is epitaxially grown on the porous layer 15 which has been flattened.

In a N ₂ atmosphere, the surface of the semiconductor member (I) shown in FIG. 3B is washed with ammonia hydrogen peroxide solution and ultrapure water at room temperature in the same manner as described above, and then washed with ultrapure water in the same manner as described above. Washing with water (washing time 500-600 seconds). This terminates the surface of the Si epitaxial layer 13 with hydrogen,
The surface is chemically stable and has improved resistance to contamination from other impurities.

Next, as shown in FIG. 3C, the second S
A thermal oxide layer 12 (layer thickness: 500 nm) was formed on the surface of the i-substrate 11 to obtain a semiconductor member (II). Semiconductor member (II)
Together with the semiconductor member (I) shown in FIG. 3B was put into an N ₂ atmosphere in a bonding apparatus.

In this state, as shown in FIG. 3D, the thermal oxide layer 12 was brought into contact with the surface of the epitaxial layer 13 and heated to about 800 to 900 ° C. By this process,
Both stably bound. Further, the diffusion of the p-type impurity, for example, boron contained in the porous layer 15 into the epitaxial layer 13 by the heat treatment at such a low temperature could be prevented.

Next, as shown in FIG. 3E, the Si substrate 14 was removed by a back grinder leaving only a few to several tens of μm. The remaining Si layer 14 was etched with hydrofluoric nitric acid. At this time, the side surfaces of the epitaxial Si layer 13 were removed by etching, but the porous layer 15 was not etched by the hydrofluoric / nitric acid solution.

The selective etching method for electrolessly wet-etching only the porous Si layer 15 will be described.

An etching solution having no etching effect on crystalline Si and capable of selectively etching only porous Si includes buffered solutions such as hydrofluoric acid, ammonium fluoride (NH ₄ F) and hydrogen fluoride (HF). A mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which hydrofluoric acid and aqueous hydrogen peroxide has been added, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which alcohol has been added, or an aqueous hydrofluoric acid or buffer having an addition of hydrogen peroxide and alcohol A mixture of difluoric acid is preferably used. The bonded substrates were wetted with these solutions for etching. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding the hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case without addition. Further, by changing the ratio of the hydrogen peroxide solution, the reaction rate can be increased. Could be controlled. In addition, by adding alcohol, bubbles of the reaction product gas can be instantaneously removed from the etching surface without stirring, and the porous Si can be etched uniformly and efficiently.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, and still more preferably 1 to 70% by weight with respect to the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, and still more preferably 5 to 80% by weight based on the etching solution.

The HF concentration is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, and still more preferably 5 to 80% by weight, based on the etching solution.

The concentration of H ₂ O ₂ is preferably from 1 to 95% by weight, more preferably from 5 to 90% by weight, still more preferably from 10 to 80% by weight, based on the etching solution. It is set within the range that produces the effect.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight with respect to the etching solution.
Hereinafter, it is more preferably 40% by weight or less, and is set within a range in which the effect of the alcohol is exerted.

The temperature is set in the range of preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and still more preferably 5 to 60 ° C.

The alcohol used in this step is not limited to ethyl alcohol, and may be any alcohol such as isopropyl alcohol which can be practically used in the production step and the like, and which can provide the above-mentioned effect of adding alcohol.

The semiconductor member (III) having the structure shown in FIG. 3 (f) obtained as described above has a single-crystal Si layer equivalent to that of a normal Si wafer which is flattened and uniformly thinned. 11 is formed over a large area.

The semiconductor member (III) shown in FIG. 3 (f) having undergone the etching step of the porous layer 15 described above.
Has substantially the same configuration as that shown in FIG. As shown in FIG. 3E, the peripheral portion of the semiconductor member is slightly thinner, so that the epitaxial layer 13 and the S
The iO ₂ layer 12 is not bonded around the semiconductor member.
For this reason, as shown in FIG. 3F, the structure is such that the epitaxial layer 13 is formed slightly inside the edge of the semiconductor member.

According to the scanning tunneling microscope (STM), the surface of the Si epitaxial layer 13 when the Si epitaxial layer 13 was washed with the above-described ammonia hydrogen peroxide solution had a center line average roughness R
a was as flat as 0.3 nm or less. Further, by repeating the wet oxidation and the washing with the ammonia hydrogen peroxide solution, the Ra after the etching removal by 40 nm is also set to 0.1.
It was 3 nm or less, and it was confirmed that the crystallinity of the epitaxial layer was good.

As described above, since the Si epitaxial layer 13 on the SiO ₂ layer 12 has lower crystal defects and impurity contamination than a normal wafer, the device performance can be improved.

(Embodiment 2) FIG. 4 schematically shows a cross section of a second embodiment of the present invention.

This embodiment differs from the embodiment shown in FIG. 2 in that a single-crystal Si thin film 13 is connected via an SiO ₂ layer 17 to an insulating layer 12 formed on the other Si substrate 11. It is. With this configuration, the interface between the Si layer 13 and the SiO ₂ layer 12, which is the active layer of the device, is not a bonded portion, and the interface level there can be reduced as compared with the first embodiment. Is advantageous in that the leakage current can be reduced.

Therefore, a method of fabricating this structure will be briefly described below. The wafer having reached the step shown in FIG. 3B is immersed in a platinum hydrogen peroxide solution Pt-H ₂ O ₂ . By this process, a thin oxide film of about 10Å is formed on the wafer surface. Next, the wafer is heated to 500 ° C. in an N ₂ atmosphere to increase the density of the thin oxide film. By this processing, 5
At a low temperature of 00 ° C., a high-quality oxide film 17 having extremely uniform thickness is formed. Since the temperature required for this oxidation is low, there is no boron diffusion from the porous layer and no influence on the device. Further, since the oxide film thickness is as thin as ten and several Å, there is no problem in film warpage due to oxidation and the like, and there is no problem in bonding.

The surface roughness after cleaning with ammonia hydrogen peroxide solution and the surface roughness after etching removal by 40 nm are the same as in Examples 1 and 2.

(Embodiment 3) FIG. 5 is a schematic sectional view of a third embodiment of the present invention. The difference from the embodiment shown in FIG. 2 is that the insulating layer provided on the surface of the substrate 11 is not necessarily a thermal oxide film. In FIG. 5, 18 is a BPSG (boron phosphorus doped glass), and 19 is a SiO _x N _{1 -x} film. By providing a layer made of a material having better reflow characteristics than SiO ₂ at the bonding interface, there is an advantage that bonding becomes more complete and uniformity is improved.

In this embodiment, the combination of BPSG and SiON film has been described.
NSG (non-doped glass) and PSG formed by CVD having better reflow characteristics than the film may be provided alone.
In addition to ON, AlN, SiN, etc., or a combination thereof can be used.

[0058] (Example 4) The entire process of each example low carbon Ar, and being an inert gas atmosphere such as N _2, ionizes the atmosphere was irradiated with ultraviolet rays to the gas, caused by the flow of gas A semiconductor member was manufactured while eliminating static electricity on the wafer. Normally, when N ₂ gas is flowed by a down flow, the wafer is easily charged to several to several tens kV. For this reason, when bonding the wafers, not only the bonding becomes non-uniform, but also when the wafers are charged, particles adhere to the wafers to generate microvoids and the like.

However, this problem was solved by preventing the wafer from being charged as described above, and the yield of wafer production was improved. It is needless to say that not all the steps are performed in an inert gas atmosphere, but only some important steps (for example, a bonding step) may be performed in an ionized inert gas.

(Embodiment 5) Next, a fifth embodiment of the present invention will be described. In the first embodiment, the surface of the Si epitaxial layer was terminated and bonded with hydrogen by cleaning in warm pure water. However, in this embodiment, the Si surface was exposed to a hydrogen radical atmosphere, and a natural oxide film or metal formed on the surface was exposed. While removing the impurities and the like, the Si surface is activated and bonded to the SiO ₂ layer which is the other wafer surface. To perform this hydrogen radical treatment, a catalyst may be placed at the hydrogen gas supply port and hydrogen gas may be passed through. Also, S
In the case where i-epitaxial growth is performed by a bias sputtering apparatus, even if bonding with the other wafer is performed continuously with Si growth in the sputtering chamber, the surface is slightly oxidized by further introducing O ₂ gas into the sputtering chamber. Therefore, they may be similarly bonded in the sputtering chamber. that's all,
As described, Si and SiO ₂ in a hydrogen radical atmosphere
By bonding the layers, the bonding temperature was lowered more than before, and the problems of boron doping and thermal distortion from the porous layer could be solved.

Example 6 n having an impurity concentration of 10 ¹⁵ cm ⁻³
An 8500 ° thick SiO ₂ layer is formed on a mold substrate, and a 0.5 μm-thick single-crystal Si thin film is formed on the SiO ₂ layer.
A CMOS SRAM was prototyped under the following conditions. CMOS
Has a gate length of 0.3 μm and an integration degree of 16 Mbits. First, LOCOS for element isolation was formed. LOCO
The thickness of S is set so that element isolation can be performed completely with an insulating layer.
It was set to 10,000 °. Thereafter, ion implantation for p-well formation is performed at a dose of 1 × 10 ¹² cm ⁻² , an acceleration voltage of 80 keV, and n.
Well formation ion implantation was performed at a dose of 5 × 10 ¹¹ cm ⁻² and an acceleration voltage of 100 keV, and the substrate was activated by heating at 1150 ° C. for 2 hours. The surface of this Si single crystal is H ₂ SO ₄ + H ₂
O ₂ washing, water washing, and aqueous ammonia hydrogen peroxide (NH ₄ O
H: H ₂ O ₂ : H ₂ O = 0.1: 1: 5), and then again with room temperature water and warm pure water, and then dry oxidation at 1000 ° C. in a gate oxidation furnace to a thickness of 150 ° oxide film. Was formed. After poly Si serving as a gate is formed by CVD, source / drain ion implantation for nMOS is performed at 7 × 10 4.
^{At a} dose of ¹⁵ cm ^-2 and an acceleration voltage of 100 keV, a source / drain ion implantation for pMOS is performed at a dose of 2 × 10 ¹⁵ cm ^-2 ,
Annealing was performed at 35 keV for 5 minutes at 1000 ° C.
Further, BPSG was formed as an interlayer insulating layer, contact holes were patterned, and Al-Si-Cu for wiring was formed by sputtering. After patterning, a chip was formed by forming SiN as a passivation film.

When 1000 chips were prototyped, there was no failure mode due to the withstand voltage failure of the gate oxide film, and good gate withstand voltage characteristics were obtained. In addition, a high-speed operation with an access time of 3 to 4 ns was confirmed by realizing the low parasitic capacitance structure of the SOI device and the high mobility of the transistor.

[0063]

As described above, according to the present invention,
In a semiconductor member, the single crystal layer of a single crystal layer on which an integrated circuit is to be formed has very good crystallinity. Therefore, a high-speed and high-integration semiconductor device can be formed using this semiconductor member.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor member.

FIG. 2 is a schematic sectional view showing a first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing method according to the example of the first embodiment;

FIG. 4 is a schematic sectional view showing a second embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a third embodiment of the present invention.

[Explanation of symbols]

 1,11,14 Substrate 2,13 Epitaxial single crystal layer 12,17,18,19 Insulating layer 15 Porous layer 16 Single crystal silicon

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/11

Claims (3)

[Claims] A step of forming a porous silicon layer on the surface of the first substrate; a step of forming an oxide layer on the surface of the porous silicon layer and inside the pores; A step of removing the formed oxide layer; a step of heat-treating the porous silicon layer in a hydrogen atmosphere; a step of epitaxially growing a single crystal semiconductor layer on the porous silicon layer; Bonding a second substrate to the single crystal semiconductor layer with an insulating layer interposed therebetween; and forming the first substrate from the bonded first and second substrates.
Removing the substrate and the porous silicon layer, and transferring the single crystal semiconductor layer onto the second substrate. 2. The method according to claim 1, wherein the removing of the porous silicon layer is performed by using HF,
The process according to claim 1, wherein the semiconductor member which by selective etching using an etching solution containing H ₂ O _2. 3. A method of manufacturing a semiconductor device, comprising: preparing a semiconductor member manufactured by the method of manufacturing a semiconductor member according to claim 1; and manufacturing a functional element on the single crystal semiconductor layer of the semiconductor member. And a method for manufacturing a semiconductor device.