JP3472171B2 - Semiconductor substrate etching method and etching apparatus, and semiconductor substrate manufacturing method using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a semiconductor substrate, an etching apparatus and a method for manufacturing a semiconductor substrate, and more particularly, a method for etching a semiconductor substrate having a silicon film, an etching apparatus and a semiconductor substrate. The manufacturing method of.

[0002]

2. Description of the Related Art In silicon-based semiconductor devices and integrated circuit technology, a semiconductor-on-insulator (SOI) structure, that is, a device using a single crystal semiconductor film on an insulating film is excellent in reducing parasitic capacitance and radiation resistance. As a technology that brings about higher cost of transistors, lower voltage, lower power consumption, higher integration, and reduction of total cost including simplification of processes such as omission of well process by facilitating element isolation Many studies have been made so far.

As a substrate having an SOI structure (SOI substrate), after SOS (silicon on sapphire) or Si single crystal substrate is surface-oxidized, a window is opened to partially expose the Si substrate, and the portion is used as a seed. A substrate in which a Si single crystal film (layer) is formed on SiO ₂ by lateral epitaxial growth, a Si single crystal substrate itself is used as an active layer, and a silicon oxide film is formed under the substrate, a thick polycrystalline Si layer. A substrate having a Si single crystal region surrounded by a V groove and dielectrically separated, a FIPOS method (Full is)
lation by porous Silico
S) by dielectric separation by oxidation of porous Si according to
An OI substrate or the like.

Recently, as a technique for forming SOI, an oxygen implantation method (SIMOX: Separation by I) is used.
(Planted Oxygen) and a wafer bonding method have become mainstream. SIMOX was reported in 1978 (K. Izumi, M. Doken, and.
H. Arioshi, Electron. Lett.
14 (1978) p. 593). In this method, oxygen is ion-implanted into a silicon substrate and then heat-treated at a high temperature to form a buried silicon oxide film.

In the SOI formation by the bonding method, there are many variations in the method of thinning one wafer after bonding.

(BPSOI) The most basic technique uses polishing. A silicon oxide layer is formed on the surface of both or one of the two wafers and then bonded. After that, one of the wafers is thinned by grinding and polishing.

Plasma has been developed in order to improve the film thickness uniformity of the SOI layer obtained by (PACE) polishing.
assisted chemical etch
g method (PACE) method. The film thickness is measured in advance at a high density measurement point of several thousand points on the wafer. Next, a plasma source having a diameter of several mm is scanned at a scanning speed corresponding to the film thickness distribution, and the etching amount is changed in accordance with the film thickness distribution, thereby improving the film thickness distribution.

(Hydrogen injection stripping method) Recently, (M. Brue
l, Electronics Letters, 31
(1995) p. 1201) Japanese Unexamined Patent Publication No. 5-211128, USP 5,374,564 with a novel bonding S
Reported OI. In this method, an ion-implanted wafer is bonded to the entire surface of a wafer previously oxidized with a light element such as hydrogen or an inert gas, and heat-treated. Then, the wafer is peeled off at the depth to which ions are implanted during the heat treatment. As a result, the layer above the projection range of the ion implantation is transferred onto the other wafer, and the SOI structure is formed.

(Epitaxial Layer Transfer Method) Japanese Patent No. 260
No. 8351, USP 5,371,037 discloses an excellent SOI in which a single crystal layer on a porous layer is transferred onto another substrate.
Substrate fabrication methods have been proposed.

This method is called "ELTRAN (registered trademark)".
Also called. (T. Yonehara, K. Sak
aguchi, N .; Sato, Appl, Phys. L
ett. 64 (1994), p. 2108) In the field of such an SOI substrate, the surface roughness introduced by etching, ion implantation, and heat treatment subsequent to ion implantation is removed to smooth the surface and to diffuse into a single crystal layer. The formation of an SOI layer made of a silicon film having a low boron concentration by removing the high concentration boron is an issue for improving the device characteristics such as the withstand voltage of the gate oxide film of MOSFET and the improvement of carrier mobility, which is overcome. A method of doing so has been proposed for each SOI substrate fabrication method.

In the hydrogen implantation delamination method, the surface after the wafer is separated by the projected range of ions has a root mean square roughness (Rrms).
The surface layer has a roughness of 10 nm, and the surface layer has an ion implantation damage. By polishing called touch polishing, the surface layer is slightly removed to smooth and remove the implantation damage layer (M. Bruel, et. al. Proc. 19
95 IEEE Int. SOI Conf. (199
5) p. 178).

In the case of the PACE method, the surface roughness of 10.66 nm in the peak-to-valley of the surface immediately after plasma etching is measured by an atomic force microscope. This roughness is smoothed up to 0.62 nm, which is equivalent to the original surface, by a minute amount of polishing called touch polish. (T. Feng, M. Matloubian,
G. J. Gardopee, and D.M. P. Math
ur, Proc. 1994 IEEE Int. SOI
Conf. (1994) p. 77. ).

In the BESOI method, in order to remove the surface roughness of about 5-7 nm in the peak-to-valley generated after etching, it is necessary to remove 3 to 5 times the thickness, that is, 20-30 nm. As a result of this polishing, the average film thickness uniformity is 0.005 μm (= 5 n
m), the uniformity deteriorates.

That is, touch polish or kiss
Even in a minute amount of polishing called polish,
At the same time as the surface roughness is removed, the film thickness is always reduced, and as a result, the film thickness uniformity may be deteriorated.
The end of polishing is generally controlled by time, but even with the same polishing time, in-plane depending on the polishing liquid, the temperature of the surface plate during polishing, and the degree of deterioration of the polishing cloth,
It is known that the polishing amount varies between surfaces and batches, and it is extremely difficult to control the polishing amount constant. In particular, it is known that the polishing amount on the outer periphery of the wafer increases.

Further, when boron is diffused at a high concentration in the entire thickness direction of the SOI layer, the concentration cannot be lowered by polishing.

The surface roughness of the SOI layer formed by the SIMOX method using oxygen ion implantation is about one digit larger than that of the bulk. S. Nakashima, K .; Izu
mi (J. Mater. Res. (1990) Vol.
5, No. 9, p. 1918) according to 1260 ℃
It has been reported that the heat treatment of 2 hours (in nitrogen) or 1300 ° C. (0.5% oxygen containing argon) for 4 hours eliminates the roughness of the SIMOX substrate in which dents with a diameter of several tens nm are numerous. On the other hand, the heat treatment at 1150 ° C. does not change the surface roughness. However, in such a high temperature heat treatment exceeding 1200 ° C., it is difficult to use the quartz tube in terms of heat resistance. Also, the high temperature process makes the introduction of slip lines more serious as the wafer size increases.

Further, in the oxygen implantation method, boron contained in the air in the clean room adheres to the substrate surface,
Moreover, the oxygen may be simultaneously implanted at the time of implanting oxygen, or the boron attached before the high temperature heat treatment for converting the ion-implanted oxygen into the buried silicon oxide layer may diffuse into the entire silicon layer by the heat treatment. Boron contained in the air in the clean room may cause the same problem in the bonded SOI.

Japanese Unexamined Patent Publication No. 5-218053 and Japanese Unexamined Patent Publication No.
In Japanese Patent Laid-Open No. 217821, the present inventors propose that the surface of the SOI substrate is smoothed by performing a heat treatment in an atmosphere containing hydrogen.

Even if a rough surface unevenness is present as compared with a commercially available polished silicon wafer such as the surface of an SOI substrate after etching, it is smoothed by hydrogen annealing and the surface of the commercially available silicon wafer (polished The surface is improved). Simultaneously, the substrate having the single crystal silicon film formed on the insulator on the surface is annealed in hydrogen, so that the boron in the single crystal silicon film is diffused outward into the gas phase and the boron in the single crystal silicon film is diffused. The concentration is lowered. The diffusion rate of boron in silicon is relatively fast,
During heat treatment in an oxidizing atmosphere or in an inert gas, the diffusion rate of boron in a silicon oxide layer such as a natural oxide film formed on the surface is small, so that boron is not confined in the silicon layer. Up to. However, by annealing in a reducing atmosphere containing hydrogen or the like, the silicon oxide film on the surface of the SOI layer, which is the diffusion barrier, can be removed and the reformation of the oxide film in the process can be suppressed. Outward diffusion is promoted, and SOI
Even when high-concentration boron is present in the entire layer, the impurity concentration in the entire SOI layer can be reduced to a level at which device fabrication can be performed by outward diffusion (N. Sato a.
nd T.N. Yonehara, Appl. Phys. L
ett. 65 (1994) p. 1924).

The heat treatment in an atmosphere containing hydrogen is an extremely effective method for realizing the out-diffusion of boron in the silicon layer and smoothing the large roughness of the silicon surface.

It has been reported in the above-mentioned paper that the heat treatment in an atmosphere containing hydrogen is also suitable for the SOI substrate by SIMOX method, and the roughness can be smoothed by the heat treatment at 1200 ° C. or less in the hydrogen atmosphere.

When the SOI substrate is annealed by hydrogen, the reduction rate of the film thickness is 0.08 nm / m at 1150 ° C.
In comparison with polishing, it is extremely small.

On the other hand, when hydrogen annealing is performed on the bulk Si wafer instead of the SOI substrate, L.S. Zhong et
al. Appl. Phys. Lett. 68 (199
6) p. 1229 has about 0.1 at 1200 ° C.
A reduction rate as small as nm / min has been reported.

However, B. M. Gallois et
al. J. Am. Ceram. Soc. , 77 (199
4) pp. 2949 includes 10 nm / min to 100 n
A relatively large reduction rate of m / min has been reported.

[0025]

If the reduction rate and the etching amount cannot be controlled, the film thickness uniformity in the wafer surface after heat treatment and between a plurality of wafers tends to deteriorate.

The variation in the film thickness of the SOI layer on the SOI substrate is caused by the device characteristics, particularly the complete depletion type SOI-MOS.
Since the characteristics such as the threshold voltage of the transistor are greatly influenced, it is extremely important to control the film thickness within the wafer and between the wafers with high accuracy.

In addition to the above-mentioned film thickness uniformity, there are some requirements for SOI substrates.

The required film thickness of the SOI layer varies depending on the characteristics of various semiconductor devices manufactured using the SOI substrate. Therefore, it is conceivable to thermally oxidize the surface of the obtained SOI layer and then wet-etch the formed thermal oxide film with hydrofluoric acid (sacrificial oxidation).
The manufacturing process becomes complicated.

Further, as seen in the hydrogen injection peeling method and the like,
Since the outermost layer of the obtained SOI layer is likely to contain a relatively large number of defects, it is also important to reduce these defects.

[Object of the Invention] An object of the present invention is to easily control the etching amount and to always perform uniform etching even when a plurality of substrates are processed, an etching apparatus, and a method for manufacturing a semiconductor substrate. To provide.

Another object of the present invention is to provide an etching method, an etching apparatus and a method for manufacturing a semiconductor substrate which can efficiently reduce impurities such as boron contained in the film while maintaining the film thickness uniformity. To do.

Still another object of the present invention is to provide an etching method, an etching apparatus and a method for manufacturing a semiconductor substrate, which can reduce the characteristic variations of devices manufactured using the semiconductor substrate.

Still another object of the present invention is to provide a low-cost etching method, etching apparatus, and semiconductor substrate manufacturing method that does not require sacrificial oxidation to easily obtain an arbitrary film thickness and has few surface defects. To provide.

[0034]

The etching method of the present invention is an etching method for etching a semiconductor substrate having a surface made of silicon, in which the surface made of silicon is provided on the surface made of silicon oxide. The method is characterized by including a step of heat-treating the surface made of silicon in a reducing atmosphere containing hydrogen in a state of being opposed to each other at a predetermined interval.

The method for producing a semiconductor substrate of the present invention is 2
The method is characterized by including a step of adhering two base materials, removing an unnecessary portion of one base material, and etching the obtained surface made of silicon by the above-mentioned etching method.

[0036]

1 is a schematic diagram showing an etching apparatus according to a preferred embodiment of the present invention.

This etching apparatus is an exhaustable reaction furnace 1 which constitutes an etching chamber for accommodating a semiconductor substrate W.
And a heater 2 for heating the gas in the substrate W and the furnace 1.
And a hydrogen gas source 5 via at least one valve 6 and an exhaust pump 8 via at least one valve 7.

On the side of the surface to be processed of the base material W, the facing surface constituting member 3 having the silicon oxide 4 on the surface is arranged at a predetermined distance AS from the base material W. Reference numeral 9 is a support that supports the base material W and the facing surface constituting member 3.

The etching method according to the present embodiment is as follows.

First, the base material W and the facing surface constituting member 3 are housed in the reaction furnace 1, and the inside of the furnace is evacuated by the exhaust pump 8 to reduce the pressure. Then, heating is performed by the heater 2.

Next, hydrogen gas is introduced from the gas source 5 into the furnace. The amount of heat generated by the heater 2 is controlled to maintain the temperature inside the furnace and the temperature of the substrate W at a predetermined temperature.

Then, the silicon on the surface of the substrate W (the surface to be processed) is etched.

As the substrate W to be etched according to the present invention, a bulk Si wafer produced by the CZ method or the like, an epitaxial Si having an epitaxially grown layer are used.
Wafer, bulk Si wafer is hydrogen annealed Si
Examples thereof include wafers, the above-described various SOI wafers, substrates having a silicon film, and the like, and in particular, wafers that have been subjected to some surface treatment after polishing to have irregularities on the surface,
A suitable base material is a wafer having an unpolished surface, an SOI wafer in the middle of a manufacturing process by a bonding method or a SIMOX method, and the like. In the present invention, since the substrate W is heat-treated in a reducing atmosphere containing hydrogen, the gas supplied to the furnace is 100% hydrogen gas, 1 to 99% hydrogen with an inert gas such as a rare gas. Hydrogen gas or the like diluted to an appropriate degree is used. In particular, it is advisable to introduce a gas of relatively high purity through a hydrogen purifier into a furnace that has been sufficiently dehydrated so that the dew point of the reducing atmosphere containing hydrogen is −92 ° C. or lower.

Residual oxygen and moisture in the atmosphere oxidize the silicon surface at the time of temperature rise to form a coating and hinder the smoothing of the surface. Further, at high temperatures, the oxidation and etching actions cause an unexpected decrease in the silicon film thickness, so it is also necessary to suppress it to a low level. Therefore, it is desirable to control the atmosphere so that the dew point is −92 ° C. or lower as described above.

The pressure of the reducing atmosphere containing hydrogen is
Atmospheric pressure may be any of increased pressure, atmospheric pressure, and reduced pressure, but atmospheric pressure or lower is preferable.

In order to improve the surface smoothing effect and the outward diffusion effect of impurities, it is preferable that the pressure is low.

When an etching furnace made of quartz glass such as fused quartz is used, in order to prevent deformation of the furnace,
The lower limit of the pressure is more than 3.9 × 10 ⁴ Pa, preferably 6.6.
More preferably, it is set to × 10 ⁴ Pa.

Considering the above points, atmospheric pressure to 1.3
It would be rational to select from the range of Pa according to the usage environment.

The flow rate of the gas containing hydrogen used in the present invention is not particularly limited. However, it is more preferable to obtain the flow rate described below.

The flow velocity means the velocity of gas passing through the region excluding the cross-sectional area of the semiconductor substrate from the cross-sectional area of the core tube.

If the flow rate is too fast, the reaction product is removed from the surface of the substrate at a high rate, and the effect of suppressing etching is reduced. On the other hand, if the flow rate is too slow, the removal of the reaction product is significantly reduced, and the ability of removing impurities such as boron in the semiconductor single crystal layer by outward diffusion is reduced.

In the present invention, the flow rate is 10 cc / min.
-Cm ^{2 to} 300 cc / min-cm ² more preferably 30 cc / min-cm ^{2 to} 150 cc / min-cm
² . The flow rate is a parameter that controls the rate at which the reaction product on the surface of the substrate diffuses to the side of the substrate and is removed.

In an atmosphere containing hydrogen, a nitrogen atmosphere or
1200 in which the surface does not become smooth in a rare gas atmosphere
Even at a temperature of not higher than 0 ° C, the surface is sufficiently smoothed with etching. The temperature at the time of etching having a smoothing effect according to the present invention depends on the composition of gas, pressure and the like. Specifically, the lower limit of the temperature is about 300 ° C. or higher, more preferably 500 ° C. or higher, and further preferably 800 ° C. or higher. The lower limit of the temperature is not higher than the melting point of Si, but 1200 ° C. or lower is particularly effective. Further, when the smoothing progresses slowly, a smooth surface can be similarly obtained by extending the heat treatment time. The influence of the constituent material of the facing surface can improve the efficiency of etching due to the interaction with the facing surface even if the spacing is the same by lowering the pressure. This is because the diffusion length of gas molecules becomes longer as the pressure decreases.

The facing surface constituting member 3 used in the present invention may be any as long as silicon oxide is formed on at least the facing surface side, but a Si wafer having a silicon oxide film formed on its surface is preferable. If it is a quartz wafer or the like and has a silicon oxide film on the opposite surface side, it is also preferable to use a wafer having the same structure as the substrate to be etched.

The opposing surface should be a plane and parallel to the surface to be processed. The size and shape of the facing surface are preferably the same as or larger than the surface to be processed of the base material W, and those having substantially the same shape as the base material are preferably used.

Further, it is also preferable that the opposing surface constituting member is also used as a holding member for the base material such as a tray.

The distance between the facing surface and the base material, that is, the distance AS depends on the size of the surface (etching surface) made of silicon of the semiconductor base material. When it is 20 mm or less, and more preferably 10 mm or less, the effect of enhancing the etching by the interaction with the facing surface material can be obtained. The lower limit of the distance is not particularly limited, but is preferably 1 mm or more, more preferably 3 mm or more.

This phenomenon begins to progress by heat treatment with the surface being clean. Therefore, when a thick natural oxide film is formed on the surface of the base material, this is preceded by the heat treatment. By removing by etching with dilute hydrofluoric acid or the like, the start point of the surface smoothing is advanced.

The smooth silicon surface thus obtained is
It can be preferably used from the viewpoint of manufacturing a semiconductor device.

A table of members made of silicon or SiC
Face the silicon oxide film formed on the surface to the substrate
When the etching is performed, the silicon oxide film is
When the film thickness is reduced by
Is reduced to about 1/10. By utilizing this phenomenon,
Silicon that you want to remove by etching the thickness of the silicon oxide film
Contains the same number of Si atoms as the amount of Si atoms contained in the thickness
If the thickness is set so that the amount of Si removed can be reproducibly
You can control. The silicon oxide film on the opposite surface is
Stoichiometric SiO formed₂ In the case of a film, oxidized silicon
Con thickness (t _ox) Of the silicon film thickness
It is preferable to use the facing component member set to 2.22 times.

Further, when considering the margin of the processing time, at least the thickness t _ox is set to 2.22 times or more the thickness of the silicon film to be removed.

In the present invention, the etching rate of the silicon film is 1.0 × 10 ⁻³ nm / min to 1.0 nm / min.
It can be easily controlled within the range of min, but considering the processing efficiency, the temperature is kept at a relatively high temperature of 1080 ° C or higher and 0.04
It is preferable to perform etching at a rate of 6 nm / min or higher, or to keep the temperature at 1100 ° C. or higher and perform etching at a rate of 0.11 nm / min or higher.

If the surface of the silicon film is etched by about 10 nm to 200 nm by this etching, surface defects and the like can be sufficiently reduced. Especially in the case of SOI substrate,
According to the present invention, a silicon film having a thickness of 50 nm to 500 nm is etched to obtain an SO having a thickness of 20 nm to 250 nm.
It becomes easy to obtain the I layer.

Although HF defects tend to increase with sacrificial oxidation, the present invention can suppress such increase in defects.

The Rrms of the surface obtained, for example, in a 1 μm square area is at least 0.4 nm or less, preferably 0.2 nm or less, and more preferably 0.15 nm or less.

The method of introducing gas is not limited to the method shown in FIG. 1, and it is preferable to adopt various modes described later.

Although SiC may be used as the constituent material of the reaction furnace 1, quartz glass is more preferably used.

As the heater 2, a resistance heater, a high frequency heater or a lamp is used.

Here, the knowledge that motivates the present invention will be described.

(Knowledge Regarding Difference in Etching Amount Due to Opposing Material) The inventors of the present invention have examined the conditions of heat treatment in a reducing atmosphere containing hydrogen capable of removing minute roughness on the surface of a silicon single crystal. It has been discovered that the etching rate of crystalline silicon varies greatly depending on the material of the surface (opposing surface) facing the surface of the single crystal silicon.

FIG. 2 is a diagram showing the temperature dependence of the etching rate depending on the material of the facing surface, and the horizontal axis on the lower side shows the reciprocal of the temperature T. The horizontal axis on the upper side represents the temperature corresponding to 1 / T. The vertical axis shows the etching rate (nm / min)
Is a logarithmic plot. When an SOI substrate is used, an SOI layer can be relatively easily
That is, the film thickness of the single crystal silicon layer on the embedded insulating film can be measured. The etching rate can be obtained by changing the heat treatment time, measuring the amount of change in the film thickness before and after the heat treatment, and determining the slope with respect to the etching time.

In the figure, data A indicates the etching rate at each temperature with the SiO ₂ base material facing the Si facing surface. At this time, the activation energy was calculated from the slope of the approximate straight line by the least square method of these plots. When E _a was determined, it was about 4.3 eV.

Data B shows the case where the Si substrate is heat-treated while facing the SiO ₂ facing surface.

Data C shows the case where the Si base material was heat-treated with the Si facing surface facing the Si facing surface, and the activation energy E _a was about 4.1 eV.

Data D shows that the SiO ₂ base material is SiO ₂
This was the case where the heat treatment was performed so as to face the facing surface, and at this time, the activation energy E _a was about 5.9 eV.

As shown in FIG. 2, in the heat treatment in a hydrogen atmosphere, the etching rate of silicon is as shown by the difference between the etching rates of B and C in the figure by changing the material of the facing surface from silicon to silicon oxide. , It became clear that the speed was increased about 9 times regardless of the temperature.

When single crystal silicon faces each other, the etching rate is about 0.045 nm at 1200 ° C.
/ Min or less (C in the figure). The etching amount in the heat treatment for 60 minutes is 3 nm or less. On the other hand, when the opposing surface of silicon is made of silicon oxide, the etching rate is about 0.36 nm / min at 1200 ° C. (B in the figure), and the etching amount per hour reaches 21.6 nm. This etching amount is close to the amount removed by touch polishing.

FIG. 3 is a diagram showing the etching amount when Si and SiO ₂ face each other, the horizontal axis is the etching time (minutes), the vertical axis is the etching thickness (nm), and the temperature T is 1200. The white circle indicates that the SiO ₂ base material is Si.
This is the case where the heat treatment is performed so as to face the facing surface, and the black circles indicate S.
The case where the i base material is heat-treated while facing the SiO ₂ facing surface is shown.

As shown in FIG. 3, at the same time, when the SiO ₂ base material shown by the white circle is opposed to the Si facing surface and heat-treated, the Si base material shown by the black circle is opposed to the SiO ₂ facing surface. The etching amount is larger than that in the case of etching by etching. That is, when heat treatment is performed with SiO ₂ and Si facing each other, SiO ₂ is removed by etching thicker.

FIG. 4 shows SiO with the opposite surface made of Si.₂ D
And the opposite surface is SiO₂ Etching of Si
At Si surface and SiO₂ Each face is etched
Fig. 3 shows the number of Si atoms removed by
Calculated and illustrated, the horizontal axis is during etching
Meanwhile, the vertical axis represents the number of removed Si atoms (atoms / cm
² ), White circles, triangles, and squares are SiO.₂ 
A black circle, a triangle, or a square indicates a Si surface.

As shown in FIG. 4, when the etching amounts of the silicon oxide surface and the single crystal silicon surface shown in FIG. 3 were converted into the number of silicon atoms, the results were almost the same as shown in FIG. . It was found that, when Si and SiO ₂ were opposed to each other and heat treated, almost the same amount of Si atoms was lost from both surfaces.

That is, the etching rate of silicon is accelerated by the interaction with the facing silicon oxide surface, and the reaction formula is generally as follows, and silicon and silicon oxide react 1: 1.

Si + SiO ₂ → 2SiO Further, the etching rate of such Si is affected by the distance from the facing surface. When silicon is arranged on the facing surface, the etching rate is suppressed more as the distance between the surfaces is reduced. On the contrary, when the silicon oxide is arranged as the facing surface, it is found that the etching rate is increased as the surface distance is decreased.

Further, reduction represented by hydrogen is used as the atmospheric gas.
Etching rate without hydrogen gas contains hydrogen
It was significantly smaller than the case. That is, such speedup
The presence of a reducing gas typified by hydrogen contributes to etching.
I am giving. When silicon and silicon oxide face each other,
Etching is a process in which either surface material is typified by hydrogen.
Reach the other surface through reaction with the original gas and react.
By responding, both surfaces are etched. example
For example, Si + H₂ → SiH₂ , SiH₂ + SiO ₂ → 2S
iO + H₂ There is a reaction. S dissociated from the Si surface
i atoms are transported in the gas phase, and SiO
₂ Is converted into SiO having a high saturated vapor pressure. S
iH₂ Is consumed at any time, so etching on the Si surface is also
Be promoted. If Si faces each other, is it the Si surface?
When the dissociated Si atoms reach a saturation concentration in the gas phase,
Subsequent reactions are rate-limited by diffusion in the gas phase. this
Since the saturation concentration of dissociated Si is not high,
The speed is not so high.

On the other hand, SiO is added to Si.₂ When facing each other,
Si atoms dissociated from the Si surface are
Since it is consumed, the reaction is not suppressed and proceeds further. S
iO ₂ Since SiO generated on the surface side has a high vapor pressure,
The reaction is rate-controlled as compared with the case where Sis face each other.
Peg.

When the material of the surface facing the single crystal silicon film was SiC, the etching amount of the single crystal silicon film was almost the same as when the facing surface was silicon.
Also, when the material of the facing surface was silicon nitride, the etching amount of the single crystal silicon film was suppressed similarly to the case where the facing surface was made of silicon.

That is, in the case of heat treating silicon in a hydrogen-containing atmosphere, if the facing surface is made of silicon oxide, the etching amount of silicon is about 10 times that in the case of using silicon as the facing surface.

(Etching device) A typical example of the etching device used in the present invention is as shown in FIG.
Various changes may be made as described below.

FIG. 5 shows an etching apparatus according to another embodiment.

In the apparatus of FIG. 5, a part of the gas containing hydrogen from the gas source 5 passes through the space between the base material W and the facing surface constituting member 3, that is, the working space AS, and is sent to the exhaust pump 8. It is configured to flow.

The method of arranging the base material W and the facing surface constituting member 3 is limited to parallel to the longitudinal direction (horizontal direction in the drawing) of the furnace tube constituting the furnace 1 as shown in FIG. However, it may be configured as shown in FIG. Alternatively, as will be described later, the substrate W and the member 3 may be arranged in an inclined manner in a horizontal furnace, or may be vertically arranged.

It is also possible to arrange a plurality of base materials W in a single furnace in parallel so as to be parallel to each other.

FIG. 6 shows an etching apparatus capable of collectively etching a plurality of such base materials.

Substrate W1 having a silicon oxide film on its surface
Arrange W so that they are all facing upward. At this time,
Since there is no facing surface on the surface of the base material W1 at the top,
Desired etching is not performed on the surface of the base material W1. Therefore, in this case, the base material W1 functions as a dummy base material. Except for the uppermost base material W1, the other base materials W are opposed to the back surface made of silicon oxide of the base material W having the facing surface, so that the front surface made of silicon of the base material W is etched. To be done.

When all the base materials W1 and W are arranged downward, the lowest base material is the dummy base material.

Further, FIG. 6 shows the main part of the constitution of a so-called vertical furnace, but if this is oriented horizontally, it becomes a horizontal furnace capable of collectively etching a plurality of base materials.

The apparatus of FIG. 6 cannot collectively etch a plurality of substrates unless the substrate having a back surface made of silicon oxide is processed.

Therefore, FIG. 7 shows an example in which the back surface can be applied to a base material made of non-oxidized silicon such as Si, SiC, and SiN.

That is, the Si surface of the base material W2 is a back surface made of silicon oxide of the member 31 (opposing surface 4) by interposing the facing surface constituting member 31 having at least a back surface made of silicon oxide between the two base materials. Is facing. With this configuration, the Si surface of the base material W2 is etched.

Further, although the shape of the member 31 is processed into a tray shape for holding the base material in FIG. 7, the shape is not limited to such a shape and may be a simple plate shape.

In any case, the distance from the facing surface is 1
In the case of a semiconductor substrate having a length of 00 mm or more, if it is approximately 20 mm or less, and more preferably 10 mm or less, the effect of enhancing etching due to the interaction with the facing surface material can be obtained.

Further, the etching rate of silicon on the main surface (surface) of the substrate in the heat treatment step in a reducing atmosphere containing hydrogen is increased by the presence of oxidizing impurities such as water and oxygen contained in the atmospheric gas. Be speeded up. If the flow rate of the atmospheric gas near the main surface is reduced in order to suppress the supply of these moisture and oxygen, the amount of etching due to these impurity gases decreases. In this way, the etching controllability by the mutual effect with the silicon oxide facing surface is enhanced. In particular, as shown in FIG. 8, the surface of the base material W installed in the core tube 1 is arranged so as to be orthogonal to the gas flows 11 and 14, and the facing surface 4 made of silicon oxide is spaced by 20 mm. By arranging as follows, the flow rate 12 of the atmospheric gas on the surface can be substantially zero, and the etching effect by the facing silicon oxide can be sufficiently brought out.

In FIG. 8, the silicon substrate 2 is used as the base material W.
Embedded insulating film 22 and SOI layer 2 made of silicon
3 shows an example of using the facing surface constituting member 3 composed of an SOI substrate having a No. 3 and a silicon substrate having a silicon oxide film formed on the surface thereof.

FIG. 9 shows a modification of the etching apparatus having the vertical furnace shown in FIG.

The four base materials W and the dummy base material W1 are coaxially arranged and held by the protrusions of the boat 13 as a support.

Here, a Si substrate having a silicon oxide film formed on the front and back surfaces is used as the dummy base material W1, and an SO having the silicon oxide film 24 formed on the back surface as the base material W is used.
An example using an I substrate is shown.

Also in this example, the flow velocity of the gas passing through the region (that is, the outer peripheral portion) excluding the cross-sectional area of the semiconductor base material from the cross-sectional area of the core tube is 10 cc / min · cm ^{2 to} 300 cc.
/ Min · cm ² so that the gas flow velocity 12 in the direction near the surface of the substrate W in the direction parallel to the surface is smaller than the gas flow velocity 11 in the direction perpendicular to the surface of the outer peripheral portion of the substrate W. I am trying.

Furthermore, the flow velocity 11 in the region (outer peripheral portion) excluding the cross-sectional area of the semiconductor base material from the cross-sectional area of the core tube was 30 cc / m.
The flow velocity 12 of the gas in the vicinity of the center of the surface of the base material W may be set to substantially 0 by setting it to be about in cm ^{2 to} 150 cc / min · cm ² .

In each of the etching apparatuses described above, the furnace 1, tray 31, support 9,
As 13 and the like, those made of quartz glass or the like may be used.

As the heater 2, a resistance heater, a lamp heater, a high frequency heater or the like is used.

(Method for Producing Semiconductor Base Material) Next, a method for producing a semiconductor base material using the etching method of the present invention will be described.

FIG. 10 shows the hydrogen injection peeling method, the PACE method,
Bonded SOI represented by the epitaxial layer transfer method
6 shows a flowchart of a method for manufacturing a substrate.

First, in step S1, a first base material is prepared. For example, Si with an insulating film having at least one surface oxidized
Hydrogen ions or rare gas ions are implanted into the wafer to form a separation layer (latent layer) at a predetermined depth position. Or S
After making the surface of the i-wafer porous, a non-porous Si layer is epitaxially grown.

In the case of the PACE method, Si without an oxide film is used.
A wafer or a Si wafer whose surface is oxidized is prepared.

On the other hand, in step S2, a second base material is prepared. For example, a normal Si wafer whose surface is oxidized, a Si wafer from which a natural oxide film is removed, a quartz wafer, a metal substrate, and the like are prepared.

Succeedingly, in a step S3, the steps S1 and S are performed.
The first and second base materials prepared in 2 are directly or indirectly bonded to each other via an adhesive layer.

At this time, it is more preferable that at least one of the bonding surface of the first base material and the bonding surface of the second base material is formed of an insulator. Of course, this is not the case when a base material other than the SOI structure is manufactured.

Further, before bonding, the bonding surface made of an insulator may be irradiated with ions of hydrogen, oxygen, nitrogen or a rare gas to activate the bonding surface.

Next, in step S4, the first bonded
And a part (unnecessary part) of the first base material is removed from the second base material (assembly). There are two major removal methods.
There are various types, one is a method of removing a part of the first base material from the back surface of the first base material by grinding and / or etching or the like. The other is a method of separating the back surface side portion and the front surface side portion of the first base material in the separation layer formed on the first base material. According to the latter method, since the unnecessary portion maintains the wafer shape, it can be used again as the first base material or the second base material. As a separation method,
There are a method of heat treatment, a method of spraying a fluid composed of a liquid or a gas on the side surface of the assembly, a method of mechanically peeling off.

Then, the surface of the silicon layer (SOI layer) of the assembly (SOI substrate) from which the unnecessary portions have been removed is uneven due to voids generated by the implanted ions, holes in the porous body, grinding, etching and the like. It has a rough surface. Therefore, in step S5, the upper layer portion of the silicon layer, which is the rough surface, is removed by performing the above-described etching. At this time, the surface of the etched silicon layer becomes a smooth surface with a surface roughness of 0.2 nm or less (1 μm square area) due to the smoothing effect that occurs together. If the conditions are optimized, it is 0.15 nm or less, Further, it can be made 0.1 nm or less.

FIG. 11 shows an SOI represented by the SIMOX method.
6 shows a flowchart of a method for manufacturing a substrate.

First, in step S11, S is used as a starting material.
Prepare an i-wafer.

Next, in step S12, the acceleration voltage is 100 ke.
V to 300 keV, 2 × 10¹⁷cm ^-2~ 4 x 10¹⁸cm
^-2Implant oxygen ions with a moderate dose.

In step S13, the oxygen ion-implanted wafer is heat-treated at a temperature of 1000 ° C. to 1400 ° C. to form a buried oxide film.

Next, in step S14, if an oxide film is formed on the surface of the SOI layer, the surface oxide film is removed.

The surface of the SOI layer of the SOI substrate thus obtained was caused by oxygen ion implantation (step S12) and formation of a buried oxide film (step S13) even if a polished wafer was used as a starting material. The surface has irregularities. Therefore, in step S15, the upper layer portion having the unevenness of the SOI layer is removed by performing the above-described etching. At this time, the surface of the SOI layer after being etched by the smoothing effect becomes a smooth surface with Rrms in a 1 μm square area of 0.4 nm or less and Rrms in a 50 μm square area of 1.5 nm or less.

Among the methods for manufacturing a semiconductor substrate according to the present invention described above, the steps for manufacturing an SOI substrate using the hydrogen implantation delamination method will be described in more detail.

In step S21, Si as the first base material is used.
At least the surface of the wafer 31 is thermally oxidized to form a silicon oxide layer to be the buried insulating film 22, and hydrogen ions or rare gas ions are dosed at 1 × 10 ¹⁶ cm ⁻² to 1 × 10 ¹⁹ c.
Ion implantation is performed at m ⁻² and an acceleration voltage of 10 keV to 500 keV. As the ion implantation method, a method of implanting ions from the plasma using the potential difference between the plasma of hydrogen or a rare gas and the wafer can be used instead of using the ion implantation apparatus. Thus, the separation layer 32 is formed.

In step S22, the surface of another Si substrate 21 as the second base material is oxidized, and if necessary, the oxide film on the bonding surface is removed as shown in FIG. 12 to expose the exposed Si.
The surface and the surface of the insulating film 22 are attached to each other. In this way, an assembly in which two Si substrates are bonded together can be made.

In step S23, the assembly is separated at the separation layer 32. For separation, if a high-pressure fluid (eg, liquid or gas) is applied to the side surface of the assembly, the separation layer becomes a fragile layer having relatively low mechanical strength. The wafer 31 is peeled (separated) from the assembly while being left on.

Alternatively, when heat treatment is performed at a temperature of 500 ° C. or higher at the same time as or after the bonding step, minute bubbles generated due to hydrogen ions or rare gas ions grow in the separation layer, and the silicon film 22 is formed on the wafer 21. The wafer 31 is separated from the assembly, leaving it above.

The wafer 31 separated and removed from the assembly as described above maintains the wafer shape even though the thickness is reduced by the thickness of the silicon film 23. Therefore, the first or second substrate is again formed. It can be used as a material. In the case of reuse, after polishing the surface exposed by separation, it is preferable to grow a single crystal silicon film by epitaxial growth.

The surface of the silicon film 25 after separation is a rough surface having irregularities due to minute bubbles (minute voids). Therefore, in step S24, as described above, heat treatment is performed in a hydrogen-containing reducing atmosphere with the surfaces made of silicon oxide facing each other, and the upper layer portion of the silicon film 25 having a rough surface is removed by etching. At this time, the surface of the silicon film 25 after etching becomes a smooth surface.

In the example of FIG. 12, the silicon oxide film 2 is formed on the back surface.
Since the wafer 21 having No. 4 is used, the silicon oxide film remains on the back surface of the SOI substrate after the process S23 is completed. Therefore, a plurality of such SOI substrates can be simultaneously etched by the present invention by using the apparatus shown in FIGS. 6 and 9.

As the method of forming the silicon oxide film on the back surface, instead of the method of forming before bonding as shown in FIG. 12, the method of forming after separation or the heat treatment of bonding in an oxidizing atmosphere. The method of forming the back surface oxide film 24 at the same time as the bonding step may be adopted.

Next, a method of manufacturing a semiconductor substrate using the epitaxial layer transfer method will be described in more detail.

As shown in FIG. 13, first in step S31,
A substrate 31 made of Si single crystal is prepared as a first base material, and a layer 33 having a porous structure is formed on at least the main surface side. Porous Si can be formed by anodizing a Si substrate in an HF solution. The porous layer has a sponge-like structure in which pores having a diameter of about 10 ^-1 nm to 10 nm are arranged at intervals of about 10 ^-1 nm to 10 nm. The density is 50 to 2 as compared with the density of single crystal Si of 2.33 g / cm ^3.
2.1-0.6 g / c by changing to 0%, changing alcohol addition ratio, and changing current density
It can be changed in the range of m ³ . Further, if the specific resistance and the electric conduction type of the portion to be made porous are previously modulated, the porosity can be varied based on this. In the p-type, under the same anodization conditions, the specific degenerate substrate (P ⁻ ) has a smaller pore size, but the pore density increases by about one digit and the porosity is higher than that of the degenerate substrate (P ⁺ ).
That is, the porosity can be controlled by varying these various conditions, and is not limited to any method. The porous layer 33 may have a single layer or a structure in which a plurality of layers having different porosities are laminated. If the ion implantation is performed so that the projection range is included in the porous layer formed by anodization, bubbles are formed in the porous hole wall near the projection range, and the porosity can be increased. Ion implantation may be performed before or after formation of the porous layer by anodization. Furthermore, the porous layer 33
It may be after the single crystal semiconductor layer structure is formed thereover.

Next, in step S32, at least one non-porous single crystal semiconductor layer 23 is formed on the porous layer 33. The non-porous single crystal semiconductor layer 23 is arbitrarily selected from a single crystal Si layer formed by epitaxial growth, a layer obtained by making the surface layer of the porous layer 33 non-porous, and the like. Further, when the silicon oxide layer 22 is formed on the single-crystal Si layer 33 by the thermal oxidation method, the interface between the single-crystal silicon layer and the buried oxide film can be an interface formed by thermal oxidation with a small interface state. Is preferred. In step S33, the main surface (bonding surface) of the semiconductor substrate having the non-porous single crystal Si layer 23 formed thereon is brought into close contact with the surface (bonding surface) of the second substrate 21 at room temperature. It is desirable to clean the surface before removing it to remove foreign matter and foreign matter. The second substrate can be selected from Si, a Si substrate on which an oxidized Si film is formed, a light-transmissive substrate such as quartz, sapphire, etc., but is not limited to this and can be used for bonding. It does not matter if the surface provided is sufficiently flat and smooth. Although FIG. 13 shows a state in which the second substrate and the first substrate are bonded together via the insulating layer 22, the insulating layer 22 may be omitted.

When laminating, the insulating thin plate is firstly placed.
It is also possible to bond three scissors between the second substrate and the second substrate.

Subsequently, the unnecessary portion on the back surface side of the first substrate 31 and the porous layer 33 are removed to remove the non-porous single crystal Si layer 23.
Express. As mentioned above, there are two methods, but the method is not limited thereto.

In the first method, the first substrate 21 is removed from the back surface side to expose the porous layer 33 (step S3).
4).

Then, the porous layer 33 is removed to expose the non-porous single crystal silicon layer 23 (step S35).

It is desirable to remove the porous layer by selective etching. When a mixed solution containing at least hydrofluoric acid and hydrogen peroxide is used, porous silicon can be selectively etched 10 ⁵ times with respect to non-porous single crystal silicon. A surfactant for preventing bubbles from adhering may be added to the above etching solution. Particularly, alcohol such as ethyl alcohol is preferably used. If the porous layer is thin, this selective etching may be omitted.

In the second method, the porous layer 3 serving as the separation layer
The substrate is separated in 3 to obtain the state as in step S34 of FIG. As a method of separating, a method of applying an external force such as pressurization, tension, shearing, a wedge, a method of applying ultrasonic waves; a method of applying heat; Method of applying; pulsed heating to apply thermal stress or softening;
There is a method of ejecting a fluid such as a water jet or a gas jet, but the method is not limited to this.

Subsequently, in step S35, the porous layer 33 remaining on the surface side of the second substrate 21 is removed by etching. The porous etching method is the same as the method for exposing the porous layer 33 by etching. If the porous silicon layer 33 remaining on the second substrate 21 side is extremely thin and has a uniform thickness, wet etching of the porous layer with hydrofluoric acid and hydrogen peroxide solution may not be performed.

Subsequently, in step S36, heat treatment is performed in a reducing atmosphere containing hydrogen to remove the upper layer portion 25 of the single crystal Si layer 23 having irregularities by etching. At this time, reduction of boron concentration in the single crystal silicon layer and surface smoothing can be achieved at the same time.

In the semiconductor substrate obtained by the present invention, the single crystal Si film 23 is flatly and uniformly thinned on the second substrate 21 via the insulating layer 22 to form a large area over the entire substrate. Has been done. The semiconductor substrate thus obtained can be suitably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

For the separated first Si single crystal substrate 31, the porous layer remaining on the separated surface is removed, and if the surface smoothness is unacceptably rough, the surface is smoothed. Then, it can be used again as the first Si single crystal substrate 31 or the next second substrate 21.

In the example shown in FIG. 13, silicon oxide is not formed on the back surface of the substrate 21. In the case of simultaneously etching a large number of wafers, a silicon oxide film needs to be formed on the back surface of the substrate 21 in order to use the back surface of the SOI substrate as an opposing surface made of silicon oxide.

Therefore, after the step S35, the silicon film 23 is formed.
To form a silicon oxide film on the back surface of the substrate 21, a silicon oxide film on the back surface of the substrate 21 before the bonding step S33, or a silicon oxide film on the back surface of the substrate 21 in the bonded state (S33). Should be formed.

FIG. 14 schematically shows the state of the silicon surface before and after etching according to the present invention.

W3 shows the cross section of the base material before etching, and W4 shows the cross section of the base material after etching.

Before etching, when observing a 1 μm square area with an atomic force microscope, the surface mean square roughness (Rrm
The rough surface whose (s) was about 0.2 nm to 20 nm was also smoothed by the etching according to the present invention, and Rrms was 0.
It is about 07 nm to 0.15 nm. This is a value equivalent to that of a polished Si wafer or a surface smoother than that.

In FIG. 14, h is the height difference (peak to valley), p is the period, and t is the etching thickness.

According to the present invention, the surface roughness is smoothed by at least about one-third, so that the height difference h is several n.
Large from m to several tens of nm, and the period p is from several nm to several hundred nm
Even on a silicon surface where large irregularities are observed, it is possible to form a flat surface having at least a height difference lower than that value, for example, 2 nm or less, more preferably 0.4 nm or less, by etching.

This phenomenon is considered to be surface reconstruction that occurs at the same time as etching. That is, on a rough surface, there are innumerable ridges with high surface energy,
Many planes of higher plane orientation than the plane orientation of the crystal layer are exposed on the surface, but the surface energy of these regions is higher than the surface energy depending on the plane orientation of the single crystal surface. In the heat treatment in a reducing atmosphere containing hydrogen, for example, the energy barrier for the transfer of surface Si atoms is lowered by the reducing action of hydrogen, the Si atoms excited by thermal energy are transferred, and the surface energy is low, flat or smooth. It is considered that the The lower the plane orientation of the single crystal surface, the more the flattening / smoothing according to the present invention is promoted.

(Example 1: Transfer of epitaxial layer / horizontal furnace / opposite surface SiO ₂ ) 49% HF and 2% ethyl alcohol were used on a 6-inch wafer surface of (100) orientation made of boron-doped Si having a specific resistance of 0.015 Ωcm: Porous silicon was formed on the surface of the wafer to a thickness of 10 μm by anodizing in the solution mixed in 1. After heat-treating this silicon wafer in an oxygen atmosphere at 400 ° C. for 1 hour, 1.25%
After being immersed in the HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, it was thoroughly washed with water and dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated in a hydrogen atmosphere at 1100 ° C. to seal most of the pores on the surface of the porous silicon. Subsequently, by adding dichlorosilane as a silicon source gas to hydrogen gas, a single crystal silicon film on the porous silicon has an average of 300 nm plus / minus 5 nm.
It was formed with a thickness of. This silicon wafer was taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200 nm. As a result of being oxidized, the thickness of the single crystal silicon film became 210 nm. Prepare a second silicon wafer separately from this silicon wafer,
Each silicon wafer was subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface, and then bonded. The bonded silicon wafer assembly is placed in a heat treatment furnace, and the temperature is 1100 ° C.
Heat treatment was performed for 1 hour to increase the adhesive strength of the bonded surfaces. The heat treatment atmosphere was nitrogen. The back surface of the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon. It was dipped in a mixed solution of HF and hydrogen peroxide water to remove the porous silicon by etching, and washed well by wet washing. The single crystal silicon film formed by epitaxial growth is transferred onto the second silicon wafer together with the silicon oxide film,
An I-wafer was made.

The film thickness of the transferred single crystal silicon is set to 1 in the plane.
When measured at 0 mm grid points, the average film thickness was 210 nm, and the variation was plus or minus 5 nm. Approximately 10 to make the SOI layer 200 nm
nm had to be removed. In addition, the surface roughness is 256 × in the range of 1 μm square and 50 μm square with an atomic force microscope.
When measured at 256 measurement points, the surface roughness is 10.1 nm in terms of mean square roughness (Rrms) and 9.
It was 8 nm. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

The back surface of this SOI wafer was previously cleaned with hydrofluoric acid or the like to remove the natural oxide film and the like, and then the SOI wafer was placed in a horizontal heat treatment furnace composed of a cylindrical core tube made of quartz. Gas flows from one of the core tubes to the other. The four SOI wafers were set by the following four methods. Sample A: FIG. 15 (a): One SOI wafer W is horizontally installed in a furnace, and 200 nm above the SOI wafer W on the surface.
The silicon wafer 3 having the silicon oxide film 4 formed thereon is placed in parallel with each other. The distance between the wafers is about 10 mm. Sample B: FIG. 15B: One SOI wafer W is horizontally installed in the furnace, and the bare silicon wafer 84 is installed above the SOI wafer W in parallel with each other. The distance between the wafers is about 10 mm; Sample C: FIG. 8C: One SOI wafer W, two on the surface
The silicon wafer 3 on which the silicon oxide film 4 of 00 nm is formed is placed so as to be opposed to and inclined in the furnace; Sample D: FIG. 8D: One SOI wafer W is oriented with the SOI layer in the upstream direction of the flow in the furnace. In this way, the silicon wafer 3 having the silicon oxide film 4 of 200 nm formed on its surface is opposed to the wafer so that the center of the wafer is on the center line of the furnace and is perpendicular to the center line. Although not shown in the drawings, the wafer was supported by using a jig made of quartz.

After the atmosphere in the furnace was replaced with hydrogen, the temperature was raised to 1100 ° C., the temperature was maintained for 4 hours, then the temperature was lowered again, the gas atmosphere was replaced with nitrogen, and then the wafer was taken out to obtain a single crystal. The film thickness of the silicon film was measured again. The amount of film thickness reduction was as follows. The flow rate of hydrogen gas was 5 slm. The film thickness was measured and averaged on grid points at intervals of 10 mm in the plane.

[0161] The amount of decrease in the film thickness of the SOI wafer was about 10 nm when silicon oxide was used as the facing surface, and the film thickness was able to meet the specifications. On the other hand, in the comparative example, that is, in the case of the sample B in which the facing surface was a silicon wafer, the amount of reduction in film thickness was extremely small at 1 nm, and etching could never be called a treatment.

When the surface roughness of the single crystal silicon film after the above heat treatment was measured by an atomic force microscope, the mean square roughness (Rrms) was found to be And commercial silicon wafers (0.13nm, 0.31nm)
It was smoothed to the same level.

Regarding the boron concentration in the single crystal silicon film, secondary ion mass spectrometry (SIM
When measured by S), all were reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which device fabrication was sufficiently possible.

(Example 2: Transfer of epitaxial layer / vertical furnace / boats / backside oxide film) Specific resistance is 0.017 Ωc
The surface of a 6-inch (100) -oriented wafer made of boron-doped Si of m is 49% HF and 2: 2.
Porous silicon was formed on the surface of the wafer to a thickness of 10 μm by anodizing in the solution mixed in 1. After heat-treating this silicon wafer in an oxygen atmosphere at 400 ° C. for 1 hour,
After soaking in a 1.25% HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, it was thoroughly washed with water and dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated at 1100 ° C. in a hydrogen atmosphere while adding a very small amount of silane gas to seal almost all pores on the surface of the porous silicon. Then,
By adding silane as a silicon source gas to hydrogen gas, a single crystal silicon film was formed on the porous silicon with an average thickness of 310 nm (error 5 nm). This silicon wafer is taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film is oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200
nm formed. As a result of being oxidized, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and a second silicon wafer having a 200 nm silicon oxide film formed on the entire front and back surfaces by thermal oxidation were each subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface. After that, I stuck them together. The bonded silicon wafer assembly was placed in a heat treatment furnace and heat-treated at 1100 ° C. for 1 hour to increase the adhesive strength of the bonded surface. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, held at 1100 ° C. for 1 hour, and cooled in the nitrogen atmosphere. The back surface of the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon. HF
The porous silicon was removed by etching by immersing it in a mixed solution of hydrogen peroxide and hydrogen peroxide, and washed well by wet washing. The single crystal silicon film formed by epitaxial growth was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

When the film thickness of the single crystal silicon transferred in one sample was measured at each in-plane lattice point of 10 mm, the average film thickness was 210 nm and the variation was positive.
It was minus 4.3 nm. Further, the surface roughness is 256 with respect to the range of 1 μm square and 50 μm square by an atomic force microscope.
When measured at measurement points of × 256, the surface roughness is 10.1 nm in terms of mean square roughness (Rrms),
It was 9.8 nm. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

These SOI wafers were placed in the vertical heat treatment furnace consisting of the quartz core tube shown in FIG. 9 with the silicon oxide film on the back surface attached. The gas flows downward from the upper part of the furnace.

The wafer 1 is horizontally and as shown in FIG.
The silicon oxide 24 on the back surface of one SOI wafer is another S
The wafer was placed on a quartz boat 13 as a support so as to face the surface of the SOI layer 23 of the OI wafer at an interval of about 6 mm, and to align the center of the wafer with the center line of the core tube. On the uppermost SOI wafer, the silicon wafers 3 having the silicon oxide film 4 formed thereon were arranged at the same intervals. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1100 ° C., held for 6 hours, then lowered again, the wafer was taken out, and the film thickness of the SOI layer was measured again.
The reduction in film thickness of SOI wafers was 10 nm plus or minus 1 nm or less on average for all wafers, and it was possible to achieve the film thickness of 200 nm as designed.

On the other hand, the boat 13 supporting the wafer is set to Si.
When a similar experiment was attempted in place of the C-made one, the etching amount in the central part of the wafer was 10 nm as in the case of the quartz boat, but at a position supported by the boat, that is, near the wafer periphery. The etching amount in 1 was as small as 1 nm, and as a result, the etching amount varied in-plane. That is, it was found that it is preferable to use SiO ₂ as the boat material.

On the other hand, when the silicon oxide film on the back surface is peeled off before the heat treatment so that the surface facing the SOI layer becomes silicon and the heat treatment is performed in the same hydrogen atmosphere as above, it faces the SOI wafer. In addition, the reduction in the thickness of the SOI layer was as small as 1 nm at the maximum. That is, the etching effect was not obtained when the material of the facing surfaces was silicon.

Further, the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope. The root mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.35 nm at 50 μm square. It was as smooth as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and it was reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which device fabrication was sufficiently possible. Was there.

(Example 3: Transfer of Epitaxial Layer / Vertical Furnace / Quartz Tray) 49% HF and ethyl alcohol are 2: 1 on the surface of a (100) -oriented 8-inch wafer made of boron-doped Si having a specific resistance of 0.017 Ωcm. Porous silicon is anodized on the surface of wafer by anodizing in mixed solution.
It was formed with a thickness of 0 μm. This silicon wafer was heat-treated in an oxygen atmosphere at 400 ° C. for 1 hour, and then treated with 1.25% H 2.
After soaking in the F aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, it was thoroughly washed with water and dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated at 1100 ° C. in a hydrogen atmosphere while adding a very small amount of silane gas to seal almost all pores on the surface of the porous silicon. Subsequently, by adding dichlorosilane as a silicon source gas to hydrogen gas, a single crystal silicon film is formed on the porous silicon on an average of 34%.
It was formed with a thickness of 0 nm plus or minus 5 nm. This silicon wafer is taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film is oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200
nm formed. As a result of being oxidized, the thickness of the single crystal silicon film became 250 nm. This silicon wafer and the second silicon wafer were each subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface, and then they were bonded together. Place the bonded silicon wafer assembly in the heat treatment furnace and
Heat treatment was performed at 100 ° C. for 1 hour to increase the adhesive strength of the bonded surfaces. The back surface of the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon. Immerse in a mixed solution of HF and hydrogen peroxide water,
The porous silicon was removed by etching and washed well by wet washing. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The film thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 242 nm, and the variation was plus or minus 4 nm. In addition, the surface roughness was measured with an atomic force microscope at 1 μm square, 5
When measured at 256 × 256 measurement points in a 0 μm square range, the surface roughness is the mean square roughness (Rrm
s) was 10.1 nm and 9.8 nm, respectively. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

All of these SOI wafers from which the natural oxide film on the back surface was removed with hydrofluoric acid were placed on a quartz tray in a vertical heat treatment furnace composed of a quartz core tube. The gas flows downward from the upper part of the furnace. The wafer should be horizontal, as shown in Figure 7.
In addition, the back surface of the tray on which one SOI wafer is placed faces the SOI layer surface of another SOI wafer at an interval of about 6 mm, and the center of the wafer is aligned with the center line of the furnace core tube. A commercially available silicon wafer placed on a quartz tray was placed at the same interval on the uppermost SOI wafer. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C and
After holding for a while, lower the temperature again, take out the wafer, and
The thickness of the I layer was measured again. The amount of film thickness reduction of SOI wafers is 41.5 nm for all wafers.
The layer thickness was 200.5 nm.

That is, even if there is no silicon oxide on the back surface, the silicon layer could be etched by placing the wafer on a quartz tray and setting the opposing surface of the wafer directly below to quartz.

Further, the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope. As a result, the root mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.30 nm at 50 μm square. It was as smooth as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and as a result, it was reduced to 1 × 10 ¹⁵ / cm ³ or less, which was a level sufficient for device fabrication. Was there.

(Example 4: Separation by WJ) Boron-doped Si having a specific resistance of 0.017 Ωcm (10)
The surface of the 0) oriented 8-inch wafer was anodized in a solution of 49% HF and ethyl alcohol mixed at a ratio of 2: 1 to form porous silicon on the surface of the wafer to a thickness of 10 μm. At that time, by changing the current, the thickness of 1μ
m, a high porosity layer with a porosity of about 60%, and a thickness of 5 on it.
A low porosity layer with a micrometer porosity of 20% was formed. This silicon wafer was heat-treated in an oxygen atmosphere at 400 ° C. for 1 hour, then immersed in a 1.25% HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, and then washed thoroughly with water. And dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated at 1100 ° C. in a hydrogen atmosphere while adding a very small amount of silane gas to seal almost all pores on the surface of the porous silicon. Subsequently, a single crystal silicon film having an average thickness of 340 nm plus / minus 5 nm was formed on the porous silicon by adding dichlorosilane as a silicon source gas to hydrogen gas. This silicon wafer was taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200 nm. As a result of being oxidized, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and a second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation are subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface. I stuck them together. The bonded silicon wafer assembly was placed in a heat treatment furnace and heat-treated at 1100 ° C. for 1 hour to increase the adhesive strength of the bonded surface. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, held at 1100 ° C. for 1 hour, and cooled in the nitrogen atmosphere. A high-pressure water jet was applied to the side surface of the silicon wafer assembly to separate the silicon wafer assembly in the high-porosity porous layer by the action of a fluid wedge to expose the porous layer. Of these, the second silicon wafer was dipped in a mixed solution of HF and hydrogen peroxide solution to remove the porous silicon by etching and thoroughly washed by wet cleaning. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 242 nm with a variation of plus or minus 6 nm. In addition, the surface roughness was measured with an atomic force microscope at 1 μm square, 50
The surface roughness was measured as a root mean square roughness (Rrms) when measured at 256 × 256 measurement points in the μm angle range.
And 10.1 nm and 9.8 nm, respectively. Also,
When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

These SOI wafers were placed in a vertical heat treatment furnace composed of a quartz core tube while confirming that the silicon oxide film on the back surface remained. The gas flows downward from the upper part of the furnace. As shown in FIG. 9, the wafer is horizontal and one S
The silicon on the back side of the OI wafer is the SO of another SOI wafer.
The wafer is placed on a quartz boat so that it faces the surface of the I layer at an interval of about 6 mm, and the center of the wafer coincides with the center line of the core tube. A commercially available silicon wafer having a silicon oxide film formed on its back surface was arranged at the same intervals. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C and
After holding for a while, lower the temperature again, take out the wafer, and
The thickness of the I layer was measured again. The average film thickness reduction amount of the SOI wafer was 43.2 nm.

In other words, the silicon layer could be set to a desired film thickness for etching by using silicon oxide as the material of the surfaces facing each other.

Further, the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope. As a result, the root mean square roughness (Rrms) was 0.12 nm at 1 μm square and 0.34 nm at 50 μm square. It was as smooth as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and it was reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which device fabrication was sufficiently possible. Was there.

(Example 5: BESOI / vertical furnace / quartz boat) A (100) -oriented 8-inch wafer made of boron-doped Si having a specific resistance of 0.007 Ωcm was placed in an epitaxial growth apparatus and heat-treated at 1100 ° C. in a hydrogen atmosphere. After lowering the temperature to 900 ° C., dichlorosilane is added to the hydrogen gas as a silicon source gas to form an average single crystal silicon film of 300 nm plus / minus 5 n.
It was formed with a thickness of m. This silicon wafer was taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200 nm. As a result of being oxidized, the thickness of the single crystal silicon film became 200 nm. This silicon wafer and a second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface. Then, after subjecting them to oxygen plasma treatment to activate both surfaces, they were washed with water and bonded. Place the bonded silicon wafer assembly in the heat treatment furnace, and
Heat treatment was performed at 00 ° C. for 10 hours to increase the adhesive strength of the bonded surfaces. The heat treatment atmosphere was nitrogen. The back surface of this silicon wafer assembly on the side of the first silicon wafer was ground until the thickness of the first silicon wafer became about 5 μm. Then, the P ⁺ layer was selectively etched by immersing in a 1: 3: 8 mixed solution of hydrofluoric acid, nitric acid and acetic acid. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The film thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 190 nm, and the variation was plus or minus 20 nm. In addition, the surface roughness can be measured with an atomic force microscope at 1 μm square,
When the surface roughness was measured at 256 × 256 measurement points in a 50 μm square area, the surface roughness was a mean square roughness (Rrm
2 nm and 2.2 nm in s).

These SOI wafers were placed in a vertical heat treatment furnace consisting of a quartz mandrel after confirming that there was a silicon oxide film on the back surface. The gas flows downward from the upper part of the furnace.
The wafer is horizontal as shown in FIG. 9, and the silicon oxide on the back surface of one SOI wafer faces the surface of the SOI layer of another SOI wafer at an interval of about 6 mm, and the center of the wafer and the center of the core tube They were placed on a boat made of quartz so that the lines coincide with each other, and a silicon wafer having a silicon oxide film formed on the front surface and the back surface was arranged at the same interval on the uppermost SOI wafer. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C., held for 1 hour, then lowered again, the wafer was taken out, and the film thickness of the SOI layer was measured again. SOI wafer thickness reduction on average is 4
At 0.8 nm, the SOI layer was 149.2 nm, which was close to the design specification of 150 nm.

When the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope, the root mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.35 nm at 50 μm square, which was commercially available silicon. It was as smooth as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and all were reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which a device could be manufactured sufficiently. .

(Example 6: Hydrogen injection delamination / vertical furnace / quartz boat) (100) -oriented Si 8-inch wafer surface 300 nm made of boron-doped Si having a specific resistance of 10 Ωcm
After oxidation, the implantation conditions are 50 KeV, 4 × 10 ¹⁶ / c
Hydrogen was ion-implanted as m ² . This silicon wafer and the second silicon wafer having an oxide film formed thereon were each subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface, and then bonded to each other. The bonded silicon wafer assembly was placed in a heat treatment furnace and subjected to heat treatment at 800 ° C. for 10 hours to increase the adhesive strength of the bonded surface. The heat treatment atmosphere was nitrogen. During this heat treatment, the silicon wafer assembly was separated at a depth corresponding to the projected range of ion implantation. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 280 nm and the variation was plus or minus 10 nm. In addition, the surface roughness can be measured with an atomic force microscope at 1 μm square,
When the surface roughness was measured at 256 × 256 measurement points in a 50 μm square area, the surface roughness was a mean square roughness (Rrm
In s), they were 9.4 nm and 8.5 nm, respectively.

These SOI wafers were placed in a vertical heat treatment furnace consisting of a quartz core tube with the silicon oxide film on the back surface attached. The gas flows downward from the upper part of the furnace. The wafer is horizontal as shown in FIG. 9, and the silicon oxide on the back surface of one SOI wafer faces the surface of the SOI layer of another SOI wafer at an interval of about 6 mm, and the center of the wafer and the center of the core tube They were placed on a boat made of quartz so that the lines were aligned with each other, and a commercially available silicon wafer having a silicon oxide film formed on the surface thereof was placed on the uppermost SOI wafer at the same intervals. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C., held for 2 hours, then lowered again, the wafer was taken out, and the film thickness of the SOI layer was measured again. The average film thickness reduction of SOI wafer is 80.
At 3 nm, the SOI layer became 199.6 nm.

Further, the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope. As a result, the root mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.35 nm at 50 μm square. It was as smooth as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and all were reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which a device could be manufactured sufficiently. .

Further, when the state before and after the heat treatment in a hydrogen atmosphere was observed by a cross-sectional TEM, dislocation groups observed near the surface of the SOI layer before the heat treatment were not observed after the heat treatment. It is considered that dislocations contained in the region removed by the heat treatment were removed together with the SOI layer by the etching.

(Example 7: Simox / vertical furnace / quartz boat) Oxygen was ion-implanted into the polished surface of a (100) -oriented 8-inch wafer made of boron-doped Si having a specific resistance of 10 Ωcm. Implantation conditions are 550 ° C, 180
KeV was 4 × 10 ¹⁷ / cm ² . This silicon wafer was placed in a heat treatment furnace, and was placed in an Ar + O ₂ mixture for 13
A buried oxide film was formed by performing heat treatment at 50 ° C. for 20 hours.

When the film thickness of the single crystal silicon on the buried oxide film was measured at each in-plane lattice point of 10 mm, the average film thickness was 200 nm and the variation was plus or minus 10 n.
It was m. Also, the surface roughness is 1 μm with an atomic force microscope.
The surface roughness is measured as a mean square roughness (R
rms) was 0.5 nm and 2 nm, respectively, and became rougher than before oxygen ion implantation. Further, when the boron concentration in the single crystal silicon film was measured by secondary ion mass spectrometry (SIMS), all were 5 × 10 ¹⁷ / cm ³ .

These SOI wafers were placed in a vertical heat treatment furnace consisting of a quartz core tube with the silicon oxide film on the back surface attached. The gas flows downward from the upper part of the furnace. As shown in FIG. 9, the wafer is horizontal, and the silicon on the back surface of one SOI wafer faces the surface of the SOI layer of another SOI wafer at an interval of about 6 mm, and the center of the wafer and the center line of the core tube. So that they coincide with each other, they were placed on a boat made of quartz, and a silicon wafer having a silicon oxide film formed on the front surface and the back surface was arranged at the same interval on the uppermost SOI wafer. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C., the temperature was maintained for 1.2 hours, the temperature was lowered again, the wafer was taken out, and the film thickness of the SOI layer was measured again. The amount of reduction in the film thickness of the SOI wafer was 50 nm in all the wafers, and the film thickness of the SOI layer was 150 nm plus or minus 10 nm.

When the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope, the mean square roughness Rrms was 0.3 nm at 1 μm square and 1.5 at 50 μm square.
nm and smoothed to the same level as a commercially available silicon wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and all were reduced to 5 × 10 ¹⁵ / cm ³ or less, which was a level at which a device could be manufactured sufficiently. .

Example 8 Transfer of Epitaxial Layer / Vertical Furnace / Quartz Tray 49% HF and 2% ethyl alcohol were used on the surface of a (100) -oriented 8 inch Si wafer made of boron-doped Si having a specific resistance of 0.017 Ωcm. Porous silicon was formed on the surface of the wafer to a thickness of 10 μm by anodizing in the solution mixed in 1. After this silicon wafer was heat-treated at 400 ° C. for 1 hour in an oxygen atmosphere, 1.25
% HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, then thoroughly washed with water and dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated at 1100 ° C. in a hydrogen atmosphere while adding a very small amount of silane gas to seal almost all pores on the surface of the porous silicon. Subsequently, a single crystal silicon film having an average thickness of 320 nm plus or minus 5 nm was formed on the porous silicon by adding dichlorosilane as a silicon source gas to hydrogen gas. This silicon wafer was taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200 nm. As a result of being oxidized, the thickness of the single crystal silicon film was 220 nm. A second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation is subjected to wet cleaning generally used in a silicon device process or the like, and the surface is activated by nitrogen plasma. It was washed with water, dried, and then laminated. The bonded silicon wafer assembly is placed in a heat treatment furnace, and the temperature is 400 ° C.
Heat treatment was performed for 0 hours to increase the adhesive strength of the bonded surfaces. The back surface of the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon. It was dipped in a mixed solution of HF and hydrogen peroxide water to remove the porous silicon by etching, and washed well by wet washing. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 220 nm and the variation was plus or minus 7 nm. In addition, the surface roughness was measured with an atomic force microscope at 1 μm square, 5
When measured at 256 × 256 measurement points in a 0 μm square range, the surface roughness is the mean square roughness (Rrm
s) was 10.1 nm and 9.8 nm, respectively. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

All of these SOI wafers were placed on a quartz tray and placed in a vertical heat treatment furnace consisting of a quartz core tube. The gas flows downward from the upper part of the furnace. Wafer is shown in FIG.
As shown in the figure, the tray on which one SOI wafer is placed is horizontally opposed to the surface of the SOI layer of another SOI wafer at an interval of about 6 mm, and the center of the wafer is aligned with the center line of the core tube. Thus, the quartz wafer was set on the quartz boat 93, and the silicon wafers placed on the quartz tray were also arranged at the same intervals on the uppermost SOI wafer.
After replacing the atmosphere in the furnace with hydrogen, raise the temperature to 1000 ° C.
After raising the temperature to 15 hours and holding the temperature again, the temperature was lowered again, the wafer was taken out, and the film thickness of the SOI layer was measured again. The film thickness of the SOI wafer could be reduced by 10 nm.

When the surface roughness of the single crystal silicon film after the heat treatment was measured by an atomic force microscope, the root mean square roughness Rrms was 0.11 nm at 1 μm square, and was 0.1 μm at 50 μm square.
It was as smooth as 50 nm, which is equivalent to that of a commercially available silicon wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and both were reduced to 1 × 10 ¹⁶ / cm ³ or less, which was a level at which device fabrication was sufficiently possible. Was there.

(Embodiment 9: Transfer of epitaxial layer / horizontal furnace / opposite surface SiO ₂ ) 49% HF and ethyl alcohol were mixed with 2% of a 6-inch wafer surface of (100) orientation made of boron-doped Si having a specific resistance of 0.015 Ωcm: Porous silicon was formed on the surface of the wafer to a thickness of 10 μm by anodizing in the solution mixed in 1. After heat-treating this silicon wafer in an oxygen atmosphere at 400 ° C. for 1 hour, 1.25%
After being immersed in the HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the porous surface and in the vicinity of the surface, it was thoroughly washed with water and dried. Subsequently, this silicon wafer was placed in an epitaxial growth apparatus and heat-treated in a hydrogen atmosphere at 1100 ° C. to seal most of the pores on the surface of the porous silicon. Subsequently, by adding dichlorosilane as a silicon source gas to hydrogen gas, a single crystal silicon film was formed on the porous silicon with an average thickness of 300 nm (error 5 nm). This silicon wafer was taken out from the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film of 200 nm. As a result of being oxidized, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and the second silicon wafer were each subjected to wet cleaning generally used in a silicon device process or the like to form a clean surface, and then they were bonded together. The bonded silicon wafer assembly was placed in a heat treatment furnace and heat-treated at 1100 ° C. for 1 hour to increase the adhesive strength of the bonded surface. The heat treatment atmosphere was nitrogen. The back surface of the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon. The porous silicon was removed by etching by immersing it in a mixed solution of HF and hydrogen peroxide water, and washed well by wet washing. The single crystal silicon film was transferred onto the second silicon wafer together with the silicon oxide film, and the SOI wafer was manufactured.

The film thickness of the transferred single crystal silicon is set to be in-plane 1
When measured at 0 mm grid points, the average film thickness was 210 nm, and the variation was plus or minus 5 nm. Since the design specification is 150nm, it is about 60n.
m had to be removed. Moreover, the surface roughness is 256 × 2 in the range of 1 μm square and 50 μm square by an atomic force microscope.
When measured at 56 measurement points, the surface roughness is 10.1 nm in mean square roughness (Rrms) and 9.8, respectively.
was nm. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸ / cm ³ .

This SOI wafer was placed in a horizontal heat treatment furnace consisting of a quartz-made cylindrical core tube. Gas flows from one of the core tubes to the other. The SOI wafer was tested for installation as follows.

Sample E The SOI wafer was made so that the single crystal silicon film was oriented in the upstream direction of the flow in the furnace, and the silicon wafer having a 133.3 nm silicon oxide film formed on its surface was made to face to the center of the wafer. Installed on the center line of the furnace and perpendicular to the center line.

Sample F The SOI wafer was made so that the single crystal silicon film was oriented in the upstream direction of the flow in the furnace, and the silicon wafer having a 200 nm silicon oxide film formed on the surface was opposed to the wafer so that the center of the wafer was the furnace. Installed so that it is on the center line and perpendicular to the center line.

In each case, the wafer was set using a jig made of quartz as a support.

After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C., the temperature was held for 2 hours, then the temperature was lowered again, and the gas atmosphere was replaced with nitrogen. Then, the wafer was taken out and the single crystal silicon film was formed. The film thickness was measured again. The amount of film thickness reduction was as follows. The flow rate was 5 slm. The film thickness was measured on the in-plane lattice points at intervals of 10 mm and averaged.

[0205] When the thickness of the silicon oxide film facing the SOI film was measured after the heat treatment, the silicon oxide was completely removed in Sample E. On the other hand, in sample F, silicon oxide has a thickness of 23 nm
Only remained. That is, in Sample E, the SOI layer was etched until the silicon oxide film disappeared, and after the silicon oxide film disappeared, the etching of the SOI film did not proceed. That is, the amount of silicon etched can be controlled by the thickness of silicon oxide.

Further, a semiconductor material other than Si can be deposited on the surface of the base material obtained by the present invention by heteroepitaxy.

[0207]

According to the present invention, it is possible to provide an etching method, an etching apparatus, and a method for manufacturing a semiconductor substrate, in which the etching amount can be easily controlled and uniform etching can be always performed even when a plurality of substrates are processed. be able to.

Further, it is possible to provide an etching method, an etching apparatus and a method for manufacturing a semiconductor substrate which can efficiently reduce impurities such as boron contained in the film while maintaining the film thickness uniformity.

Further, it is possible to provide an etching method, an etching apparatus and a method for manufacturing a semiconductor substrate, which can reduce the characteristic variations of devices manufactured by using the semiconductor substrate.

Further, it is possible to provide an etching method, an etching apparatus and a method for manufacturing a semiconductor substrate, which can easily obtain an arbitrary film thickness without the need for sacrificial oxidation, have few surface defects. it can.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an etching apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing the temperature dependence of the etching rate depending on the facing surface material.

FIG. 3 is a diagram showing an etching amount when Si and SiO ₂ face each other.

FIG. 4 S removed when Si and SiO ₂ face each other
It is a figure which shows i atomic weight.

FIG. 5 is a schematic cross-sectional view of an etching apparatus according to another embodiment of the present invention.

FIG. 6 is a schematic sectional view of a main part of an etching apparatus according to still another embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing an example of a facing surface constituent member used in the present invention.

FIG. 8 is a schematic cross-sectional view showing another example of the facing surface constituting member used in the present invention.

FIG. 9 is a schematic cross-sectional view of a main part of an etching apparatus according to another embodiment of the present invention.

FIG. 10 is a diagram showing a flowchart of an example of a method for manufacturing a semiconductor substrate using the etching method of the present invention.

FIG. 11 is a diagram showing a flowchart of another example of a method for producing a semiconductor substrate using the etching method of the present invention.

FIG. 12 is a schematic diagram for explaining a method for manufacturing a semiconductor substrate using the etching method and the hydrogen injection peeling method of the present invention.

FIG. 13 is a schematic diagram for explaining a method for manufacturing a semiconductor substrate using the etching method and the epitaxial layer transfer method of the present invention.

FIG. 14 is a schematic view for explaining the action of the etching method of the present invention.

FIG. 15 is a schematic diagram for explaining a method of disposing a base material during etching.

Continuation of the front page (56) Reference JP-A-4-168768 (JP, A) JP-A-2-28323 (JP, A) JP-A-4-146620 (JP, A) JP-A-3-123027 (JP , A) JP 10-308355 (JP, A) JP 10-200078 (JP, A) JP 9-307084 (JP, A) JP 7-249749 (JP, A) JP 7-86540 (JP, A) JP-A-4-115511 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/302

Claims (76)

(57) [Claims] 1. An etching method for etching a semiconductor substrate having a silicon surface, wherein the silicon surface of the semiconductor substrate is opposed to a plane made of silicon oxide at a predetermined interval. A method for etching a semiconductor substrate, comprising the step of: heat-treating the substrate in a reducing atmosphere containing hydrogen. 2. The method for etching a semiconductor substrate according to claim 1, wherein the semiconductor substrate is an SOI substrate having a single crystal silicon film. 3. The method for etching a semiconductor substrate according to claim 1, wherein a mean square roughness in a 1 μm square region of the surface made of silicon is 0.2 nm or more. 4. The method for etching a semiconductor substrate according to claim 1, wherein the silicon surface is an unpolished surface. 5. The method for etching a semiconductor substrate according to claim 1, wherein the silicon surface has a rough surface caused by a porous Si layer. 6. The surface made of silicon before etching has a rough surface due to minute voids.
A method for etching a semiconductor substrate according to claim 1. 7. A semiconductor base material having the single crystal silicon film is bonded to a first silicon base material and a second base material having a separation layer for defining a separation position in advance, and the second base material is bonded to each other. 3. The semiconductor substrate according to claim 2, which is an SOI substrate having a single crystal silicon film transferred to the second substrate by separating the substrate with a separation layer for defining the separation position. Etching method. 8. The method for etching a semiconductor substrate according to claim 7, wherein the separation layer is a layer into which an inert gas or hydrogen is ion-implanted. 9. The separation layer is a porous layer.
The method for etching a semiconductor substrate according to. 10. The method of etching a semiconductor substrate according to claim 2, wherein the semiconductor substrate has a buried oxide layer obtained by ion-implanting oxygen into a silicon wafer and heat-treating it. 11. In the etching step, the gas flow rate in the direction near the silicon surface in a direction parallel to the surface is set to be lower than the gas flow rate in a direction perpendicular to the surface of the outer peripheral portion of the semiconductor substrate. The method for etching a semiconductor substrate according to claim 1. 12. The method for etching a semiconductor substrate according to claim 11, wherein the treatment is performed such that the gas flow rate in the vicinity of the surface of the semiconductor substrate is substantially zero. 13. A silicon wafer having a silicon oxide film formed on the surface thereof is arranged so as to face the silicon surface of the semiconductor substrate, and heat treatment is performed until the silicon oxide film of the silicon wafer is etched to expose underlying silicon. The method for etching a semiconductor substrate according to claim 1. 14. The method for etching a semiconductor substrate according to claim 1, wherein a tray made of silicon oxide is provided so as to face the silicon surface of the semiconductor substrate. 15. The reducing atmosphere containing hydrogen is 10
The method for etching a semiconductor substrate according to claim 1, comprising 0% hydrogen, or hydrogen and an inert gas. 16. The method for etching a semiconductor substrate according to claim 1, wherein a dew point of the reducing atmosphere containing hydrogen is −92 ° C. or lower. 17. The method for etching a semiconductor substrate according to claim 1, wherein at least the surface of the member supporting the semiconductor substrate is made of a material containing silicon oxide as a main component. 18. The method of etching a semiconductor substrate according to claim 1, wherein the semiconductor substrate is arranged such that its surface is perpendicular to the main flow of the gas containing hydrogen in the container. 19. A plurality of semiconductor base materials having the silicon film are arranged in a container in parallel and coaxially at predetermined intervals,
The method for etching a semiconductor substrate according to claim 1, wherein a gas containing hydrogen is flowed around the semiconductor substrate so that the gas flow on the surface of the single crystal silicon film becomes substantially zero, and the heat treatment is performed. .. 20. The method of etching a semiconductor substrate according to claim 1, wherein a quartz plate is arranged so as to face the single crystal silicon film of the semiconductor substrate with a gas containing hydrogen interposed therebetween and heat treatment is performed. 21. The method according to claim 1, wherein silicon oxide is formed on the back surface of the semiconductor base material, and the back surface of the semiconductor base material is opposed to the silicon surface of another semiconductor base material through a gas containing hydrogen. A method for etching a semiconductor substrate according to claim 1. 22. The method for etching a semiconductor substrate according to claim 1, wherein the substrate is arranged in a container whose inner wall surface is made of silicon oxide. 23. The plurality of semiconductor base materials supported by a support member whose surface is made of silicon oxide are arranged in a container whose inner wall surface is made of silicon oxide so that the plurality of semiconductor base materials are parallel to each other. 1. The method for etching a semiconductor substrate according to 1. 24. The silicon surface has a thickness of 10 nm to 200 nm.
The method for etching a semiconductor substrate according to claim 1, wherein the etching is performed by removing about 1 nm by etching. 25. The method for etching a semiconductor substrate according to claim 1, wherein the etching rate of the silicon surface is 1.0 × 10 ⁻³ nm / min to 1.0 nm / min. 26. One of the silicon surfaces after etching
The method for etching a semiconductor substrate according to claim 1, wherein the average square roughness in a μm square region is 0.4 nm or less. 27. The method of etching a semiconductor substrate according to claim 1, wherein the thickness of the silicon oxide is at least 2.2 times the etching thickness of the silicon surface. 28. A plurality of the semiconductor base materials are coaxially arranged at a predetermined interval in the same direction, and a silicon oxide film is formed on the surface of the semiconductor base material so as to face the silicon surface of the top semiconductor base material. 24. The method for etching a semiconductor substrate according to claim 1, wherein a dummy substrate or a quartz wafer substrate having the above is arranged. 29. The single crystal silicon film presenting the silicon surface is an SOI formed by epitaxial growth.
It is a layer, The etching method of the semiconductor substrate in any one of Claims 2-23. 30. The method for etching a semiconductor substrate according to claim 2, wherein the single crystal silicon film presenting the silicon surface before etching has a thickness of 50 nm to 500 nm. 31. An opposing surface constituting member having a silicon oxide film formed on a surface of a supporting material is disposed so as to face the base material,
The method for etching a semiconductor substrate according to claim 1, wherein the heat treatment is performed for a time sufficient to expose the support material surface by etching the silicon oxide film. 32. The method for etching a semiconductor substrate according to claim 2, wherein the single crystal silicon film presenting the silicon surface after etching has a thickness of 20 nm to 250 nm. 33. The single crystal silicon film exhibiting the silicon surface having a thickness selected from the range of 50 nm to 500 nm is etched to a thickness of 20 nm to 250 nm. The method for etching a semiconductor substrate according to. 34. An etching apparatus for carrying out the etching method according to claim 1. 35. The etching apparatus according to claim 34, further comprising a quartz glass reactor capable of containing the semiconductor substrate and reducing the pressure. 36. In a method for manufacturing a semiconductor substrate having a silicon film, a step of bonding a first base material and a second base material having a separation layer for defining a separation position therein, and the bonding step. By separating the first and second base materials in the layer defining the separation position, the silicon film is separated into the second film.
The step of transferring the silicon film to the base material, and the silicon film transferred to the second base material with a plane made of silicon oxide facing the silicon film, and the silicon film is heat-treated in a reducing atmosphere containing hydrogen. Accordingly, an etching step of etching the surface of the silicon film, thereby producing a semiconductor substrate. 37. A method of manufacturing a semiconductor base material having a silicon film, the step of bonding a first base material and a second base material, and the step of bonding the first and second base materials to each other. A removal step of removing a part of the first base material leaving the silicon film on the second base material; and a flat surface made of silicon oxide facing the unpolished surface of the silicon film. An etching step of etching the surface of the silicon film by heat-treating the silicon film in a reducing atmosphere containing hydrogen,
A method for manufacturing a semiconductor substrate including: 38. The method for producing a semiconductor base material according to claim 36, further comprising the step of forming a silicon oxide film on the back surface of the second base material to provide a surface made of the silicon oxide. 39. The first base material having a non-porous single crystal silicon film formed on a porous silicon layer is prepared, and the non-porous single crystal silicon film is attached to a second base material,
38. The method for producing a semiconductor substrate according to claim 36, further comprising a step of removing the porous silicon before etching. 40. The fabrication of a semiconductor substrate according to claim 36, wherein the separation layer is a porous layer, and the etching step is performed after selectively etching the porous layer remaining on the silicon film after separation. Method. 41. The method for producing a semiconductor substrate according to claim 36, wherein the separation layer is a porous layer, and the etching step is performed in a state where the porous layer remains on the silicon film after separation. 42. The semiconductor substrate according to claim 36, wherein the separation layer is a layer into which an inert gas or hydrogen ions is implanted, and the etching step is performed without polishing the surface of the silicon film exposed after separation. Of manufacturing. 43. The method for producing a semiconductor substrate according to claim 37, wherein the removing step includes a step of removing the porous layer remaining on the silicon film. 44. The method for manufacturing a semiconductor substrate according to claim 37, wherein the porous layer remains on the silicon film after the removing step. 45. The surface of the silicon film after the removing step is a plasma-etched surface.
7. The method for producing a semiconductor substrate according to 7. 46. The method for producing a semiconductor substrate according to claim 36, wherein a mean square roughness in a 1 μm square region of the silicon film surface is 0.2 nm or more. 47. The surface of the silicon film is porous Si.
37. Having a rough surface due to a layer.
Or the method for producing a semiconductor substrate according to 37. 48. The separation layer is a layer in which an inert gas or hydrogen is ion-implanted.
The method for producing a semiconductor substrate according to. 49. The method for manufacturing a semiconductor substrate according to claim 36, wherein the separation layer is a porous layer. 50. In the etching step, a gas flow velocity in a direction parallel to the surface of the semiconductor substrate near the surface is
38. The method for producing a semiconductor substrate according to claim 36 or 37, wherein the treatment is performed so as to be smaller than the gas flow velocity in the direction perpendicular to the surface of the outer peripheral portion of the semiconductor substrate. 51. The method for producing a semiconductor substrate according to claim 50, wherein the treatment is performed such that the gas flow rate near the surface of the semiconductor substrate is substantially zero. 52. A silicon wafer having a silicon oxide film formed on a surface thereof is arranged so as to face the silicon film of the semiconductor substrate, and the silicon oxide film of the silicon wafer is etched to expose underlying silicon. The method for manufacturing a semiconductor substrate according to claim 36 or 37, characterized by performing heat treatment. 53. The method for producing a semiconductor substrate according to claim 36, wherein a tray made of silicon oxide is arranged so as to face the silicon film of the semiconductor substrate. 54. The reducing atmosphere containing hydrogen is 10
38. The method for producing a semiconductor substrate according to claim 36 or 37, which comprises 0% hydrogen or hydrogen and an inert gas. 55. The method for producing a semiconductor substrate according to claim 36, wherein a dew point of the reducing atmosphere containing hydrogen is −92 ° C. or lower. 56. The method for manufacturing a semiconductor substrate according to claim 36, wherein at least the surface of the member supporting the semiconductor substrate is made of a material containing silicon oxide as a main component. . 57. The semiconductor substrate according to claim 36, wherein the semiconductor substrate is arranged so that its surface is perpendicular to the main flow of the gas containing hydrogen in the container. How to make wood. 58. A plurality of semiconductor substrates having the silicon film are arranged in a container in parallel and coaxially at predetermined intervals,
38. The heat treatment is performed by causing a gas containing hydrogen to flow around the semiconductor substrate so that the gas flow on the surface of the silicon film becomes substantially zero.
The method for producing a semiconductor substrate according to. 59. The manufacturing of a semiconductor substrate according to claim 36, wherein a quartz plate is arranged so as to face the silicon film of the semiconductor substrate with a gas containing hydrogen interposed therebetween and heat treatment is performed. Method. 60. A silicon oxide is formed on the back surface of the semiconductor substrate, and the back surface of the semiconductor substrate is opposed to a silicon film surface of another semiconductor substrate via a gas containing hydrogen. The method for producing a semiconductor substrate according to claim 36 or 37. 61. The method for producing a semiconductor base material according to claim 36, wherein the base material is arranged in a container whose inner wall surface is made of silicon oxide. 62. A container having an inner wall surface made of silicon oxide, wherein the plurality of semiconductor base materials supported by a supporting member having a surface made of silicon oxide are arranged so that the plurality of semiconductor base materials are parallel to each other. 36. The method for producing a semiconductor substrate according to 36 or 37. 63. The surface of the silicon film has a thickness of 10 nm to 2 nm.
The method according to claim 36 or 3, wherein the film is removed by etching to a thickness of about 00 nm.
7. The method for producing a semiconductor substrate according to 7. 64. An etching mask for the surface of the silicon film.
1.0 x 10 ^-3nm / min to 1.0 nm / mi
The method for producing a semiconductor substrate according to claim 36 or 37, wherein n is n.
Law. 65. The method for producing a semiconductor substrate according to claim 36, wherein the mean square roughness of the surface of the silicon film after etching is 0.4 nm or less. 66. The method for producing a semiconductor substrate according to claim 36, wherein the thickness of the silicon oxide is 2.2 times or more the etching thickness of the surface made of silicon. 67. A plurality of the semiconductor base materials are coaxially arranged at predetermined intervals in the same direction, and are oxidized on the surface so as to face the surface of the silicon film of the top semiconductor base material. The method for manufacturing a semiconductor substrate according to claim 36 or 37, wherein a dummy substrate having a silicon film or a quartz wafer substrate is arranged. 68. The method for manufacturing a semiconductor substrate according to claim 36, wherein the single crystal silicon film is an SOI layer formed by epitaxial growth. 69. The silicon film before etching is 5
The method for producing a semiconductor substrate according to claim 36 or 37, which has a thickness of 0 nm to 500 nm. 70. The silicon film after etching is 2
The method for producing a semiconductor substrate according to claim 36 or 37, which has a thickness of 0 nm to 250 nm. 71. The silicon film having a thickness selected from the range of 50 nm to 500 nm is formed in the range of 20 nm to 2 nm.
The etching according to claim 36 or 3, wherein etching is performed to a thickness of 50 nm.
7. The method for producing a semiconductor substrate according to 7. 72. The method of etching a semiconductor substrate according to claim 1, wherein the temperature of the heat treatment is 300 ° C. or higher and the melting point of silicon or lower. 73. The method for etching a semiconductor substrate according to claim 1, wherein the temperature of the heat treatment is 800 ° C. or higher and the melting point of silicon or lower. 74. The method for producing a semiconductor substrate according to claim 36, wherein the temperature of the heat treatment is 300 ° C. or higher and the melting point of silicon or lower. 75. The method for producing a semiconductor substrate according to claim 36, wherein the temperature of the heat treatment is 800 ° C. or higher and the melting point of silicon or lower. 76. The flow velocity of the gas flowing in the outer peripheral portion of the semiconductor base material in the furnace is set to 10 cc / min · cm ² or more and 300 c or more.
The method for etching a semiconductor substrate according to claim 1, which is c / min · cm ² or less, or the method for producing a semiconductor substrate according to claim 36 or 37.