JPH11251563A - Method and furnace for heat treating soi substrate and production of soi substrate employing them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make smooth the surface constantly and uniformly even when a plurality of substrates are processed by heat treating an SOT substrate in reducing atmosphere while facing the plane of a material principally comprising nonoxidative silicon through a specified interval thereby facilitating suppression of etching. SOLUTION: A facing area composing member 3 having a plane 4 of a material principally comprising nonoxidative silicon is arranged on the side of the surface to be treated of an SOI basic material W through a specified interval AS. The materials W and the member 3 are contained in a reaction furnace 1 which is then evacuated through an evacuation pump 8 and heated by means of a heater 2. Subsequently, hydrogen gas is introduced from a gas source 5 and the temperature in the furnace and of the material is sustained at a specified level by controlling the heating value of the heater 2. Residual oxygen and moisture in the atmosphere are suppressed because the surface of silicon is oxidized upon temperature rise to form a coating thus impeding smoothing of the surface. Surface of a single crystal silicon film is thereby flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a heat treatment method for an SOI substrate, a heat treatment apparatus, and a method for manufacturing a semiconductor substrate.
More specifically, the present invention relates to a heat treatment method, a heat treatment apparatus, and a method for manufacturing an SOI substrate of an SOI substrate having a silicon film.

[0002]

2. Description of the Related Art In a silicon-based semiconductor device and an integrated circuit technology, a semiconductor-on-insulator (SOI) structure, that is, a device using a single crystal semiconductor film on an insulating film has a reduced parasitic capacitance and excellent radiation resistance. As a technology that can increase the speed, lower the voltage, lower the power consumption, increase the integration of the transistor, and reduce the total cost, including simplification of the process including elimination of the well process, by facilitating element isolation, etc. Numerous studies have been done so far.

As a substrate having an SOI structure (SOI substrate), after oxidizing the surface of an SOS (silicon on sapphire) or Si single crystal substrate, a window is opened to partially expose the Si substrate, and the portion is used as a seed. A substrate formed by epitaxially growing laterally and forming a Si single crystal film (layer) on SiO ₂ , a substrate using a Si single crystal substrate itself as an active layer and forming a silicon oxide film thereunder, a thick polycrystalline Si layer A substrate having a Si single crystal region which is dielectrically separated and surrounded by a V-groove on the upper surface thereof by a FIPOS method (Full is
Olation by poor Silico
n) by dielectric separation by oxidation of porous Si
An OI substrate or the like.

Recently, as an SOI formation technique, an oxygen implantation method (SIMOX: Separation by I
(planted Oxygen) and the wafer bonding method have become mainstream. SIMOX was reported in 1978 (K. Izumi, M. Doken, and
H. Ariyoshi, Electron. Lett.
14 (1978) p. 593). This is a method in which oxygen is ion-implanted into a silicon substrate and then heat treatment is performed at a high temperature to form a buried silicon oxide film.

In the SOI formation by the bonding method, there are many variations in a method of thinning one wafer after bonding.

(BPSOI) The most basic technique uses polishing. After a silicon oxide layer is formed on both or one of the two wafers, they are bonded to each other. Thereafter, one of the wafers is thinned by grinding and polishing.

(PACE) Plasma was developed to improve the uniformity of the thickness of the SOI layer obtained by polishing.
assisted chemical etch
g method (PACE) method. The film thickness is measured in advance at a high-density measuring point of several thousand points on the wafer. Next, a plasma source having a diameter of several mm is scanned at a scanning speed corresponding to the film thickness distribution, and the etching amount is changed in accordance with the film thickness distribution, thereby improving the film thickness distribution.

(Hydrogen implantation stripping method) Recently, (M. Blue
1, Electronics Letters, 31
(1995) p. 1201) A new bonding S is disclosed in JP-A-5-211128, US Pat. No. 5,374,564.
OI was reported. In this method, an ion-implanted wafer is bonded to the entire surface of a wafer in which light elements such as hydrogen and inert gas have been oxidized in advance, and heat treatment is performed. Then, the wafer is peeled at the ion-implanted depth during the heat treatment. As a result, a layer above the projection range of the ion implantation is transferred to the other wafer, and an SOI structure is formed.

(Epitaxial layer transfer method) Patent No. 260
No. 8,351, US Pat. No. 5,371,037 discloses an excellent SOI in which a single crystal layer on a porous layer is transferred to another substrate.
A method for manufacturing a substrate has been proposed.

This method is called "ELTRAN (registered trademark)".
Also called. (T. Yonehara, K. Sak
aguchi, N .; Sato, Appl, Phys. L
ett. 64 (1994), p. 2108) In the field of such an SOI substrate, removing surface roughness introduced by etching, ion implantation, heat treatment subsequent to ion implantation, or the like to smooth the surface;
In addition, removing the high-concentration boron diffused in the single-crystal layer to form an SOI layer made of a silicon film having a low boron concentration is intended to improve device characteristics such as improvement of gate oxide film breakdown voltage and carrier mobility of MOSFET. A method for overcoming this problem has been proposed for each SOI substrate manufacturing method.

In the hydrogen implantation delamination method, the surface after the wafer is separated in the projected range of the ion has a mean square roughness (Rrms).
Has a roughness of 10 nm, has ion implantation damage to the surface layer, and smoothes and removes the implant damage layer by slightly removing the surface layer by polishing called touch polishing (M. Bruel, et. al. Proc.
95 IEEE Int. SOI Conf. (199
5) p. 178).

In the case of the PACE method, the surface immediately after plasma etching has a peak-to-valley surface roughness of 10.66 nm measured by an atomic force microscope. This roughness is smoothed to 0.62 nm, which is the same as the original surface, by a very small amount of polishing called touch polish. (T. Feng, M. Matrubian,
G. FIG. J. Gardopee, and D.M. P. Math
ur, Proc. 1994 IEEE Int. SOI
Conf. (1994) p. 77. ).

In the BESOI method, in order to remove a surface roughness of about 5-7 nm in peak-to-valley generated after etching, it is necessary to remove a thickness 3 to 5 times the thickness, that is, 20 to 30 nm. As a result of this polishing, the film thickness uniformity averaged 0.005 μm (= 5n
m), the uniformity is degraded.

That is, even in a small amount of polishing called a touch polish or a kiss polish, at the same time as the surface roughness is removed, the film thickness is necessarily reduced, and as a result, the film thickness uniformity may be deteriorated. . Generally, the end of polishing is controlled by time, but even within the same polishing time, in-plane or inter-plane depending on the polishing liquid, the temperature of the platen at the time of polishing, and the degree of deterioration of the polishing cloth. It is known that the polishing amount between batches fluctuates,
It is extremely difficult to control the polishing amount to be constant. In particular, a phenomenon that the polishing amount on the outer periphery of the wafer is increased is known.

When boron is diffused at a high concentration throughout the thickness of the SOI layer, the concentration cannot be reduced by polishing.

The surface roughness of the SOI layer manufactured by the SIMOX method using oxygen ion implantation is about one digit larger than that of the bulk. S. Nakashima, K .; Izu
mi (J. Mater. Res. (1990) Vol.
5, No. 9, p. 1918), 1260 ° C
It is reported that the heat treatment of 2 hours (in nitrogen) or 4 hours at 1300 ° C. (0.5% oxygen containing argon) eliminates the roughness of the SIMOX substrate in which countless tens of nm-diameter dents are present. On the other hand, heat treatment at 1150 ° C. does not change the surface roughness. However, in such a high-temperature heat treatment exceeding 1200 ° C., it is difficult to use a quartz tube from the viewpoint of heat resistance. Also, the high temperature process increases the introduction of slip lines as the wafer size increases.

In the oxygen implantation method, boron contained in clean room air adheres to the substrate surface,
In addition, boron may be implanted at the same time as the oxygen implantation, or boron attached before the high-temperature heat treatment for converting the ion-implanted oxygen into the buried silicon oxide layer may be diffused throughout the silicon layer by the heat treatment. Boron contained in the air in the clean room may cause the same problem in the bonded SOI.

JP-A-5-218053, JP-A-5-218053
Japanese Patent Application No. 217821 proposes that the surface of an SOI substrate is smoothed by performing a heat treatment in an atmosphere containing hydrogen.

Even if a rough surface such as the etched surface of the SOI substrate has a rough surface as compared with a commercially available polished silicon wafer, it is smoothed by hydrogen annealing, and the surface of the commercially available polished silicon wafer (polishing). Surface) is improved to the same level. Simultaneously, by annealing a substrate having a single-crystal silicon film formed on an insulator on its surface in hydrogen, boron in the single-crystal silicon film is outwardly diffused into a gaseous phase so that boron in the single-crystal silicon film is removed. The concentration is reduced. Although the diffusion rate of boron in silicon is relatively fast,
In a heat treatment in an oxidizing atmosphere or a heat treatment in an inert gas, the diffusion rate of boron in a silicon oxide layer such as a natural oxide film formed on the surface is low, so that boron is confined in the silicon layer. Up to. However, by annealing in a reducing atmosphere containing hydrogen or the like, the silicon oxide film on the surface of the SOI layer serving as the diffusion barrier can be removed, and the re-formation of the oxide film during the process can be suppressed. Out diffusion is promoted and SOI
Even when a high concentration of boron exists in the entire layer, the impurity concentration of the entire SOI layer can be reduced to a level at which device fabrication is possible by out-diffusion (N. Sato).
and T. Yonehara, Appl. Phys
s. Lett. 65 (1994) p. 1924).

The heat treatment in an atmosphere containing hydrogen is an extremely effective method for realizing the outward diffusion of boron in the silicon layer and the smoothness of a large roughness of the silicon surface.

The heat treatment in an atmosphere containing hydrogen is, of course, suitable for SOI substrates by the SIMOX method, and the above-mentioned paper reports that the roughness can be smoothed by heat treatment at 1200 ° C. or less in a hydrogen atmosphere.

When the SOI substrate is annealed with hydrogen, the reduction rate of the film thickness is 0.08 nm / m at 1150 ° C.
Very small compared to in and polishing.

However, instead of the SOI substrate, bulk Si
When hydrogen annealing the wafer, B. M. Gallo
iset al. J. Am. Ceram. Soc. , 7
7 (1994) pp. 2949 has 10-100 nm
A relatively large reduction rate of / min has been reported.

[0024]

If the reduction rate and the amount of etching cannot be controlled, the uniformity of the film thickness within the wafer surface after heat treatment and between a plurality of wafers tends to deteriorate.

The variation in the thickness of the SOI layer on the SOI substrate depends on the device characteristics, especially on a fully depleted SOI-MOS.
Since the characteristics such as the threshold voltage of the transistor are greatly affected, it is extremely important to control the film thickness with high accuracy both within the wafer and between the wafers.

In addition to the above-mentioned uniformity of the film thickness, there are some requirements for the SOI substrate.

The required thickness of the SOI layer varies depending on the characteristics of various semiconductor devices manufactured using the SOI substrate. Therefore, it is preferable in terms of the design of the SOI substrate that the thickness of the SOI layer in the SOI substrate does not change due to the heat treatment.

[Object of the Invention] An object of the present invention is to provide a heat treatment method, a heat treatment apparatus, and a heat treatment method that can easily suppress etching and can always provide uniform surface smoothness even when a plurality of substrates are treated.
An object of the present invention is to provide a method for manufacturing an OI substrate.

Another object of the present invention is to provide a heat treatment method, a heat treatment apparatus, and a method for manufacturing an SOI substrate which can efficiently reduce impurities such as boron contained in a film while maintaining uniformity of the film thickness. It is in.

Still another object of the present invention is to provide a heat treatment method, a heat treatment apparatus, and a method for manufacturing an SOI substrate, which can reduce variation in characteristics of a device manufactured using a semiconductor substrate.

Still another object of the present invention is to provide a low-cost heat treatment method, a heat treatment apparatus, and a method for manufacturing an SOI substrate which can easily obtain an arbitrary film thickness and have few surface defects.

[0032]

The essence of the present invention is to provide a method for heat-treating an SOI substrate having a silicon surface, the method comprising:
A heat treatment method, a heat treatment apparatus, and a method for manufacturing an SOI substrate including a step of heat-treating the SOI substrate in a reducing atmosphere containing hydrogen in a state where the OI substrate is opposed to the OI substrate at a predetermined interval.

[0033]

FIG. 1 is a schematic diagram showing a heat treatment apparatus according to a preferred embodiment of the present invention.

This heat treatment apparatus includes an exhaustible reaction furnace 1 constituting a heat treatment chamber (vessel) for accommodating a semiconductor substrate (SOI substrate) W, and a heat treatment chamber 1 for heating the substrate W and gas in the furnace 1. A heater 2 and at least one hydrogen gas source 5
It is connected via two valves 6 and connected to an exhaust pump 8 via at least one valve 7.

On the surface to be treated of the substrate W, an opposing surface constituting member 3 having a flat surface 4 of a material mainly composed of non-oxidized silicon on its surface is arranged at a predetermined distance AS from the substrate W. I have. 9 is a support for supporting the base material W and the opposing surface constituting member 3.

The heat treatment method according to the present embodiment is as follows.

First, the substrate W and the facing surface constituting member 3 are accommodated in the reaction furnace 1, and the inside of the furnace is evacuated by the exhaust pump 8 to reduce the pressure. Then, heating is performed by the heater 2.

Next, hydrogen gas is introduced from the gas source 5 into the furnace. The amount of heat generated by the heater 2 is controlled to maintain the inside of the furnace and the temperature of the substrate W at a predetermined temperature.

Then, the silicon on the surface of the substrate W (the surface to be processed) is annealed.

The substrate (SOI substrate) W to be heat-treated according to the present invention is bulk Si formed by a CZ method or the like.
Various types of S described above manufactured using a wafer, an epitaxial Si wafer having an epitaxially grown layer, and a Si wafer obtained by subjecting a bulk Si wafer to hydrogen annealing.
An OI wafer, a quartz glass substrate having a silicon film, and the like can be cited. Among them, an SOI wafer having a surface which is subjected to some surface treatment after polishing, an SOI wafer having an unpolished surface, a lamination, etc. A SOI wafer or the like in the middle of a manufacturing process by the SIMOX method or the SIMOX method is a suitable base material.

In the present invention, since the substrate W is subjected to the heat treatment in a reducing atmosphere containing hydrogen, the gas supplied into the furnace is 100% hydrogen gas or an inert gas such as a rare gas. Hydrogen gas or the like diluted to about 99% is used. Especially in a furnace that has been sufficiently dehydrated so that the dew point of the reducing atmosphere containing hydrogen is -92 ° C or less,
A relatively high purity gas may be introduced through a hydrogen purifier.

Since the residual oxygen and moisture in the atmosphere oxidize the silicon surface at the time of raising the temperature and hinder the smoothing of the surface as a film, it is necessary to keep the oxygen and moisture low. At a high temperature, an unexpected decrease in the silicon film thickness is caused by the oxidation and the etching action. Therefore, it is desirable to control the atmosphere so that the dew point is −92 ° C. or less as described above.

As the pressure of the reducing atmosphere containing hydrogen,
Atmospheric pressure of any of pressurization, atmospheric pressure, and reduced pressure may be used, but preferably atmospheric pressure or lower.

In order to improve the surface smoothing effect and the effect of out-diffusion of impurities, the pressure is preferably lower.

When an etching furnace made of fused quartz is used, the lower limit of the pressure is 3.9 to prevent deformation of the furnace.
× preferably from 10 ^-4 Pa is more preferable to the 6.6 × 10 ^-4 Pa.

In consideration of the above points, atmospheric pressure to 1.3
It would be reasonable to select from the range of Pa according to the use environment.

The flow rate of the gas containing hydrogen used in the present invention is not particularly limited. However, it is more preferable to obtain the flow rates described below.

The flow velocity refers to the velocity of gas passing through a region excluding the sectional area of the semiconductor substrate from the sectional area of the furnace tube.

If the flow rate is too high, the removal rate of the reaction product from the surface of the base material increases, and the effect of suppressing the etching decreases. On the other hand, if the flow rate is too slow, the removal of reaction products will be significantly reduced, and the ability of the semiconductor single crystal layer to remove impurities such as boron by outward diffusion will be reduced.

In the present invention, the flow rate is 10 cc / min.
Cm ² -300 cc / min · cm ^2, more preferably 30 cc / min · cm ² -150 cc / min · cm
² . The flow rate is a parameter that controls the rate at which the reaction products on the substrate surface diffuse to the side of the substrate and are removed.

In an atmosphere containing hydrogen, a nitrogen atmosphere,
In a rare gas atmosphere, 1200
Even at a temperature of not more than ° C., the surface is sufficiently smoothed together with etching. The temperature at the time of etching having the smoothing action according to the present invention depends on the composition and pressure of the gas. Specifically, the lower limit of the temperature is about 300 ° C. or higher, preferably 500 ° C. or higher, and more preferably 800 ° C. or higher. The lower limit of the temperature is equal to or lower than the melting point of Si. In particular, 1200 ° C. or lower is effective. When the progress of the smoothing is slow, a smooth surface can be obtained similarly by extending the heat treatment time.

As the facing surface constituting member 3 used in the present invention, any material may be used as long as a material mainly composed of non-oxidized silicon is formed on at least the facing surface side.
Preferably, a Si wafer having a non-oxidized silicon film such as silicon nitride or silicon carbide formed on the surface of a Si wafer from which a natural oxide film has been removed, a quartz glass wafer having a non-oxidized silicon film such as Si, SiN or SiC formed on the surface, or the like If there is a non-oxide silicon film on the facing surface side, it is also preferable to use a wafer having the same structure as the substrate to be heat-treated.

The surface to be processed should be flat and parallel to the surface to be processed. Further, the size and shape of the facing surface are the same as or larger than the surface to be processed of the substrate W, and those having substantially the same shape as the substrate are preferably used.

Further, it is preferable that the opposing surface constituting member is also used as a support for the base material, for example, a tray or the like.

The distance between the opposing surface and the substrate, that is, the distance of the distance AS depends on the size of the silicon surface (annealed surface) of the semiconductor substrate. When the thickness is 20 mm or less, more preferably 10 mm or less, an effect of suppressing etching due to interaction with the facing surface material can be obtained. The lower limit of the distance is not particularly limited, but is preferably 1 mm or more, more preferably 3 mm or more. This phenomenon starts when heat treatment is performed with the surface clean, so if a thick native oxide film is formed on the surface of the base material, dilute hydrofluoric acid is added before heat treatment. By removing the surface by etching, etc., the starting point of smoothing the surface is advanced.

The smooth silicon surface thus obtained is
It can be suitably used from the viewpoint of semiconductor device production.

In the present invention, it is easy to obtain a thin SOI layer having a thickness of 450 nm or less, particularly a very thin SOI layer having a uniform thickness of 20 nm to 250 nm.

Then, the obtained surface is smoothed, and for example, Rrms in a 1 μm square area is at least 0.4.
nm or less, preferably 0.2 nm or less, and more preferably 0.15 nm or less.
nm or less can be easily achieved.

The method of gas introduction is not limited to the method shown in FIG. 1, and it is preferable to adopt various forms described later.

As a constituent material of the reaction furnace 1, it is preferable to use a material whose inner surface at least near the substrate W is made of non-oxidized silicon, for example, a SiC reaction tube. As the heater 2, a resistance heater, a high-frequency heater or a lamp is used.

Here, the knowledge which motivated the present invention will be described.

(Knowledge Regarding Difference in Etching Amount Due to Opposing Material) The present inventors have studied heat treatment conditions in a reducing atmosphere containing hydrogen which can remove minute roughness on the surface of a silicon single crystal. It has been found that the etching rate of crystalline silicon varies greatly depending on the material of the surface (opposing surface) facing the single crystal silicon surface.

FIG. 2 is a diagram showing the temperature dependence of the etching rate due to the material of the facing surface. The lower horizontal axis shows the reciprocal of the temperature T. The upper horizontal axis indicates the temperature corresponding to 1 / T. The vertical axis is the etching rate (nm / min)
Is plotted logarithmically. When an SOI substrate is used, the SOI layer can be relatively easily formed using a commercially available light reflection type film thickness gauge.
That is, the thickness of the single crystal silicon layer over the buried insulating film can be measured. The amount of change in film thickness before and after the heat treatment is measured while changing the heat treatment time, and the slope with respect to the etching time is obtained, whereby the etching rate can be obtained.

The data A in the figure shows the etching rate at each temperature with the SiO ₂ substrate facing the Si-facing surface. At this time, the activation energy was obtained from the slope of the approximate straight line by the least square method of these plots. was determined the E _a, it was about 4.3eV.

Data B shows the case where the heat treatment was performed with the Si substrate facing the SiO ₂ facing surface.

[0066] The data C is a case where the heat treatment so as to face the Si substrate on the Si facing surface, this time, the activation energy E _a was about 4.1 eV.

[0067] The data D is, SiO ₂ and SiO ₂ substrate
A case where the heat treatment to face the opposing surface, this time, the activation energy E _a was about 5.9 eV.

As shown in FIG. 2, in the heat treatment in the hydrogen atmosphere, the etching rate of silicon is changed by changing the material of the facing surface from silicon to silicon oxide, as shown by the difference between the etching rates of B and C in the figure. It was found that the speed was increased by about 9 times regardless of the temperature.

When single-crystal silicon is opposed to each other, the etching rate is about 0.045 nm at 1200 ° C.
/ Min or less (C in the figure). The etching amount in the heat treatment for 60 minutes is 3 nm or less. On the other hand, when the silicon facing surface is made of silicon oxide, the etching rate is about 0.36 nm / min at 1200 ° C. (B in the figure), and the amount of etching per hour reaches 21.6 nm. This etching amount is close to the removal amount by touch polishing.

FIG. 3 is a diagram showing the etching amount when Si and SiO ₂ are opposed to each other. The horizontal axis represents the etching time (minute), the vertical axis represents the etching thickness (nm), and the temperature T is 1200. In ° C., open circles indicate that the SiO ₂
This is the case where heat treatment is performed so as to face the facing surface.
This shows a case where the heat treatment is performed with the i-base material facing the SiO ₂ facing surface.

As shown in FIG. 3, at the same time, when the heat treatment was performed with the SiO ₂ substrate indicated by the white circle facing the Si-facing surface, the Si substrate indicated by the black circle was opposed to the SiO ₂ -facing surface. The amount of etching is larger than that in the case where the etching is performed by the etching. In other words, when heat treatment is performed with SiO ₂ and Si facing each other, the SiO ₂ is removed by etching thicker.

FIG. 4 shows a structure in which the opposite surface is made of SiO._Two No
And the opposite surface is SiO_Two Si etching
In, the Si surface and SiO_Two Each side of the surface is etch
FIG. 3 shows the number of Si atoms removed by
The horizontal axis indicates the etching time.
The vertical axis represents the number of atoms of Si removed (atoms / cm
^Two ), In which white circles, triangles, and squares represent SiO_Two 
The black circles, triangles, and squares indicate the Si surface.

As shown in FIG. 4, when the etching amount of the silicon oxide surface and the single-crystal silicon surface shown in FIG. 3 was converted into the number of silicon atoms, the results were almost the same as shown in FIG. . When heat treatment was performed with Si and SiO ₂ facing each other, it was found that almost the same amount of Si atoms was lost from both surfaces.

That is, the etching rate of silicon is increased by the interaction with the opposing silicon oxide surface, and the reaction formula is as follows, and silicon and silicon oxide react 1: 1.

Si + SiO ₂ → 2SiO Further, the etching rate of Si is affected by the distance from the opposing surface. When silicon is disposed on the facing surface, the etching speed is suppressed as the distance between the surfaces is reduced. On the other hand, when silicon oxide was disposed as the opposing surface, it was found that the etching speed was increased as the distance between the surfaces became shorter.

The reduction of the atmosphere gas represented by hydrogen is
Hydrogen etching rate when hydrogen is not included
It was significantly smaller than the case. That is, the speed increase
The presence of a reducing gas typified by hydrogen is
I am giving. When silicon and silicon oxide face each other,
Etching is performed by removing any surface material represented by hydrogen.
Reacts with the primary gas to reach the other surface and reacts
In response, both surfaces are etched. example
If Si + H_Two → SiH_Two , SiH_Two + SiO _Two → 2S
iO + H_Two There is a reaction. S dissociated from Si surface
i atoms are transported in the gas phase and SiO 2
_Two And converted into SiO having a high saturated vapor pressure. S
iH_Two Is consumed from time to time, so etching on the Si surface
Promoted. When Si is opposed to each other,
When the dissociated Si atoms reach the saturation concentration in the gas phase,
Subsequent reactions are governed by diffusion in the gas phase. this
Time, since the saturated concentration of dissociated Si is not high,
The speed is hardly increased.

On the other hand, SiO is used for Si._Two When facing
Si atoms dissociated from the Si surface are
Because it is consumed, the reaction proceeds further without being suppressed. S
iO _Two Since SiO generated on the surface side has a high vapor pressure,
The reaction is rate-limiting compared to the case where Sis face each other.
Peg.

Further, when the material of the surface facing the single crystal silicon film was silicon carbide, the etching amount of the single crystal silicon film was almost the same as when the facing surface was silicon. Similarly, when the material of the facing surface was silicon nitride, the etching amount of the single crystal silicon film was similarly suppressed as in the case where the facing surface was silicon.

That is, when the Si film is heat-treated in a reducing atmosphere containing hydrogen, the opposite surface is not made of silicon oxide, but is made of a material mainly containing one of silicon, silicon and carbon, and silicon and nitrogen. Use a material that does not contain oxygen as its main component. In short, by forming the facing surface with a material that does not react with silicon via the atmosphere, the etching rate of the silicon film is reduced to at least 1/10 or less as compared with the case where silicon oxide is used as the facing surface. That is, the etching amount can be substantially reduced to zero.

(Heat Treatment Apparatus) A typical example of the heat treatment apparatus used in the present invention is as shown in FIG. 1, but various modifications may be made as described below.

FIG. 5 shows a heat treatment apparatus according to another embodiment.

In the apparatus shown in FIG. 5, a part of the gas containing hydrogen from the gas source 5 passes through the space between the base material W and the facing surface constituting member 3, that is, through the working space AS, to the exhaust pump 8. It is configured to flow.

The method of arranging the base material W and the facing surface constituting member 3 is limited to being parallel to the longitudinal direction (horizontal direction in the figure) of the furnace tube constituting the furnace 1 as shown in FIG. It does not need to be done, and may be as shown in FIG. Alternatively, as described later, the base material W and the member 3 may be arranged in a horizontal furnace at an angle, or may be arranged upright.

Further, a plurality of substrates W may be arranged in parallel in a furnace so as to be spaced apart from each other.

FIG. 6 shows a heat treatment apparatus that can heat-treat such a plurality of substrates at once.

The base material W1, whose surface is made of non-oxidized silicon,
W is arranged so that all of them face upward. At this time,
Since there is no facing surface on the surface of the base material W1 at the top,
Desired heat treatment is not performed on the surface of the substrate W1. Therefore, in this case, the base material W1 functions as a dummy base material. Except for the uppermost base material W1, the other base materials W are opposed to the back surface made of non-oxidized silicon of the base material W on which the upper surfaces are respectively located.
Annealed with little etching.

When all the substrates W1 and W are arranged downward, the lowermost substrate is the dummy substrate.

FIG. 6 shows a main part of the configuration of a so-called vertical furnace. If this is turned sideways, a horizontal furnace can be obtained in which a plurality of base materials can be annealed at once.

The apparatus shown in FIG. 6 cannot anneal a plurality of substrates at once unless the substrate having the back surface made of non-oxidized silicon is processed.

FIG. 7 shows an example in which the present invention can be applied to an SOI wafer having a silicon oxide film formed on the back surface or a substrate having silicon oxide on the back surface such as a substrate made of quartz glass. .

That is, by interposing the opposing surface constituting member 31 at least the back surface of which is made of non-oxide silicon between the two base materials, the Si surface of the base material W2 is made of the back surface (the opposing surface) of the member 31 made of non-oxide silicon. 4).
With this configuration, the Si surface of the base material W2 is annealed without being etched.

In FIG. 7, the shape of the member 31 is processed into a tray shape for holding the base material. However, the shape is not limited to such a shape and may be a simple plate shape. This member can be made of SiC, Si, or the like. Further, the surface of a base material made of quartz glass may be coated with Si, SiC, SiN or the like.

In any case, the distance from the opposing surface is 1
In the case of a semiconductor substrate having a thickness of 00 mm or more, if the thickness is approximately 20 mm or less, and more preferably 10 mm or less, an effect of suppressing etching due to interaction with the facing surface material is obtained.

The etching rate of silicon on the main surface (surface) of the substrate in the heat treatment step in a reducing atmosphere containing hydrogen is increased by the presence of oxidizing impurities such as moisture and oxygen contained in the atmosphere gas. Speeded up. If the flow rate of the atmospheric gas near the main surface is reduced to suppress the supply of moisture and oxygen, the amount of etching by these impurity gases decreases. In this way, the etching due to the mutual effect with the non-oxide silicon facing surface is suppressed. In particular, as shown in FIG. 8, the surface of the base material W installed in the furnace tube 1 is arranged so as to be orthogonal to the gas flows 11 and 14, and the opposing surface 4 made of non-oxidized silicon is separated by a distance. If the distance is set to 20 mm or less, the flow rate 12 of the atmospheric gas on the surface can be made substantially zero, and the etching effect by the opposed silicon oxide can be sufficiently obtained.

In FIG. 8, a silicon substrate 2 is used as the base material W.
1. A buried insulating film 22 and an SOI layer 2 made of silicon
An example is shown in which an SOI substrate having an N.3 and an opposing surface component 3 made of a silicon substrate from which a natural oxide film has been removed are used.

FIG. 9 is a modification of the heat treatment apparatus having the vertical furnace shown in FIG.

The four base materials W and the dummy base material W1 are coaxially arranged and held on the projection of the boat 13 as a support.

Here, an example is shown in which an Si substrate having no silicon oxide film formed on the front and back surfaces is used as the dummy base material W1, and an SOI substrate having no silicon oxide film formed on the back surface is used as the base material W. ing.

Also in this example, the flow rate of the gas passing through the region (outer peripheral portion) excluding the cross-sectional area of the semiconductor substrate from the cross-sectional area of the furnace tube is 10 cc / min · cm ^{2 to} 300 cc.
/ Min · cm ² , the gas flow rate 12 in the direction parallel to the surface of the substrate W near the surface of the substrate W becomes smaller than the gas flow rate 11 in the direction perpendicular to the surface at the outer peripheral portion of the substrate W. Like that.

Further, the flow rate 11 in the region (outer peripheral portion) excluding the cross-sectional area of the semiconductor base material from the cross-sectional area of the core tube is 30 cc / m.
in the ^{in · cm 2 ~150cc / min ·} cm 2 or so, near the center of the flow rate 12 of gas on the surface of the substrate W may substantially zero.

FIG. 10 shows still another heat treatment apparatus according to the present invention.

This heat treatment apparatus includes an inner tube 31 having an inner surface made of non-oxidized silicon such as SiC, a furnace tube 132 made of quartz glass such as fused quartz, and a jacket having a surface made of non-oxidized silicon such as SiC. And a tube 145. 124, 125, 147 are O-rings, 12
Reference numeral 2148 denotes a flange. 126 is a closed lid.

Then, the hydrogen-containing reducing gas is introduced into the space in which the wafer W is arranged from the lower inlet 105 through the flow path 141. This gas passes from the opening 135 through a check valve (136, 137) such as a check valve.
It flows into the flow path 142 between the core tube 132 and the inner tube 131. Then, the gas in the flow path 142 is exhausted from the exhaust port 106.

The space 143 between the furnace tube 132 and the sealed mantle tube 145 has a lower purge gas inlet 146.
As a result, an inert gas such as He, Ar, Ne, N ₂ , Ku, or Xe is introduced and exhausted from the upper purge gas exhaust port 144.

The hydrogen gas does not come into contact with the silicon oxide heated to 1000 ° C. or higher until it is introduced into the high-temperature region of the space where the wafer W is placed. That is, since the heat barrier 109 made of foamed silica, which is silicon oxide, is outside the high-temperature heating area 150 by the heater 2, even if hydrogen gas is supplied through the flow path 141, almost no moisture is generated, and Incorporation into negligible is negligible.

In the high temperature heating region 150 and the inner tube 13
1, the inner surface of the space in which the wafer is arranged, that is, the inner surface that is in contact with the high-temperature region, is entirely made of a non-oxidized silicon material such as SiC, so that the generation of moisture is also suppressed here.

Since the gas in the inner pipe 131 is discharged from the opening 135 at the center of the pipe, a uniform gas flow can be obtained.

Since the furnace tube is a sealed tube made of silicon oxide such as fused quartz, it has an excellent heat insulating effect and makes the temperature inside the high-temperature heating region 150 uniform. Also, inner tube 1
Even if hydrogen leaks from 31, it does not leak out of the furnace tube 132.

Since the boat 13 for holding the wafer W also has a surface made of non-oxidized silicon such as SiC,
Does not generate moisture.

With the sealed mantle tube 145 and the purge gas,
Metal impurities from the heater 2 are prevented from entering the inner tube.

The upper part of the boat 13 is provided with a flat surface made of non-oxidized silicon such as SiC, which is opposed to the uppermost wafer W, and suppresses the etching of the uppermost wafer W.

The back surface of the wafer W is shown on the back surface made of non-oxidized silicon by removing the oxide film to expose Si, or by covering it with a film of non-oxide silicon. In each of the heat treatment apparatuses described above, similarly to the apparatus of FIG.
For example, a material having a surface made of non-oxide silicon, for example, a material made of SiC, Si, SiN, or the like may be used instead of a material made of quartz glass or the like.

As the heater 2, a resistance heater, a lamp heater, a high-frequency heater, or the like is used.

Further, a load lock chamber for accommodating an inert gas and accommodating a wafer is attached to the furnace, and the inert gas in the load lock chamber is removed from the inert gas atmosphere in the furnace without exposing the furnace to an oxidizing atmosphere. It is preferable to load the wafer into the atmosphere.

(Method of Manufacturing SOI Substrate) Next, a method of manufacturing an SOI substrate using the heat treatment method of the present invention will be described.

FIG. 11 shows a hydrogen implantation separation method, a PACE method,
Bonded SOI represented by epitaxial layer transfer method
4 shows a flowchart of a method for manufacturing a substrate.

First, in step S1, a first base material is prepared. For example, Si with an insulating film having at least one surface oxidized
Hydrogen ions or rare gas ions are implanted into the wafer to form a separation layer (latent layer) at a predetermined depth. Or S
After the surface of the i-wafer is made porous, a non-porous Si layer is epitaxially grown.

In the case of the PACE method, Si without an oxide film is used.
A wafer or a Si wafer whose surface has been oxidized is prepared.

On the other hand, in step S2, a second base material is prepared. For example, a normal Si wafer whose surface is oxidized, a Si wafer from which a natural oxide film is removed, a quartz glass wafer, a metal substrate, and the like are prepared.

Subsequently, in step S3, the above steps S1, S
The first and second base materials prepared in 2 are bonded directly or indirectly via an adhesive layer therebetween.

At this time, it is better if at least one of the bonding surface of the first base material and the bonding surface of the second base material is formed of an insulator. Needless to say, when a substrate other than the SOI structure is manufactured.

Furthermore, before bonding, the bonding surface made of an insulator may be irradiated with ions of hydrogen, oxygen, nitrogen, or a rare gas to activate the bonding surface.

Next, in step S4, the first
And removing a part (unnecessary part) of the first base material from the second base material (assembly). The removal method is roughly divided into 2
There are various types, and one is a method of removing a part of the first base material from the back surface of the first base material by grinding and / or etching or the like. The other is a method of separating the back side portion and the front side portion of the first base material in the separation layer formed on the first base material. According to the latter method, since the unnecessary portion maintains the wafer shape, it can be used again as the first base material or the second base material. As a separation method,
There are a method of heat treatment, a method of spraying a fluid composed of a liquid or a gas on the side surface of the assembly, and a method of mechanically peeling off.

The surface of the silicon layer (SOI layer) of the assembly (SOI substrate) from which unnecessary portions have been removed has voids caused by the implanted ions, holes in the porous body, irregularities caused by grinding, etching, and the like. Has a rough surface. Therefore, in step S5, the upper layer portion of the roughened silicon layer is smoothed by performing the above-described heat treatment (hydrogen annealing). Thereby, the surface roughness is 0.2 n
m or less (1 μm square area). By optimizing the conditions, the surface can be made 0.15 nm or less, and even 0.1 nm or less.

FIG. 12 shows an SOI represented by the SIMOX method.
4 shows a flowchart of a method for manufacturing a substrate.

First, in step S11, S as a starting material
Prepare an i-wafer.

Next, in step S12, for example, an acceleration voltage of 10
0 keV to 300 keV, 2 × 10 ¹⁷cm^-2~ 4 × 10
¹⁸cm^-2Oxygen ions are implanted at a moderate dose.

In step S13, the wafer into which oxygen ions have been implanted is heat-treated at a temperature of 1000 ° C. to 1400 ° C. to form a buried oxide film.

Next, in step S14, if an oxide film is formed on the surface of the SOI layer, the surface oxide film is removed.

The surface of the SOI layer of the SOI substrate thus obtained is caused by oxygen ion implantation (step S12) and formation of a buried oxide film (step S13) even when a polished wafer is used as a starting material. The surface has irregularities. Therefore, in step S15, the above-described heat treatment (hydrogen annealing) is performed to remove the upper layer portion having the unevenness of the SOI layer. At this time, the surface of the SOI layer after being etched by the smoothing effect has a smooth surface having an Rrms of 0.4 nm or less in a 1 μm square area and an Rrms of 1.5 nm or less in a 50 μm square area.

[0131] Of the above-described methods for manufacturing a semiconductor substrate according to the present invention, a process for manufacturing an SOI substrate using a hydrogen implantation separation method will be described in more detail with reference to FIG.

In step S21, Si as the first base material
At least the surface of the wafer 31 is thermally oxidized to form a silicon oxide layer to be the buried insulating film 22, and a dose of 1 × 10 ¹⁶ cm ⁻² to 1 × 10 ¹⁹ c of hydrogen ions or rare gas ions is applied.
Ion implantation is performed at m ⁻² and an acceleration voltage of 10 keV to 500 keV. In addition to using the ion implantation apparatus, a method of implanting ions into the wafer from the plasma of hydrogen or a rare gas using the potential difference between the plasma and the wafer can be used as the ion implantation method. Thus, the separation layer 32 is formed.

In step S22, another Si substrate 21 as a second base material is prepared, and if necessary, the natural oxide film on the bonding surface is removed, and the Si surface and the surface of the insulating film 22 are removed. Paste. Thus, an assembly in which the two Si substrates are bonded to each other is completed.

In step S23, heat treatment is performed in an oxidizing atmosphere, and the assembly is separated in the separation layer 32. If a high-pressure fluid (for example, a liquid or a gas) is applied to the side surface of the assembly for separation, the separation layer becomes a weak layer having relatively low mechanical strength. The wafer 31 is separated (separated) from the assembly while remaining on the wafer.

Alternatively, when heat treatment in an oxidizing atmosphere is performed at a high temperature of 500 ° C. or higher at the same time as or after the bonding step, hydrogen ions, nitrogen ions, or rare gas ions may be generated in the separation layer. The microbubbles grow, and the wafer 31 is separated from the assembly while the silicon film 22 remains on the wafer 21.

The wafer 31 thus separated / removed from the assembly maintains the wafer shape although the thickness is reduced by the thickness of the silicon film 23. Can be used as material. In the case of reuse, a single-crystal silicon film may be grown by epitaxial growth after polishing the surface exposed by separation.

The surface of the silicon film 25 after the separation is a rough surface having irregularities caused by microbubbles (microvoids). Therefore, in step S24, as described above, heat treatment is performed in a hydrogen-containing reducing atmosphere with the planes made of non-oxide silicon opposed to smooth the upper layer of the silicon film 25 having a rough surface.

In the example of FIG. 13, since the wafer 21 has the silicon oxide film 24 on the back surface by the heat treatment in the oxidizing atmosphere, the silicon oxide film 24 remains on the back surface of the SOI substrate after the step S23. I have. Therefore, with the surface of the silicon film 25 being masked, the silicon oxide film is removed with an etchant such as hydrofluoric acid. Thereafter, a plurality of SOI substrates can be etched at the same time by the present invention using the apparatus shown in FIGS.

Alternatively, the heat treatment for bonding is performed in a non-oxidizing atmosphere, and the back oxide film 24 is simultaneously formed during the bonding process.
If the natural oxide film is removed before hydrogen annealing, the back surface becomes non-oxide silicon.

Next, a method for manufacturing a semiconductor substrate using the epitaxial layer transfer method will be described in more detail.

As shown in FIG. 14, first, in step S31,
A substrate 31 made of a single crystal of Si is prepared as a first base material, and a layer 33 having a porous structure is formed at least on a main surface side. Porous Si can be formed by anodizing a Si substrate in an HF solution. The porous layer has a sponge-like structure in which pores having a diameter of about 10 ^-1 nm to 10 nm are arranged at intervals of about 10 ^-1 nm to 10 nm. The density of the HF solution is 50 to 2 compared to the density of single crystal Si of 2.33 g / cm ^3.
0 to 0.6%, changing the alcohol addition ratio, or changing the current density to 2.1 to 0.6 g / c.
m ³ . If the specific resistance and the electric conductivity type of the portion to be made porous are modulated in advance, the porosity can be changed based on this. In the p-type, under the same anodizing conditions, the specific degenerate substrate (P ⁻ ) has a smaller pore diameter but a higher pore density by about one digit and higher porosity than the degenerate substrate (P ⁺ ).
That is, the porosity can be controlled by changing these conditions, and is not limited to any one of the methods. The porous layer 33 may be either a single layer or a structure in which a plurality of layers having different porosity are stacked. If the ion implantation is performed so that the projection range is included in the porous layer formed by anodization, bubbles are formed in the porous pore walls near the projection range, and the porosity can be increased. The ion implantation may be performed before or after the formation of the porous layer by anodization. Further, the porous layer 33
It may be after the single crystal semiconductor layer structure is formed thereon.

Next, in step S32, at least one layer of a non-porous single crystal semiconductor is formed on the porous layer 33. The nonporous single crystal semiconductor layer 23 is arbitrarily selected from a single crystal Si layer formed by epitaxial growth, a layer in which the surface layer of the porous layer 33 is made nonporous, and the like. Further, when the silicon oxide layer 22 is formed on the single crystal Si layer 33 by a thermal oxidation method, the interface between the single crystal silicon layer and the buried oxide film can be an interface formed by thermal oxidation with a small interface state. Is preferred. In step S33, the main surface (bonding surface) of the semiconductor substrate on which the non-porous single-crystal Si layer 23 is formed is brought into close contact with the surface (bonding surface) of the second substrate 21 at room temperature. Before the contact, it is desirable to wash to remove deposits and foreign substances on the surface. The second substrate can be selected from Si, a substrate in which a Si oxide film is formed on a Si substrate, a light-transmitting substrate such as quartz, sapphire, etc., but is not limited thereto. The surface to be provided may be sufficiently flat and smooth. FIG. 13 shows a state in which the second substrate and the first substrate are bonded to each other with the insulating layer 22 interposed therebetween; however, the insulating layer 22 may not be provided.

At the time of bonding, the insulating thin plate is
It is also possible to bond three sheets of scissors between the second substrate and the second substrate.

Subsequently, the unnecessary portion on the back side of the first substrate 31 and the porous layer 33 are removed to remove the non-porous single-crystal Si layer 23.
Is expressed. This includes, but is not limited to, the two methods described above.

In the first method, the first substrate 21 is removed from the back side to expose the porous layer 33 (step S3).
4).

Subsequently, the porous layer 33 is removed to expose the non-porous single-crystal silicon layer 23 (Step S35).

The removal of the porous layer is preferably performed by selective etching. At least mixture using the porous silicon containing hydrofluoric acid and hydrogen peroxide to non-porous single-crystal silicon, 10 ⁵ fold selective etching. A surfactant may be added to the above-described etching solution to prevent air bubbles from adhering. Particularly, an alcohol such as ethyl alcohol is preferably used. If the porous layer is thin, this selective etching may be omitted.

In the second method, the porous layer 3 serving as a separation layer is used.
The substrate is separated in 3 to obtain a state as in step S34 in FIG. As a method of separation, a method of applying an external force such as pressurizing, pulling, shearing, wedge, or the like; a method of applying ultrasonic waves; a method of applying heat; A method of heating in a pulsed manner to apply thermal stress or soften;
There is a method of ejecting a fluid such as a water jet or a gas jet, but the present invention is not limited to this method.

The separation layer desirably has at least two layers having different porosity.

Subsequently, in step S35, the porous layer 33 remaining on the surface side of the second substrate 21 is removed by etching. The porous etching method is the same as the method of exposing the porous layer 33 by etching. If the porous silicon layer 33 remaining on the second substrate 21 side is extremely thin and has a uniform thickness, wet etching of the porous layer with hydrofluoric acid and hydrogen peroxide need not be performed.

Subsequently, in step S36, a heat treatment is performed in a reducing atmosphere containing hydrogen to anneal the upper layer portion 25 having the irregularities of the single crystal Si layer 23. At this time, it is possible to simultaneously reduce the boron concentration in the single crystal silicon layer and smooth the surface.

In the semiconductor substrate obtained by the present invention, a single-crystal Si film 23 is flattened and uniformly thinned on the second substrate 21 with the insulating layer 22 interposed therebetween, and formed over a large area over the entire substrate. Have been. The semiconductor substrate obtained in this way can be suitably used from the viewpoint of producing an insulated electronic element.

The separated first Si single crystal substrate 31 is subjected to removal of the porous layer remaining on the separation surface and, if the surface smoothness is unacceptably rough, the surface is smoothed. By doing so, the substrate can be used again as the first Si single crystal substrate 31 or the next second substrate 21.

In the example shown in FIG. 13, no silicon oxide is formed on the back surface of the substrate 21. When the substrate 21 itself is made of silicon oxide like fused quartz, the silicon film 23 is masked after the step S35 to form a film of Si, SiC, SiN or the like on the back surface, or a silicon oxide tray is used. Hydrogen annealing.

FIG. 15 schematically shows the state of the silicon surface before and after the heat treatment according to the present invention.

W3 shows a cross section of the base material before the heat treatment according to the present invention, and W4 shows a cross section of the base material after the heat treatment.

When silicon does not face silicon oxide
In the case, SiH generated from the silicon surface_Two Represented by
Since gas components containing silicon are not consumed, saturated steam
When the pressure is reached, the gasification reaction of silicon,
Ringing is suppressed. Gas flow velocity near silicon film
By reducing the size, SiH generated from the silicon surface
_Two High vapor pressure of silicon-containing gas components such as
Thus, etching of silicon can be suppressed.

Before heat treatment, when a 1 μm square area was observed with an atomic force microscope, a rough surface having a mean square roughness (Rrms) of about 0.2 nm to 20 nm was smoothed by the etching according to the present invention. Rrms is 0.07n
m to about 0.15 nm. This is a value equivalent to a polished Si wafer or a surface that is even smoother.

In FIG. 15, h indicates a height difference (peak to valley), and p indicates a period.

When the surface of the base material is smoothed by polishing or the like, the thickness t of the film 23 decreases. On the other hand, according to the present invention, the etching rate can be set to about 0.01 nm at 1150 ° C. Can be regarded as almost none.

According to the present invention, the surface roughness is smoothed by at least about 1/3, more preferably by about 1/100. Even on a silicon surface on which large irregularities with p of several nm to several hundred nm are observed, at least a level difference is lower than that value, for example, 2 nm or less, more preferably 0.4 nm or less by heat treatment. You can also.

This phenomenon is considered to be surface reconstruction. That is, on the rough surface, there are countless ridge portions having high surface energy, and many surfaces having higher plane orientations are exposed on the surface as compared with the plane orientation of the crystal layer. Is higher than the surface energy depending on the plane orientation of the single crystal surface. In the heat treatment in a reducing atmosphere containing hydrogen, for example, the surface Si is reduced by the reducing action of hydrogen.
It is considered that the energy barrier of the movement of the atoms is lowered, and the Si atoms excited by the thermal energy move to form a flat or smooth surface having a low surface energy. As the plane orientation of the single crystal surface has a lower index, the flattening / smoothing according to the present invention is promoted.

Example 1 Epitaxial Layer Transfer Method / Horizontal Furnace / Opposed Surface Si A (100) -oriented 6-inch wafer surface made of boron-doped Si having a specific resistance of 0.015 Ωcm was treated with 49% HF and ethyl alcohol in a ratio of 2: Anodizing was performed in the solution mixed in Step 1 to form porous silicon with a thickness of 10 μm on the surface of the wafer. This silicon wafer was heat-treated at 400 ° C. for 1 hour in an oxygen atmosphere. This forms an ultra-thin oxide film on the surface of the porous layer and on the inner wall surface of the pore. Thereafter, the porous layer was immersed in a 1.25% HF aqueous solution for 30 seconds to remove the ultra-thin oxide film formed on the surface of the porous layer and on the inner wall surface of the hole near the surface, and then thoroughly washed with water and dried. Subsequently, this silicon wafer was set in an epitaxial growth apparatus, and 1
Heat treatment was performed in a hydrogen atmosphere at 100 ° C. to almost seal the pores on the surface of the porous silicon. Subsequently, by adding dichlorosilane as a silicon source gas to the hydrogen gas, a single crystal silicon film was formed on the porous silicon by an average of 30 μm.
It was formed with a thickness of 0 nm ± 5 nm. The silicon wafer was taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a 200 nm silicon oxide film.
As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and a second silicon wafer prepared separately were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface (bonding surface), the wafers were bonded together. The bonded silicon wafer assembly was placed in a heat treatment furnace and subjected to a heat treatment at 1100 ° C. for 1 hour to increase the bonding strength of the bonded surface. The atmosphere for the heat treatment was a mixed atmosphere of nitrogen and oxygen. The back surface of this silicon wafer assembly on the side of the first silicon wafer was ground to expose porous silicon. The porous silicon was immersed in a mixed solution of HF and hydrogen peroxide to remove the porous silicon by etching, and was thoroughly cleaned by wet cleaning. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single crystal silicon is set to in-plane 1
When each was measured at a lattice point of 0 mm, the average of the film thickness was 210 nm and the variation was ± 5 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 1 in terms of mean square roughness (Rrms).
0.1 nm and 9.8 nm. Further, when the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸
/ Cm ³ .

After removing the silicon oxide formed on the back surface of the SOI wafer by etching with hydrofluoric acid or the like in advance, the SOI wafer was set in a horizontal heat treatment furnace having a cylindrical furnace tube made of fused quartz. Gas flows from one of the core tubes to the other. SOI wafers were tested for placement as follows.

FIG. 16 is a schematic view showing the manner of installation. In FIG. 16, reference numeral 21 denotes a second silicon wafer as a support substrate, 22 denotes a silicon oxide film as a buried insulating film, and 23 denotes a silicon film. Is a single crystal silicon film. Sample A: FIG. 16 (a): One SOI wafer was set horizontally in the furnace; Sample B: FIG. 16 (b): One SOI wafer was set horizontally in the furnace, and the surface was oxidized above the SOI wafer Installed silicon wafers without film facing each other. Sample C, C ': FIG. 16 (c): Two SOI wafers were installed in parallel in a furnace at an angle; Samples D, D': FIG. 16 (d): SOI wafer Samples E and E ': two sheets are arranged so that the surfaces of the single-crystal silicon films 23 face each other, and the center of the wafer is on the center line of the furnace and perpendicular to the center line. 16 (e): The two SOI wafers are directed in parallel with the single crystal silicon film 23 in the upstream direction of the flow in the furnace so that the centers of the wafers are at equal intervals in parallel with the center line of the furnace. The wafer was set in a furnace 1 using a jig (not shown) made of SiC in each case.

After the atmosphere in the furnace was replaced with hydrogen, the temperature was raised to 1100 ° C., maintained for 4 hours, lowered again, the gas atmosphere was replaced with nitrogen, the wafer was taken out, and the single crystal silicon film was removed. Was measured again. The film thickness reduction was as follows. The flow rate was 5 slm. The film thickness was measured on grid points at 10 mm intervals in the plane and averaged.

Etching Amount Thickness Variation Sample A: 15.2 nm 193.8 nm ± 9 nm Sample B: 3 nm 206 nm ± 5.2 nm Sample C: 10.4 nm 199.1 nm ± 8 nm (upstream wafer) Sample C ′: 1. 7 nm 208 nm ± 5 nm (downstream wafer) Sample D: 1.4 nm 208.3 nm ± 5 nm (upstream wafer) Sample D ′: 1.2 nm 208.5 nm ± 5.1 nm (downstream wafer) Sample E: 12.4 nm 197.3 nm ± 8.5 nm (upstream wafer) Sample E ′: 1.1 nm 208.7 nm ± 5 nm (downstream wafer) The amount of decrease in the thickness of the SOI wafer is the same for all wafers when silicon is used as the facing surface. And 2 nm or less. On the other hand, in the comparative example, that is, when silicon is not prepared as the material of the opposing surface, and the inner surface of the cylindrical fused silica furnace tube is substantially the opposing surface, ie, samples A and C (upstream side) and E (upstream side) Had an etching amount exceeding 10 nm. That is,
By making the material of the facing plane silicon
The amount of etching was suppressed to at least 1/5 or less as compared with the case where there was no opposing surface of non-oxide silicon. The thickness variation was not deteriorated as compared to before the heat treatment.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope. The average square roughness (Rrms) was 1 μm square 50 μm square Sample A: 0.11 nm 0.35 nm Sample B: 0.13 nm 0.36 nm Sample C ': 0.11 nm 0.33 nm Sample D: 0.13 nm 0.35 nm (upstream) Sample D': 0.13 nm 0.35 nm (downstream) Sample E ': 0.12 nm 0.32 nm commercial Si wafer 0.13 nm 0.31 nm (reference) and commercial bulk Si silicon wafer (polished)
It was smoothed to the same level.

The boron concentration in the single-crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was found to be 5 × 10 ¹⁵ / cm ³ or less. Had been reduced to

Example 2 Epitaxial Layer Transfer Method / Vertical Furnace / Various Boats / Backside Oxide Film Stripping Specific Resistance 0.01
The surface of an 8-inch Si wafer of (100) orientation made of boron-doped Si of 7 Ωcm is anodized in a solution in which 49% HF and ethyl alcohol are mixed at a ratio of 2: 1 to form porous silicon with a thickness of 10 μm on the surface of the wafer. did. After heat treating this silicon wafer at 400 ° C. for 1 hour in an oxygen atmosphere, it is immersed in a 1.25% HF aqueous solution for 30 seconds to remove the ultra-thin oxide film formed on the porous surface and in the vicinity of the surface, and then thoroughly washed with water. And dried. Subsequently, the silicon wafer was set in an epitaxial growth apparatus and heat-treated in a hydrogen atmosphere at 1100 ° C. while adding a very small amount of silane gas, thereby almost completely sealing the pores on the surface of the porous silicon. Subsequently, a single crystal silicon film was formed on the porous silicon with an average thickness of 310 nm ± 5 nm by adding dichlorosilane as a silicon source gas to hydrogen gas. The silicon wafer was taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a 200 nm silicon oxide film. As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and the second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, the wafers were bonded together. The bonded silicon wafer set was placed in a heat treatment furnace and heat-treated at 1100 ° C. for 1 hour to increase the bonding strength of the bonded surfaces. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, kept at 1100 ° C. for 1 hour, and cooled in a nitrogen atmosphere. The back surface of this silicon wafer assembly on the side of the first silicon wafer was ground to expose porous silicon. The porous silicon was immersed in a mixed solution of HF and hydrogen peroxide to remove the porous silicon by etching, and was thoroughly cleaned by wet cleaning. The single crystal silicon film is transferred together with the silicon oxide film onto the second silicon wafer,
An I wafer was made.

The thickness of the transferred single crystal silicon is set to in-plane 1
When measured at lattice points of 0 mm, the average of the film thickness was 210 nm and the variation was ± 7 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 1 in terms of mean square roughness (Rrms).
0.1 nm and 9.8 nm. Further, when the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸
/ Cm ³ .

After removing the silicon oxide film on the back surface of these SOI wafers by etching with hydrofluoric acid in advance, the silicon oxide film was set in a vertical heat treatment furnace having a furnace tube made of fused quartz as shown in FIG. The gas flows downward from the upper part of the furnace.

As the facing surface constituting member 3, commercially available bulk Si
An 8-inch wafer was used. As shown in FIG. 9, the wafer W is placed horizontally so that the silicon on the back surface of one SOI wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm, and the center of the wafer and the core tube 1 It was set on a boat 4 made of SiC so that the center lines coincided with each other, and an 8-inch bulk Si wafer 3 was arranged at the same interval on the top SOI wafer. After the atmosphere in the furnace was replaced with hydrogen, the temperature in the furnace was raised to 1100 ° C., maintained for 4 hours, then lowered again, and the wafer was taken out.
The layer thickness was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

On the other hand, when a similar experiment was attempted by replacing the boat supporting the wafer with a quartz glass boat, the etching amount at the center of the wafer was 1 nm or less as in the case of the SiC boat. In some wafers W, the etching amount near the position supported by the boat was as large as 8 nm at the maximum. That is, the boat material has a non-oxidized silicon surface, for example, Si
C is preferred.

On the other hand, if the silicon oxide film on the back surface of the wafer was not peeled off before the heat treatment, and the surface facing the SOI layer was made of silicon oxide, and the heat treatment was performed in the same hydrogen atmosphere as above, the SOI wafer The amount of decrease in the thickness of the SOI layer facing the silicon wafer was as large as about 9 nm, and only the SOI wafer facing the top silicon wafer had an etching amount of 1 nm or less. That is, by using silicon as the material of the facing surface, the etching amount was suppressed to about 1/10.

FIG. 17 shows the result. FIG. 17 is a diagram showing the position dependence of the amount of decrease in the thickness of the SOI layer by the heat treatment of the present embodiment in the furnace tube. The horizontal axis indicates the arrangement position (order from the top) of the wafer in the furnace tube, and the vertical axis indicates the amount of decrease in the film thickness (nm) due to the heat treatment. Reference F indicates data in the case where the back surface oxide film of the SOI wafer is removed in advance and the SOI layer is arranged so as to face the back surface made of silicon of another SOI wafer based on this example. As a comparative example, without removing the backside oxide film of the SOI wafer,
The case where the SOI layer is disposed so as to face the back surface oxide film of another SOI wafer is shown. Since a silicon wafer (dummy wafer) arranged to secure the uniform temperature of the furnace is arranged on the first SOI wafer, the front surface of the SOI wafer faces silicon on the back surface of the silicon wafer. ing.

As is clear from FIG. 17, when the silicon oxide on the back surface is not removed, only the SOI wafer located at the top of the SOI wafer and facing the back surface of the Si wafer has a thickness reduction of 1 nm or less. However, the amount of decrease in the thickness of the SOI layer of another SOI wafer was about 10 nm.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness Rrms was 0.11 nm at 1 μm square and 0.1 mm at 50 μm square.
It was 35 nm, which was as smooth as a commercial silicon wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was found to be 5 × 10 ¹⁵ / cm ³ or less, which was a level sufficient for device fabrication. I was

Example 3 Epitaxial Layer Transfer Method / Vertical Furnace / SiC Tray The surface of an (100) -oriented 8-inch Si wafer made of boron-doped Si having a specific resistance of 0.017 Ωcm was treated with 49% HF and ethyl alcohol in a ratio of 2: Anodizing was performed in the solution mixed in Step 1 to form porous silicon with a thickness of 10 μm on the surface of the wafer. After heat-treating this silicon wafer at 400 ° C. for 1 hour in an oxygen atmosphere,
It was immersed in a 5% HF aqueous solution for 30 seconds to remove the ultra-thin oxide film formed on the porous surface and in the vicinity of the surface, and then thoroughly washed with water and dried. Subsequently, the silicon wafer was set in an epitaxial growth apparatus and heat-treated in a hydrogen atmosphere at 1100 ° C. while adding a very small amount of silane gas, thereby almost completely sealing the pores on the surface of the porous silicon. Subsequently, a single crystal silicon film was formed on the porous silicon with an average thickness of 310 nm ± 5 nm by adding dichlorosilane as a silicon source gas to hydrogen gas. The silicon wafer was taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a 200 nm silicon oxide film. As a result of the oxidation, the thickness of the single crystal silicon film is 21
It became 0 nm. This silicon wafer and the second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, the wafers were bonded together. The bonded silicon wafer assembly is placed in a heat treatment furnace and subjected to heat treatment at 1100 ° C. for 1 hour.
The bonding strength of the bonding surface was increased. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, kept at 1100 ° C. for 1 hour, and cooled in a nitrogen atmosphere. The back surface of this silicon wafer assembly on the side of the first silicon wafer was ground to expose porous silicon. The porous silicon was immersed in a mixed solution of HF and hydrogen peroxide to remove the porous silicon by etching, and was thoroughly cleaned by wet cleaning. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single-crystal silicon is set to in-plane 1
When each was measured at a lattice point of 0 mm, the average of the film thickness was 210 nm and the variation was +/− 7 nm. Also,
When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 10.1 nm and 9.8 nm as mean square roughness (Rrms), respectively. Was. When the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10
¹⁸ / cm ³ .

All of these SOI wafers were placed on a SiC tray as shown in FIG. 7 and placed in a vertical heat treatment furnace comprising a fused quartz furnace tube as shown in FIG. The gas flows downward from the upper part of the furnace. The wafer is horizontal and 1
The back of the SiC tray on which one SOI wafer is
The OI wafer is placed on a SiC boat so as to face the SOI layer surface of the OI wafer at an interval of about 6 mm, and the center of the wafer coincides with the center line of the furnace tube. Also, commercially available silicon wafers placed on a tray made of SiC were arranged at the same interval. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1180 ° C., and maintained for 1 hour. Then, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

On the other hand, when an SiO ₂ tray was used instead of the SiC tray, and the surface facing the SOI layer was made of silicon oxide, and heat treatment was performed in the same hydrogen atmosphere as above, the SOI wafer faced. The thickness reduction of the SOI layer was as large as about 40 nm.

Even when the silicon oxide on the back surface of the SOI wafer is not removed, the SOI wafer is placed on the SiC tray,
By making the opposite surface of the SOI wafer SiC, the amount of decrease in film thickness could be suppressed.

The surface roughness of the single-crystal silicon film after the heat treatment was measured by an atomic force microscope, and the mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.30 nm at 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was found to be 5 × 10 ¹⁵ / cm ³ or less, which was a level sufficient for device fabrication. I was

Example 4 Method of Transferring WJ Separated Epitaxial Layer The surface of an 8-inch (100) -oriented Si wafer made of boron-doped Si having a specific resistance of 0.017 Ωcm was set to 49.
Anodizing was performed in a solution of 2% HF and ethyl alcohol in a ratio of 2: 1 to form porous silicon with a thickness of 6 μm on the surface of the wafer. At this time, by changing the current, a high porosity layer having a thickness of 1 μm and a porosity of about 60% and a low porosity layer having a thickness of 5 μm and a porosity of 20% were formed thereon. After heat-treating this silicon wafer at 400 ° C. for 1 hour in an oxygen atmosphere, it was immersed in a 1.25% HF aqueous solution for 30 seconds to form an ultra-thin film formed on the surface of the low-porosity porous layer and on the inner wall surface of the hole near the surface After removing the oxide film, it was thoroughly washed with water and dried. Subsequently, the silicon wafer was set in an epitaxial growth apparatus and heat-treated in a hydrogen atmosphere at 1100 ° C. while adding a very small amount of silane gas, thereby almost completely sealing the pores on the surface of the porous silicon. Subsequently, dichlorosilane or silane was added as a silicon source gas to the hydrogen gas to form a single crystal silicon film on the porous silicon with an average thickness of 310 nm ± 5 nm.
The silicon wafer is taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film is oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film.
00 nm was formed. As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and the second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, the wafers were bonded together. The bonded silicon wafer assembly was placed in a heat treatment furnace and subjected to a heat treatment at 1100 ° C. for 1 hour to increase the bonding strength of the bonded surface. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, kept at 1100 ° C. for 1 hour, and cooled in a nitrogen atmosphere. A high-pressure water jet was applied to the side surface of the silicon wafer assembly by a water jet, and the silicon wafer assembly was separated in a high-porosity porous layer by a fluid wedge to expose the porous layer. It was immersed in a mixed solution of HF and hydrogen peroxide solution to selectively remove residual porous silicon by etching, and was thoroughly washed by wet washing. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single-crystal silicon is set to in-plane 1
The average of the film thickness was measured at each of the 0 mm grid points.
Was 210 nm and the variation was ± 7 nm. Also the surface
Roughness in the range of 1 μm square and 50 μm square by atomic force microscope
About 256 × 256 measurement points
And the surface roughness was 10.10, respectively, as the mean square roughness Rrms.
1 nm and 9.8 nm. In addition, the boron concentration
When measured by ion mass spectrometry (SIMS),
The boron concentration in the single crystal silicon film is 1.2 × 10 ¹⁸/ C
m^Three Met.

The silicon oxide film on the back surface of these SOI wafers was removed by etching with hydrofluoric acid in advance and then placed in a vertical heat treatment furnace comprising a furnace tube made of fused quartz. The gas flows downward from the upper part of the furnace. The wafer is as shown in FIG.
Horizontally, the silicon on the back side of one SOI wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm, and the center of the wafer and the center line of the core tube coincide with each other. It was set on a boat made of SiC, and a commercially available bulk silicon wafer from which a natural oxide film had been removed was arranged at the same interval on the top SOI wafer.
After replacing the atmosphere in the furnace with hydrogen, the temperature was set to 1100 ° C.
After heating for 4 hours, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

On the other hand, when the silicon oxide film on the back surface is not peeled off before the heat treatment and the surface facing the SOI layer is the silicon oxide film and the heat treatment is performed in the same hydrogen atmosphere as above, the SOI The decrease in the thickness of the SOI layer facing the wafer was as large as about 9 nm, and the etching amount was only 1 nm or less for only the SOI wafer facing the top silicon wafer. That is, by using silicon as the material of the facing surface, the etching amount was suppressed to about 1/10.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.12 nm at 1 μm square and 0.34 nm at 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was found to be 5 × 10 ¹⁵ / cm ³ or less, which was a level sufficient for device fabrication. I was

(Example 5: BESOI / vertical furnace / SiC)
Boat) Boron doped Si with specific resistance 0.007Ωcm
Is placed in an epitaxial growth apparatus, heat-treated in a hydrogen atmosphere at 1100 ° C., lowered to a temperature of 900 ° C., and then added with dichlorosilane as a silicon source gas to hydrogen gas to produce single-crystal silicon. The film was formed with an average thickness of 310 nm ± 5 nm. The silicon wafer was taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a 200 nm silicon oxide film. As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and a second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, both surfaces (bonded surfaces) were activated with oxygen plasma, washed with water, and bonded to the wafers. The bonded silicon wafer assembly is placed in a heat treatment furnace,
Heat treatment was performed for 0 hour to increase the bonding strength of the bonded surface. The atmosphere for the heat treatment was nitrogen. The back surface of this silicon wafer set on the side of the first silicon wafer was ground until the thickness of the first silicon wafer became about 5 μm. After this,
It was immersed in a 1: 3: 8 mixture of hydrofluoric acid, nitric acid and acetic acid to selectively etch the P ⁺ layer. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single-crystal silicon is set to in-plane 1
When each was measured at a lattice point of 0 mm, the average of the film thickness was 210 nm and the variation was ± 20 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 2 in terms of mean square roughness (Rrms).
nm and 2.2 nm.

These SOI wafers were placed in a vertical heat treatment furnace comprising a furnace tube made of fused quartz after the silicon oxide film on the back surface was removed by etching with hydrofluoric acid in advance. The gas flows downward from the upper part of the furnace. The wafer is as shown in FIG.
Horizontally, the silicon on the back side of one SOI wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm, and the center of the wafer and the center line of the core tube coincide with each other. It was set on a boat made of SiC, and a commercially available silicon wafer from which a natural oxide film had been removed was arranged at the same interval on the top SOI wafer. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1100 ° C., and maintained for 4 hours. After that, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.11 nm for a 1 μm square and 0.35 nm for a 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single-crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was reduced to 5 × 10 ¹⁵ / cm ³ or less in all cases. .

Example 6 Hydrogen Injection Peeling Method / Vertical Furnace / S
iC boat) A surface of an (100) -oriented 8-inch wafer made of boron-doped Si having a resistivity of 10 Ωcm
After being oxidized by nm, hydrogen was ion-implanted. The implantation conditions are 50 KeV and 4 × 10 ¹⁶ / cm ² . This silicon wafer and a second silicon wafer prepared separately were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface (bonding surface), the wafers were bonded together.
The bonded silicon wafer assembly was placed in a heat treatment furnace and heat-treated at 800 ° C. for 10 hours to increase the bonding strength of the bonded surface. The atmosphere for the heat treatment was nitrogen. During this heat treatment, the silicon wafer assembly separated at a depth corresponding to the projected range of the ion implantation. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single-crystal silicon is set to in-plane 1
When measured at lattice points of 0 mm, the average of the film thickness was 210 nm and the variation was ± 10 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 9.4 nm and 8.5 nm in terms of mean square roughness (Rrms), respectively. Met.

These SOI wafers were placed in a vertical heat treatment furnace comprising a furnace tube made of fused quartz after the silicon oxide film on the back surface was removed by etching with hydrofluoric acid in advance. The gas flows downward from the upper part of the furnace. The wafer is as shown in FIG.
Horizontally, the silicon on the back side of one SOI wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm, and the center of the wafer and the center line of the core tube coincide with each other. It was set on a boat made of SiC, and a commercially available silicon wafer from which a natural oxide film had been removed was arranged at the same interval on the top SOI wafer. After the atmosphere in the furnace was replaced with hydrogen, the temperature was raised to 1150 ° C., and maintained for 1.5 hours. Then, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.11 nm for a 1 μm square and 0.35 nm for a 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single-crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was reduced to 5 × 10 ¹⁵ / cm ³ or less in all cases. .

(Example 7: Simox / vertical furnace / SiC)
(Boat) Oxygen was ion-implanted into the surface of a (100) -oriented 8-inch wafer made of boron-doped Si having a specific resistance of 10 Ωcm. The injection conditions are 550 ° C., 180 KeV, 4
× 10 ¹⁷ / cm ² . This silicon wafer was placed in a heat treatment furnace and subjected to heat treatment at 1350 ° C. for 20 hours in a mixture of Ar + O ₂ to form a buried oxide film.

The thickness of the transferred single-crystal silicon is set to in-plane 1
When measured at lattice points of 0 mm, the average of the film thickness was 200 nm and the variation was ± 10 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 0.5 nm and 2 nm as mean square roughness (Rrms), respectively. Was. Further, when the boron concentration in the single crystal silicon film was measured by secondary ion mass spectrometry (SIMS), it was 5 × 10 ¹⁷ / cm ³ in all cases.

These SOI wafers were placed in a vertical heat treatment furnace comprising a furnace tube made of fused quartz after the silicon oxide film on the back surface was removed by etching with hydrofluoric acid in advance. The gas flows downward from the upper part of the furnace. The wafer is as shown in FIG.
Horizontally, the silicon on the back side of one SOI wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm, and the center of the wafer and the center line of the core tube coincide with each other. It was set on a boat made of SiC, and a commercially available silicon wafer from which a natural oxide film had been removed was arranged at the same interval on the top SOI wafer. After the atmosphere in the furnace was replaced with hydrogen, the temperature was raised to 1150 ° C., and maintained for 1.5 hours. Then, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.3 nm for a 1 μm square and 1.5 nm for a 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single-crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was reduced to 5 × 10 ¹⁵ / cm ³ or less in all cases. .

(Example 8: Non-porous layer transfer method / vertical furnace /
(SiC boat) Anodizing a (100) oriented 8-inch wafer surface made of boron-doped Si with a specific resistance of 0.017 Ωcm in a solution of 49% HF and ethyl alcohol mixed at a ratio of 2: 1 to form a porous surface on the wafer surface 10 silicon
It was formed with a thickness of μm. This silicon wafer is heat-treated at 400 ° C. for 1 hour in an oxygen atmosphere, and then 1.25% HF
The substrate was immersed in an aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the surface of the porous layer and in the vicinity of the surface. Subsequently, this silicon wafer is placed in a vertical heat treatment furnace, and heat-treated in a hydrogen atmosphere at 1100 ° C. to seal the pores on the surface of the porous silicon, and to make the surface of the porous layer non-porous to make it extremely thin and non-porous. A single crystal silicon thin film was formed. This silicon wafer and the second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, the wafers were bonded together. The bonded silicon wafer assembly is placed in a heat treatment furnace and
Heat treatment was performed at 100 ° C. for 1 hour to increase the bonding strength of the bonded surface. The temperature of the heat treatment was raised in a mixture of nitrogen and oxygen, and replaced with a combustion gas of oxygen and hydrogen at 1100 ° C.
The temperature was maintained for a period of time and the temperature was lowered in a nitrogen atmosphere. The back surface on the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon layer. The porous silicon layer was immersed in a mixed solution of HF and hydrogen peroxide to remove the porous silicon layer by etching, and washed well by wet washing. Thus, the non-porous single-crystal silicon film was transferred onto the second silicon wafer, and an SOI wafer was manufactured.

The thickness of the transferred single crystal silicon is set to in-plane 1
When measured at lattice points of 0 mm, the average of the film thickness was 10 nm. The surface roughness was measured with an atomic force microscope in the range of 1 × 50 μm square to 256 × 256.
The surface roughness was 10.1 nm and 9.8 nm in terms of mean square roughness (Rrms), respectively.
Met.

After the silicon oxide film on the back surface of the SOI wafer thus obtained was removed by etching with hydrofluoric acid in advance, the silicon oxide film was placed in a vertical heat treatment furnace comprising a fused silica furnace tube.
An OI wafer was set. The gas flows downward from the upper part of the furnace. As shown in FIG. 9, the wafer is horizontally and one SO
So that the back surface made of silicon of the I wafer faces the SOI layer surface of another SOI wafer at intervals of about 6 mm,
In addition, the wafer is placed on a SiC boat such that the center of the wafer coincides with the center line of the furnace tube, and a commercially available silicon wafer from which a natural oxide film has been removed is placed on the top SOI wafer at the same interval. Arranged. After replacing the atmosphere in the furnace with hydrogen, the temperature was raised to 1100 ° C., and maintained for 4 hours. After that, the temperature was lowered again, the wafer was taken out, and the thickness of the SOI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

On the other hand, when the silicon oxide film on the back surface is not peeled off before the heat treatment, and the silicon oxide film on the back surface of the wafer becomes the silicon oxide on the back surface of the wafer, and the heat treatment in the same hydrogen atmosphere as above is performed. The decrease in the thickness of the SOI layer facing the SOI wafer was as large as about 5 nm, and pit-shaped portions of the silicon oxide were observed in some places. Only the SOI wafer facing the uppermost silicon wafer had an etching amount of 1 nm or less, and a pit-free SOI layer was formed. That is, by using a material of the facing surface as a kind of non-silicon oxide silicon, the amount of etching was suppressed and the generation of pits was suppressed.

The surface roughness of the single crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.11 nm at 1 μm square and 0.35 nm at 50 μm square. It was smoothed to the same level as a wafer.

(Example 9: Epitaxial transfer method on quartz glass / vertical furnace / SiC tray) Specific resistance is 0.01
The surface of an 8-inch (100) -oriented wafer made of boron-doped Si of 7 Ωcm was anodized in a mixed solution of 49% HF and ethyl alcohol at a ratio of 2: 1 to form porous silicon with a thickness of 10 μm on the wafer surface. . After heat-treating this silicon wafer at 400 ° C. for 1 hour in an oxygen atmosphere, it was immersed in a 1.25% HF aqueous solution for 30 seconds to remove the ultrathin oxide film formed on the surface of the porous layer and on the inner wall of the hole near the surface. Thereafter, it was thoroughly washed with water and dried. Subsequently, this silicon wafer is set in an epitaxial growth apparatus, and
Heat treatment was performed in a hydrogen atmosphere at 0 ° C. while adding a very small amount of silane gas to almost seal the pores on the surface of the porous silicon layer. Subsequently, a single crystal silicon film was formed on the porous silicon layer with an average thickness of 310 nm ± 5 nm by adding dichlorosilane as a silicon source gas to hydrogen gas. The silicon wafer was taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film was oxidized by a combustion gas of oxygen and hydrogen to form a 200 nm silicon oxide film. As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and the second silicon wafer having a 200-nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after activating the surface (bonding surface) with nitrogen plasma, washing and drying, the wafers were bonded together. The bonded silicon wafer assembly is set in a heat treatment furnace and 400
Heat treatment was performed at 10 ° C. for 10 hours to increase the adhesive strength of the bonded surface. The back surface on the first silicon wafer side of this silicon wafer assembly was ground to expose the porous silicon layer. The porous silicon layer was immersed in a mixed solution of HF and hydrogen peroxide to remove the porous silicon layer by etching, and washed well by wet washing. The single crystal silicon film was transferred onto a second silicon wafer together with the silicon oxide film, and an SOI wafer was manufactured.

The thickness of the transferred single-crystal silicon is set to in-plane 1
When measured at lattice points of 0 mm, the average of the film thickness was 210 nm and the variation was ± 7 nm. When the surface roughness was measured at 256 × 256 measurement points in a range of 1 μm square and 50 μm square with an atomic force microscope, the surface roughness was 1 in terms of mean square roughness (Rrms).
0.1 nm and 9.8 nm. Further, when the boron concentration was measured by secondary ion mass spectrometry (SIMS), the boron concentration in the single crystal silicon film was 1.2 × 10 ¹⁸
/ Cm ³ .

All of these SOI wafers were loaded on a SiC tray from an inert gas atmosphere in a load lock chamber (not shown) to a vertical heat treatment furnace comprising a furnace tube made of fused quartz. The inert gas flows downward from the upper part of the furnace. As shown in FIGS. 7 and 9, the wafer is horizontally and one SOI
So that the back surface of the tray 31 on which the wafer is placed faces the SOI layer surface of another SOI wafer at intervals of about 6 mm,
A commercially available silicon wafer placed on a SiC tray was placed on a SiC boat so that the center of the wafer coincided with the center line of the furnace tube. They were arranged at intervals. After the atmosphere in the furnace was replaced with hydrogen from an inert gas, the temperature was raised to 1000 ° C., maintained for 15 hours, then lowered again, replaced with an inert gas, and filled with an inert gas from the furnace. Unloaded into the load lock chamber, takes out the wafer from the load lock chamber,
The thickness of the OI layer was measured again. The amount of decrease in the thickness of the SOI wafer was 1 nm or less in all the wafers.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope. The mean square roughness (Rrms) was 0.11 nm for a 1 μm square and 0.50 nm for a 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment. As a result, the concentration was reduced to 1 × 10 ¹⁶ / cm ³ or less. I was

(Example 10: WJ separation epitaxial layer transfer method / vertical furnace) A (100) -oriented 8-inch Si wafer made of boron-doped Si having a specific resistance of 0.017 Ωcm was treated with 49% HF and ethyl alcohol in a ratio of 2: Anodization was performed in the solution mixed in Step 1 to form porous silicon with a thickness of 3 μm on the surface of the wafer. At this time, by changing the current, a high porosity layer having a thickness of 2 μm and a porosity of about 45% and a low porosity layer having a thickness of 1 μm and a porosity of 20% were formed thereon. This silicon wafer was heat-treated at 400 ° C. for 1 hour in an oxygen atmosphere. Thus, a thin oxide film is formed on the surface of the porous layer and the inner wall surface of the hole. Then, 1.
After immersing in a 25% aqueous HF solution for 30 seconds to remove the ultrathin oxide film formed on the surface of the low-porosity porous layer and on the inner wall surface of the pore near the surface, the film was thoroughly washed with water and dried. Subsequently, this silicon wafer was set in an epitaxial growth apparatus, and 1
Heat treatment was performed in a hydrogen atmosphere at 100 ° C. while adding a very small amount of silane gas to almost seal the pores on the surface of the porous silicon with low porosity. Subsequently, by adding dichlorosilane as a silicon source gas to hydrogen gas, a single-crystal silicon film was formed with an average thickness of 310 nm ± 5 nm on the low-porosity porous silicon whose pores were sealed. The silicon wafer is taken out of the epitaxial growth apparatus, placed in an oxidation furnace, and the surface of the single crystal silicon film is oxidized by a combustion gas of oxygen and hydrogen to form a silicon oxide film.
0 nm was formed. As a result of the oxidation, the thickness of the single crystal silicon film became 210 nm. This silicon wafer and the second silicon wafer having a 200 nm silicon oxide film formed on the entire surface by thermal oxidation were subjected to wet cleaning generally used in a silicon device process or the like. Then, after forming a clean surface, the wafers were bonded together. The bonded silicon wafer assembly was placed in a heat treatment furnace and subjected to a heat treatment at 1100 ° C. for 1 hour to increase the bonding strength of the bonded surface. The atmosphere of the heat treatment was heated in a mixture of nitrogen and oxygen, replaced with a combustion gas of oxygen and hydrogen, kept at 1100 ° C. for 1 hour, and cooled in a nitrogen atmosphere. A high-pressure water stream by a water jet is applied to the side surface of the silicon wafer assembly, the silicon wafer assembly is separated in a highly porous porous layer by a fluid wedge, and the silicon wafer assembly is separated from the monocrystalline silicon film on the second silicon wafer. The porous layer was exposed. The single crystal silicon film is transferred together with the silicon oxide film onto the second silicon wafer, and the SOI having a residual porous silicon layer on the surface is formed.
A wafer was made.

After the silicon oxide film on the back surface of the SOI wafer having the residual porous layer was removed by etching with hydrofluoric acid in advance, it was set in the vertical heat treatment furnace shown in FIG. The gas flows downward from the upper part of the furnace. Fig. 9
And the silicon on the back surface of one SOI wafer is approximately 6 m from the surface of the SOI layer of another SOI wafer.
It was set on a SiC boat so that it faced at m intervals and the center of the wafer and the center line of the furnace tube were aligned, and the natural oxide film was removed on the top SOI wafer. Were placed at the same intervals on a commercially available bulk silicon wafer. After replacing the atmosphere in the furnace with hydrogen, set the temperature to 1
After the temperature was raised to 100 ° C. and maintained for 4 hours, the temperature was lowered again and the wafer was taken out.

The surface roughness of the single-crystal silicon film after the heat treatment was measured with an atomic force microscope, and the mean square roughness (Rrms) was 0.12 nm at 1 μm square and 0.34 nm at 50 μm square. It was smoothed to the same level as a wafer. The boron concentration in the single crystal silicon film was also measured by secondary ion mass spectrometry (SIMS) after the heat treatment, and was found to be 5 × 10 ¹⁵ / cm ³ or less, which was a level sufficient for device fabrication. I was

[0215]

According to each of the embodiments described above, the amount of decrease in the thickness of the single crystal silicon film of the semiconductor base material having the single crystal silicon film formed on the insulator on the surface is suppressed and substantially reduced. The surface of the single-crystal silicon film can be flattened to the same level as a commercially available single-crystal silicon wafer without reduction and without introducing crystal defects such as a work-strained layer introduced by polishing. That is, the surface of the SOI substrate or the like can be smoothed and the boron concentration can be reduced without impairing the film thickness uniformity within the wafer and between the wafers.

Further, even when a plurality of semiconductor substrates each having a single-crystal silicon film formed on an insulator on the surface are processed at a time, a decrease in the thickness of the single-crystal silicon film is suppressed.
In addition, since the variation in the amount of reduced film thickness within a wafer, between wafers, and between batches can be reduced, application to SOI substrates achieves surface smoothing and reduced boron concentration while maintaining uniform film thickness. it can.

Further, since the heat treatment temperature is a temperature usually used in a semiconductor process, it can be manufactured by using the existing semiconductor heat treatment manufacturing apparatus manufacturing technology. Further, heat treatment can be performed continuously with other steps.

In addition, a local single crystal region which cannot be flattened by polishing, such as the bottom of a dent formed on the surface of the substrate, can be smoothed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a heat treatment apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing the temperature dependence of an etching rate by a facing surface material.

FIG. 3 is a diagram showing an etching amount when Si and SiO ₂ are opposed to each other.

FIG. 4 shows S removed when Si and SiO ₂ face each other.
It is a figure which shows i atomic weight.

FIG. 5 is a schematic sectional view of a heat treatment apparatus according to another embodiment of the present invention.

FIG. 6 is a schematic sectional view of a main part of a heat treatment apparatus according to still another embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing an example of an opposing surface constituting member used in the present invention.

FIG. 8 is a schematic sectional view showing another example of the opposing surface constituting member used in the present invention.

FIG. 9 is a schematic sectional view of a main part of a heat treatment apparatus according to another embodiment of the present invention.

FIG. 10 is a schematic sectional view of a heat treatment apparatus according to still another embodiment of the present invention.

FIG. 11 is a flowchart showing an example of a method for manufacturing a semiconductor substrate using the heat treatment method of the present invention.

FIG. 12 is a flowchart showing another example of a method for manufacturing a semiconductor substrate using the heat treatment method of the present invention.

FIG. 13 is a schematic view for explaining a method for manufacturing a semiconductor substrate using the heat treatment method and the ion implantation separation method of the present invention.

FIG. 14 is a schematic diagram for explaining a method for manufacturing a semiconductor substrate using the heat treatment method and the epitaxial layer transfer method of the present invention.

FIG. 15 is a schematic diagram for explaining a smoothing action by the heat treatment method of the present invention.

FIG. 16 is a schematic diagram for explaining a method of arranging a substrate during heat treatment.

FIG. 17 is a view showing the furnace position dependence of a film thickness reduction amount by heat treatment.

Claims (66)

[Claims] 1. A heat treatment method for an SOI substrate having a silicon surface, wherein the SOI substrate is opposed to a plane made of a material mainly containing non-silicon oxide at a predetermined interval. A heat treatment method for an SOI substrate, comprising a step of heat treating the substrate in a reducing atmosphere containing hydrogen. 2. The method according to claim 1, wherein the material is silicon, silicon carbide,
2. The SOI according to claim 1, wherein the SOI is made of any one of silicon nitride.
Heat treatment method for the substrate. 3. The method according to claim 1, wherein the silicon surface is an unpolished surface. 4. The method according to claim 1, wherein the silicon surface has a rough surface caused by a porous Si layer. 5. The heat treatment method for an SOI substrate according to claim 1, wherein the silicon surface has a rough surface caused by minute voids. 6. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI substrate has a buried insulating film obtained by oxygen ion implantation and heat treatment. 7. The heat treatment method for an SOI substrate according to claim 1, wherein the plane is a surface from which a natural oxide film has been removed. 8. The heat treatment method for an SOI substrate according to claim 1, wherein the plurality of SOI substrates are opposed to each other so that the silicon surfaces are parallel to each other. 9. The heat treatment method for an SOI substrate according to claim 8, wherein one of the SOI substrates faces a back surface of the other SOI substrate from which an oxide film has been removed. 10. The heat treatment method for an SOI substrate according to claim 8, wherein the silicon surfaces face each other. 11. The heat treatment method for an SOI substrate according to claim 1, wherein the plurality of SOI substrates are coaxially arranged at predetermined intervals so as to be in the same direction, and the silicon surface of the top SOI substrate is provided. A heat treatment method for an SOI substrate, wherein a dummy substrate having the plane is disposed so as to face the SOI substrate. 12. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI substrate is disposed in a container having an inner wall surface made of non-oxide silicon. 13. The SOI substrate according to claim 1, wherein the SOI substrate is disposed in a container having an outer tube made of silicon oxide and an inner tube having an inner surface made of non-oxide silicon. Heat treatment method. 14. The SOI substrate heat treatment method according to claim 13, wherein a hydrogen gas is supplied into the inner tube, and the hydrogen gas is supplied from the inner tube through a flow path between the inner tube and the outer tube. SOI to exhaust
Heat treatment method for the substrate. 15. The heat treatment method for an SOI substrate according to claim 1, wherein a support member whose surface is made of non-oxide silicon is placed in a container whose inner wall surface is made of non-oxide silicon so that the plurality of SOI substrates are parallel to each other. A heat treatment method for an SOI substrate on which the plurality of supported SOI substrates are arranged. 16. The heat treatment method for an SOI substrate according to claim 1, wherein a mean square roughness in a 1 μm square region of the silicon surface after the heat treatment is 0.4 nm or less. 17. The heat treatment method for an SOI substrate according to claim 1, wherein the plurality of SOI substrates are coaxially arranged at predetermined intervals so as to be in the same direction, and face the silicon surface of the first SOI substrate. Heat treatment method for an SOI substrate in which a dummy substrate at least on the surface of which is made of non-oxide silicon is disposed. 18. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI substrate has an Si layer formed by epitaxial growth. 19. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI layer of the SOI substrate has a thickness of 450 nm or less. 20. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI layer of the SOI substrate has a thickness of 20 nm to 250 nm. 21. The process is performed so that the gas flow rate in the direction parallel to the main surface near the main surface of the SOI substrate is smaller than the gas flow rate in the direction perpendicular to the main surface at the outer peripheral portion of the SOI substrate. The method for heat treating an SOI substrate according to claim 1. 22. The method for heat treating an SOI substrate according to claim 21, wherein the treatment is performed such that the gas flow rate near the main surface of the SOI substrate becomes substantially zero. 23. The SOI substrate heat treatment method according to claim 1, wherein the silicon oxide film on the back surface of the SOI substrate is removed to expose a back surface made of non-oxide silicon. 24. The SOI substrate is placed on a tray having a back surface made of non-oxidized silicon, with the SOI layer facing upward, and the SOI substrates placed on a plurality of trays are arranged facing the back surface of the tray. The S according to claim 1,
Heat treatment method for OI substrate. 25. The heat treatment method for an SOI substrate according to claim 1, wherein a heat treatment is performed by arranging an opposing surface component mainly composed of silicon carbide via a hydrogen gas in opposition to the SOI substrate. 26. The heat treatment method for an SOI substrate according to claim 1, wherein the reducing atmosphere containing hydrogen substantially consists of hydrogen or hydrogen and an inert gas. 27. The method according to claim 1, wherein a dew point of the reducing atmosphere containing hydrogen is −92 ° C. or less. 28. The heat treatment method for an SOI substrate according to claim 1, wherein at least the surface of the member supporting the SOI substrate is made of a material mainly containing Si, SiC or SiN. 29. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI substrate is disposed such that a main surface thereof is perpendicular to a main flow of a gas introduced into the container. 30. An SOI substrate heat treatment apparatus having an etching apparatus for performing the heat treatment method according to claim 1. 31. The apparatus for heat treating an SOI substrate according to claim 30, further comprising a furnace containing the SOI substrate and having an inner surface made of non-oxidized silicon that can be reduced in pressure. 32. A method for manufacturing an SOI substrate, comprising the step of smoothing the surface of the SOI substrate by the heat treatment method of claim 1. 33. An SOI method comprising the step of lowering the impurity concentration of an SOI layer of an SOI substrate by the heat treatment method of claim 1.
How to make a substrate. 34. A method for manufacturing an SOI substrate having a silicon film, comprising: a step of bonding a first base material and a second base material having an internal separation layer for defining a separation position; Transferring the silicon film onto the second base material by separating the first and second base materials in a layer that defines the separation position; and transferring the silicon film onto the second base material. Heat-treating the silicon film in a reducing atmosphere containing hydrogen with the flat surface made of non-oxidized silicon facing the silicon film. 35. A method for manufacturing an SOI substrate having a silicon film, comprising: bonding a first base material and a second base material; and bonding the first and second base materials to the first base material. A removing step of removing a part of the base material while leaving a silicon film on the second base material; and a non-polished surface of the silicon film, a flat surface made of non-oxidized silicon, Heat treating the silicon film in a reducing atmosphere containing hydrogen. 36. The method for manufacturing an SOI substrate according to claim 34, wherein the method includes a step of removing a silicon oxide film on a back surface of the second base material. 37. The first base material having a non-porous single-crystal silicon film formed on a porous silicon layer, and bonding the non-porous single-crystal silicon film to a second base material;
36. The method for manufacturing an SOI substrate according to claim 34, further comprising a step of removing the porous silicon before etching. 38. The method for manufacturing an SOI substrate according to claim 34, wherein the separation layer is a porous layer, and the heat treatment step is performed after selectively etching a porous layer remaining on the silicon film after separation. . 39. The method for manufacturing an SOI substrate according to claim 34, wherein the separation layer is a porous layer, and the heat treatment step is performed after the separation, with the porous layer remaining on the silicon film. 40. The SOI substrate according to claim 34, wherein the separation layer is a layer into which an inert gas or hydrogen ions are implanted, and the heat treatment step is performed without polishing the surface of the silicon film exposed after separation. Production method. 41. The SOI according to claim 35, wherein the removing step includes a step of removing a porous layer remaining on the silicon film.
How to make a substrate. 42. The method for manufacturing an SOI substrate according to claim 35, wherein a porous layer remains on the silicon film after the removing step. 43. The surface of the silicon film after the removing step is a surface subjected to a plasma etching process.
6. The method for manufacturing an SOI substrate according to 5. 44. The method for manufacturing an SOI substrate according to claim 34, wherein a mean square roughness in a 1 μm square region on the surface of the silicon film is 0.2 nm or more. 45. In the heat treatment step, the SOI
36. The process according to claim 34, wherein the gas flow in the direction parallel to the surface near the surface of the substrate is smaller than the gas flow in the direction perpendicular to the surface of the outer peripheral portion of the SOI substrate. 3. The method for manufacturing an SOI substrate according to 1. 46. The method for manufacturing an SOI substrate according to claim 45, wherein the processing is performed such that the gas flow rate near the surface of the SOI substrate becomes substantially zero. 47. The S according to claim 34, wherein the dew point of the reducing atmosphere containing hydrogen is −92 ° C. or less.
A method for manufacturing an OI substrate. 48. The method for manufacturing an SOI substrate according to claim 34, wherein at least a surface of the member supporting the SOI substrate is made of a material mainly containing Si, SiC or SiN. 49. The method for manufacturing an SOI substrate according to claim 34, wherein the SOI substrate is disposed so that a main surface thereof is perpendicular to a main flow of a gas introduced into the container. 50. The method for manufacturing an SOI substrate according to claim 34, wherein the silicon oxide film on the rear surface of the SOI substrate is removed to expose a rear surface made of non-oxide silicon. 51. The SOI substrate is placed on a tray having a back surface made of non-oxidized silicon with an SOI layer facing upward, and the SOI substrates placed on a plurality of trays are arranged facing the back surface of the tray. A method for manufacturing an SOI substrate according to claim 34 or 35. 52. The method for manufacturing an SOI substrate according to claim 34, wherein a heat treatment is performed by arranging an opposing surface constituent member containing silicon carbide as a main component via the hydrogen gas in opposition to the SOI substrate. 53. The method for manufacturing an SOI substrate according to claim 34, wherein the reducing atmosphere containing hydrogen substantially consists of hydrogen or hydrogen and an inert gas. 54. The method for manufacturing an SOI substrate according to claim 34, wherein a mean square roughness of the surface of the silicon film after the heat treatment is set to 0.1.
A method for manufacturing an SOI substrate with a thickness of 4 nm or less. 55. The method for manufacturing an SOI substrate according to claim 34, wherein the plurality of SOI substrates are coaxially arranged at predetermined intervals so as to be in the same direction, and the silicon of the top SOI substrate is formed. A method for manufacturing an SOI substrate in which a dummy substrate whose surface is made of non-oxidized silicon is provided so as to face the surface of the film. 56. The method for manufacturing an SOI substrate according to claim 34 or 35, wherein the silicon film is an SOI layer formed by epitaxial growth. 57. The method for manufacturing an SOI substrate according to claim 34, wherein the silicon film before etching has a thickness of 450 nm or less. 58. The method for manufacturing an SOI substrate according to claim 34, wherein the silicon film after etching has a thickness of 20 nm to 250 nm.
A method for manufacturing an SOI substrate having a thickness of m. 59. The method for manufacturing an SOI substrate according to claim 1, wherein the temperature of the heat treatment is higher than or equal to 300 ° C. and lower than or equal to the melting point of silicon. 60. The method for manufacturing an SOI substrate according to claim 1, wherein the temperature of the heat treatment is equal to or higher than 800 ° C. and equal to or lower than the melting point of silicon. 61. The method for manufacturing an SOI substrate according to claim 34, wherein the temperature of the heat treatment is higher than or equal to 300 ° C. and lower than or equal to the melting point of silicon. 62. The method for manufacturing an SOI substrate according to claim 34, wherein the temperature of the heat treatment is equal to or higher than 800 ° C. and equal to or lower than the melting point of silicon. 63. The SOI substrate according to claim 34 or 35.
In the manufacturing method, the flow rate of the gas flowing through the outer periphery of the SOI substrate in the furnace is set to 1
0cc / min.cm ^Two More than 300cc / min.cm
^Two A method for manufacturing an SOI substrate described below. 64. The method for manufacturing an SOI substrate according to claim 34, further comprising a step of spraying a fluid onto the side surfaces of the bonded first and second base materials to mechanically separate the side surfaces. 65. The method for manufacturing an SOI substrate according to claim 64, wherein the separation layer has at least two layers having different porosity. 66. The heat treatment method for an SOI substrate according to claim 1, wherein the SOI substrate is carried into the furnace from a load lock chamber without exposing the inside of the furnace to an oxidizing atmosphere.