JP2000150840A - Semiconductor substrate and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce a semiconductor substrate having reduced crystal defect on a porous silicon layer by performing heat treatment in an atmosphere containing no nonporous single crystal material gas, specifying silicon etching at a specified amount or less and specifying the variation rate of haze on the surface of a porous silicon layer. SOLUTION: A substrate 1 having a porous silicon layer 90 at least in the surface layer is prepared and a thin protective film 4 is formed on the wall 3 of a hole made in the porous single crystal silicon layer. It is immersed into an aqueous solution of low concentration HF and the protective film 4 is removed. The basic body where porous silicon is formed is then set in an epitaxial growth system and subjected to heat treatment (prebake) before a nonporous single crystal 6 is grown. Prebake conditions are set such that the etching amount of porous silicon layer, i.e., reduction in the thickness thereof, is 2 nm or less, preferably 1 nm or less, and the variation rate(r) of haze of the porous silicon layer is within 3.5, preferably within 2.0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly, to a non-porous semiconductor layer formed on a porous semiconductor layer and a method for forming the same.
Furthermore, the present invention relates to a method for evaluating the surface shape and state of a semiconductor substrate, particularly a porous layer, and a method for manufacturing a semiconductor substrate using the evaluation method.

The present invention mainly relates to a MOSFET,
The present invention relates to a semiconductor substrate used as a base of an integrated circuit using a bipolar transistor or the like, and a method for forming the same.

[0003]

2. Description of the Related Art In silicon-based semiconductor devices and integrated circuit technology, a silicon-on-insulator (SOI) structure in which a single-crystal silicon film is disposed on an insulator has a reduced parasitic capacitance and facilitates element isolation. Numerous studies have been made on technologies for achieving high speed, low power consumption, high integration, and reduction in total cost.

As a method of forming this SOI structure, 1
FIPOS (Fully isola) proposed by Imai, which was popular during the 970s and early 1980s
There is a method of “tion by porous silicon”. (K. Imai, Solid State El
electronics 24 (1981) P.E. 159).
This method forms an SOI structure using the accelerated oxidation phenomenon of porous silicon, but has a specific problem that a surface silicon layer can be formed only in an island shape.

[0005] As one of the SOI formation techniques that have recently attracted attention, a wafer bonding technique (wafer bond) is used.
Ding technology), and various methods have been proposed from the viewpoint of the arbitrary thickness of the surface silicon layer and the buried silicon oxide layer having the SOI structure and the good crystallinity of the surface silicon layer.

A bonding method for bonding wafers to each other without an intermediate layer such as an adhesive has been proposed by Nakamura et al. B. L
Asky et al. (JB Lasky, SR Stiff
ler, F .; R. White, and J.M. R. Abe
rnathey, technical Digesto
f the International Elect
ron Devices Meeting (IEEE,
New York, 1985); 684) reported in 1984 the method of thinning one of the bonded wafers and the operation of the MOS transistor formed thereon.

In the method of Lasky, a low-concentration or n-type epitaxial silicon layer is formed on a single-crystal silicon wafer to which high-concentration boron is added as a first wafer. And the second wafer having an oxide film formed on the surface is cleaned as necessary,
When the two wafers are brought into close contact, the two wafers are adhered by Van der Waals force. When heat treatment is further performed, a covalent bond is formed between the two wafers, and the bonding strength is increased to a level that does not hinder device fabrication. Thereafter, the first wafer is etched from the back surface with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid,
La selectively removes the p ⁺ silicon wafer and leaves only the epitaxial silicon layer on the second wafer.
Sky et al. (Single Etch-stop method). However, the ratio between the etching rates of p ⁺ silicon and epitaxial silicon (P ⁻ or n) is as low as several tens, and further improvement has been desired in order to leave an epitaxial silicon layer having a uniform thickness on the entire surface of the wafer.

Therefore, a method has been devised in which the selective etching is performed twice. That is, as the first substrate, p ^{++ is added to} the surface of the low impurity concentration silicon wafer substrate.
And a low-impurity-concentration layer is prepared, and this substrate is bonded to a second substrate similar to the above-described method.
After that, the first substrate is thinned from the back surface by a mechanical method such as grinding and polishing. Next, p embedded in the first substrate
⁺⁺ Selective etching is performed until the entire surface of the Si layer is exposed. At this time, by using an alkaline solution such as ethylenediamine pyrocatechol and KOH as an etching solution,
Selective etching is performed depending on the difference in the impurity concentration of the substrate. Thereafter, if the exposed p ⁺⁺ Si layer is selectively removed by selective etching using a mixture of hydrofluoric acid, nitric acid and acetic acid in the same manner as in the method of Lasky et al., The above-mentioned is formed on the second substrate. Only a single-crystal Si layer with a low impurity concentration is transferred (Double Etch-stop method).
In this method, by performing selective etching a plurality of times, the overall etching selectivity is improved, and as a result, the film thickness uniformity of the surface Si layer in SOI is improved.

However, in the above-described thinning of the substrate by selective etching utilizing the impurity concentration of the substrate or the difference in composition, it is expected that the impurity concentration is affected by the profile in the depth direction. That is, if the heat treatment after bonding is performed at a high temperature in order to increase the bonding strength of the wafer, the impurities in the buried layer are diffused, so that the etching selectivity is deteriorated, and as a result, the film thickness uniformity is deteriorated. Was. Therefore, the heat treatment after bonding needs to be 800 degrees Celsius or less. In addition, since the plurality of etchings have low etching selectivity, controllability during mass production has been questioned.

In the above-mentioned method, the selectivity of etching is determined based on the impurity concentration or the difference in composition. However, Japanese Patent Laid-Open Publication No. Hei 5-21338 discloses a method for solving the above-mentioned problem. I am looking for. That is, due to the difference in structure between porous silicon and non-porous silicon having a surface area per unit volume of 200 m ² / cm ³ , selective etching as high as 100,000 times is realized (the structural difference using porous silicon). Selective etching method). In such a method, single crystal Si as a first substrate is used.
After the wafer surface is made porous by anodizing, a non-porous single-crystal silicon layer is epitaxially grown to obtain a first substrate. Then, after bonding with the second substrate and increasing the bonding strength by heat treatment or the like, if necessary, the back surface of the first substrate is removed by grinding, polishing, or the like, so that the entire surface of the porous silicon layer is exposed. Thereafter, the porous silicon is selectively removed by etching, and as a result, the non-porous single-crystal silicon layer is transferred onto the second substrate. As a result of obtaining a high selectivity of 100,000 times, the thickness uniformity of the obtained SOI layer is hardly impaired by etching, and the uniformity during the growth of the epitaxially grown single crystal silicon layer is directly reflected. It was revealed. That is, the uniformity within a wafer realized by a commercially available CVD epitaxial growth apparatus is, for example, 1.
Less than 5-3% is realized in the SOI-Si layer. In this method, porous silicon, which was a material for selective oxidation in FIPOS, is used as a material for selective etching. Therefore, the porosity is not limited to around 56%, but is preferably as low as around 20%. Note that the above-mentioned Japanese Patent Application Laid-Open No. 5-2133 is disclosed.
No. 8, published by Yonehara et al. (T. Yonehara, K. Sakaguchi).
i, N. sato, Appl. Phys. lett. 6
4 (1994) p. 2108), ELTRAN
(Registered trademark).

Further, since it does not become the structural material of the porous silicon final product, structural change and coarsening of the porous silicon are allowed as long as the etching selectivity is not impaired.

The present inventor, Sato et al. (N. Sato,
K. Sakaguchi, K .; Yamagata, Y .;
Fujiyama, and T.M. Yonehara, P
rc. of the Seventh Int. Sy
mp. on SiliconMater. Sci. an
d Tech. Semiconductor Sili
con, (Pennigton, The Electr
ochem. Soc. Inc. , 1994), p. 44
3) As the epitaxial growth on the porous material, SiH
CVD (Chemical) using ₂ Cl ₂ as a source gas
Vapor Deposition) method,
The process temperature at that time is 1040 ° C. for the heat treatment performed before the epitaxial growth, and 900-95 for the epitaxial growth.
0 ° C.

Although the structure of porous silicon is remarkably coarsened by heat treatment at a high temperature, Sato et al. Conducted a pre-oxidation (preoxidation) step of forming a protective film on the pore walls of porous silicon prior to epitaxial growth. Due to the introduction, the coarsening of the structure of the porous silicon layer due to the heat treatment is substantially suppressed. This pre-oxidation is performed, for example, at 400 ° C. in an oxygen atmosphere.

In this method, one of the important techniques is how to form a defect-free epitaxial growth of non-porous single crystal silicon on porous silicon. In the SOI wafer thus formed, stacking faults are the main defects, and stacking fault density in an epitaxial silicon layer on porous silicon is reported to be 10 ³ to 10 ⁴ / cm ² .

[0015]

Generally, stacking faults are oxidized.
It is important to note that the dielectric strength of the film may deteriorate.
Has been plucked. This is due to the absence of metal in the transition area surrounding stacking faults.
When a pure substance is deposited, the leakage current of the pn junction is increased,
It is thought to degrade the minority carrier lifetime
ing. Epitaxial growth on other porous materials mentioned above
Defect detection with lower detection limit
Method of optical microscopy after localized etching
With 10 crystal defects^Three / Cm^Two There is no report that it is below
Was. 10 ^Three -10^Four / Cm^Two Stacking fault of 1μm^Two of
The probability of being included in the gate region is approximately 0.0001-0.
Although it is as low as 00001, compared to bulk silicon wafer
The defect density is still high, and the effect is generally
It is expected that the circuit will surface as the yield. Above
The SOI wafer obtained by the method
The stacking fault density to at least 1000 / cm^Two Less than
It is required to reduce it below.

Further, the reason why a large number of stacking faults are introduced when non-porous single-crystal silicon is epitaxially grown on a porous silicon layer is that the support substrate for epitaxial growth has a "porous structure".

Conventionally, as a method of evaluating (observing) this porous structure, particularly its surface shape and state, a means of directly observing with a SEM or the like has been mainly used, but the means is complicated. There was a need for a method that could be evaluated more easily.

(Object of the Invention) A first object of the present invention is to provide a semiconductor substrate having a non-porous single crystal layer with reduced crystal defects on a porous silicon layer, and a method for manufacturing the substrate. is there.

A second object of the present invention is to provide a substrate having a non-porous crystal layer having a low crystal defect density on an insulator, and a method for manufacturing the same.

A third object of the present invention is to provide a simple method for evaluating the surface state of a porous layer, and further reduce the stacking fault density of a thin film formed on a porous material by using the method. Is to do.

[0021]

According to the present invention, there is provided a method of manufacturing a semiconductor substrate having a non-porous single-crystal layer on a porous silicon layer, wherein the non-porous single-crystal layer is formed on the porous silicon layer. Prior to the step of performing, including a step of performing a heat treatment on the porous silicon layer in an atmosphere containing no source gas of the non-porous single crystal layer, and the haze value of the surface of the porous silicon layer before and after the heat treatment The heat treatment conditions are determined so that the rate of change r (r = (haze value of porous silicon layer surface after heat treatment) / (haze value of porous silicon layer surface before heat treatment)) is within a certain range. It is characterized by the following.

In the present invention, the predetermined range is 1 ≦ r
≦ 3.5. Further, the present invention provides a step of preparing a substrate having a porous silicon layer, a heat treatment step of heat treating the porous silicon layer, and a growth step of growing a non-porous single crystal layer on the porous silicon layer,
In the method for manufacturing a semiconductor substrate having, the heat treatment is performed in an atmosphere containing no source gas for the non-porous single crystal layer, and the amount of silicon etched by the heat treatment is 2 nm or less, and the surface of the porous silicon layer is The rate of change of the haze value r (r = haze value after the heat treatment / haze value before the heat treatment) satisfies 1 ≦ r ≦ 3.5.

Further, the present invention provides a step of preparing a first substrate having a porous silicon layer, a heat treatment step of heat treating the porous silicon layer, and growing a non-porous single crystal layer on the porous silicon layer. A method of manufacturing a semiconductor substrate, comprising: a growth step; and a step of transferring the non-porous single crystal layer on the first substrate to a second substrate. In an atmosphere containing no source gas, the amount of silicon etched by the heat treatment is 2 nm or less, and the rate of change r of the haze value of the surface of the porous silicon layer (r = haze value after the heat treatment / haze value before the heat treatment) ) Is performed so as to satisfy 1 ≦ r ≦ 3.5.

Before describing the embodiments of the present invention,
After a method for forming a non-porous layer on a porous substrate is described, experimental results that led to the present invention will be described.

A method for forming a non-porous single crystal layer (epitaxially grown layer) on a porous silicon layer will be described with reference to the flowchart of FIG.

First, a substrate having a porous silicon layer is prepared (S1). Next, prior to the growth of the non-porous single-crystal layer, the porous silicon layer is subjected to a heat treatment in an atmosphere containing no source gas for the non-porous single-crystal layer.

This is called a pre-bake step (S2), and is a step for removing a natural oxide film adhered to the surface of the porous silicon layer.

The above-mentioned "in an atmosphere containing no source gas for the non-porous single crystal layer" is specifically defined as a reducing atmosphere containing a hydrogen gas or an inert gas such as He, Ar, Ne or the like. This is a heat treatment in an atmosphere or an ultra-high vacuum.

After the pre-bake step, a raw material gas is supplied to grow a non-porous single crystal layer (S3). Thus, a non-porous single crystal layer is formed on the porous silicon layer.

Next, the technical findings that led to the present invention will be described.

(Experiment 1: Difference in Si Etching Amount in Heating Step Before Growth of Shrimp Film) FIG. 3 shows the time dependence of the amount of thickness reduction by etching of the surface of non-porous single crystal silicon in the two epitaxial growth systems. The system A is a system using a device with a load lock chamber, and the system B is a system using a device without a load lock chamber and having an open-to-air reaction chamber.

As will be described in detail below, the apparatus of the system A is provided with a load lock chamber so that wafers can be taken in and out without directly exposing the reaction chamber to the atmosphere.

The amount of leak in the reaction chamber is 20 mTorr.
r / min or less, more preferably 10 mTorr / min or less.

Further, the leak amount of the gas panel of the supply gas system is set to 0.5 psi / 24 h, more preferably 0.2 psi.
/ 24h or less.

Further, it is preferable to use a high-purity gas as the supply gas. Specifically, for example, when prebaking is performed using H ₂ gas, about 20 m near the apparatus is used.
It is good to use what passed through a gas purifier arranged within 10 m, preferably within 10 m. As the purifier, a type that makes a heated palladium cell equivalent or a filter type equipped with an adsorbent is suitably used.

The processing apparatus shown schematically in FIG. 2 was used.

Reference numeral 21 denotes a reaction chamber (process chamber), 2
2 is a load lock chamber, and 32 is a transfer chamber (transfer chamber). Reference numeral 23 denotes a gate valve that separates the reaction chamber 21 from the transfer chamber 32, and 24 denotes a transfer chamber and the load lock chamber 2.
2 is a gate valve for partitioning 2. 25 is a heater such as a lamp for heating the substrate W, 26 is a susceptor for mounting the substrate W, and 27, 28 and 33 exhaust the inside of the reaction chamber 21 and the transfer chamber 32 of the rod lock chamber 22 respectively. Exhaust system 29, a gas supply system 29 for introducing a processing gas into the reaction chamber 21, 30, 34 a transfer chamber 32 and a rod lock chamber 2.
This is a gas supply system for purging the inside 2 and for introducing a gas for increasing the pressure. Reference numeral 31 denotes a transfer arm for transferring the substrate W into and out of the reaction chamber 21. Reference numeral 35 denotes a wafer cassette.

Further, as a modified example, the rod lock chamber 22 may be integrated with the transfer chamber 32 accommodating the transfer arm without being partitioned by the gate valve 24.

The heat treatment performed using such a treatment apparatus with a load lock chamber is referred to as “heat treatment in system A” for convenience.

In the system A, the heater in the reaction chamber is operated in advance, and the temperature of the susceptor and the like can be raised to about 600 ° C. to 1000 ° C.

By employing this method, it is possible to raise the temperature of the wafer introduced into the reaction chamber to 600 ° C. to 1000 ° C. in about 10 seconds. The change in the state of the pores on the surface can be suppressed from progressing by this heat treatment.

The heat treatment temperature is 1100 ° C. for system A,
1050 ° C., 600 Torr for system A, 7 for system B
At 60 Torr, both atmospheres are hydrogen gas. The etching amount was obtained by measuring the amount of decrease in the thickness of the SOI layer using an SOI substrate.

In the system B, the etching amount is 7 nm or more even if the heat treatment time is 0. This means the amount of etching when the temperature is immediately lowered after the substrate is heated to the set temperature. Just increasing the temperature will reduce the silicon thickness by as much as 7 nm.

On the other hand, in the system A, the etching amount is 2 nm or less even after the heat treatment for 10 minutes. It is known that, in the system A, the etching amount with respect to the heat treatment time is larger at 1100 ° C. than at 1050 ° C.

This difference is explained by the oxidation of silicon and the etching of the formed silicon oxide in the temperature raising step by the oxygen content and moisture in the reaction vessel. The oxygen content and moisture in the reaction vessel are determined by the purity of the supplied gas, the moisture absorbed in the supply pipe, minute leaks, the hermeticity of the reaction vessel itself, and the contamination when the substrate is carried into the reaction vessel. Incorporation of oxygen and hydrogen at the time of carrying in the substrate greatly depends on whether the substrate is introduced into the reaction vessel via a load lock or the reaction vessel is directly opened to the atmosphere and the substrate is carried in.

However, even if the reaction vessel is opened to the atmosphere, if the gas in the vessel is sufficiently replaced without raising the temperature thereafter, the concentration of residual oxygen and water decreases, but efficiency becomes a problem during mass production. Further, the amount of etching is also affected by the time required to raise the temperature to the set temperature. When supported by a substrate holder having a small heat capacity, the rate of temperature rise can be increased.

When a trace amount of oxygen or moisture is present in the system, if these concentrations are low, etching of silicon can be performed as described in F.S. w. Smith et. al. J.
Electrochem. Soc. 129 1300
(1982) and G.W. Ghidini et. al. J.
Electrochem. Soc. 131 2924
(1984).

On the other hand, when the concentration of moisture or the like increases, silicon is oxidized to form silicon oxide. Then, this silicon oxide reacts with the adjacent silicon as the temperature rises and is etched. SiO ₂ + Si → 2S
It reacts with iO ↑.

After all, the oxygen content and moisture remaining in the system are parasitic on the silicon etching during the temperature rise. Therefore, the magnitude of the residual oxygen and moisture content in the reaction vessel can be grasped by examining the silicon etching amount. .

(Experiment 2: Relationship between Prebaking Temperature and Stacking Fault Density) In these systems A and B, heat treatment temperature of stacking fault density introduced into non-porous single-crystal silicon formed on the porous silicon layer FIG. 4 shows (pre-bake temperature) dependency. The pressure in system A is 600 Torr
r, the pressures in systems B-1 and B-2 are both 760 To
rr.

The systems B-1 and B-2 were obtained from Sato et al.
o et. al. Jpn. J. Appl. Phys. 3
5 (1996) 973). The stacking fault density decreases with increasing pre-bake temperature. In the system B-2, the supply rate of the silicon source gas in the initial stage of the growth was reduced to significantly suppress the growth rate. Although the stacking fault density is reduced to about 1/3 irrespective of the temperature as compared with the system B-1, the defect density is reduced in any case only when the heat treatment temperature is increased.

The reason why the stacking fault density is reduced by increasing the pre-bake temperature as described above is as follows. System B with a large silicon etching amount of about 7 nm
At -1 and B-2, silicon oxide is once formed on the silicon surface by the residual oxygen and moisture during the temperature raising process. In the low temperature region, the formed silicon oxide cannot be completely removed, so that the defect density is high. However, if the heat treatment temperature and time are sufficiently secured, it is considered that the formed silicon oxide is removed, and as a result, the crystal defect density starts to decrease.

On the other hand, in the system A, the crystal defect density is 1000
In a high temperature range exceeding 100 ° C., the density is on the order of 10 ⁴ / cm ² , and the defect density does not decrease remarkably as compared with the systems B-1 and B-2 even when the heat treatment temperature is increased. However, as the temperature was lowered, a minimum value of the defect density was present at around 950 ° C., and the defect density was reduced to about 10 ² / cm ² at 950 ° C.

That is, unlike the systems B-1 and B-2 which have a large silicon etching amount, the silicon etching amount is 2n.
It was found that in the case of the system A as small as m or less, the stacking fault density can be reduced without changing the structure and coarsening of the porous structure.

As described above, the period from when the substrate on which the porous silicon layer is formed is set in the epitaxial growth apparatus to when the silicon source gas is introduced into the reaction vessel and the formation of the non-porous single crystal layer is started. It has been found that the amount of silicon etched from the surface of the silicon layer of the imperial chamber, that is, the amount of reduction in the thickness of the porous silicon layer plays an important role in introducing stacking faults into the non-porous single-crystal silicon layer.

(Experiment 3: Relationship between Haze Level and Stacking Fault Density) On the other hand, in System A, in order to clarify the reason why the defect density takes a minimum value near 950 ° C., the substrate on which the porous silicon layer was formed was prebaked. After performing only the above treatment, the substrate was taken out of the reaction vessel, and the surface haze level at which the porous silicon was formed was measured using a commercially available foreign substance inspection device.

For measuring the haze level, a foreign substance inspection apparatus is commercially available from a plurality of apparatus manufacturers as an apparatus for detecting the position, size, etc. of a foreign substance (Particle) on a mirror surface of a silicon wafer. Was performed using In these foreign substance inspection devices, a foreign substance is detected by irradiating a laser beam onto a silicon wafer and monitoring not a specular reflection light but a scattered light. By moving the laser light or the silicon wafer side, the position in the wafer where the laser light is incident is moved, and the scattered light intensity at each location is monitored in correspondence with the coordinate position. When a laser beam reaches a place where a foreign substance exists, the laser is scattered by the foreign substance, and the scattered light intensity increases.

FIG. 16 shows Surfscan 6 of Tencor Company.
A conceptual diagram of the observation at 420 is shown. Calibrating the scattered light intensity with standard particles such as latex particles in advance and converting the scattered light intensity into the size of a foreign substance is a method adopted by many foreign substance inspection apparatuses currently on the market. In addition, 50 is incident light, 51 is reflected light, 52 is scattered light, 53 is a silicon wafer, and 54 is an observation area.

Although the surface of the silicon wafer is mirror-finished by mechanochemical polishing or the like, it is not a completely flat surface when observed microscopically, but is composed of unevenness components having various periods and amplitudes, such as minute roughness and long-period undulations. It is confirmed by the observation with an atomic force microscope or an optical interference microscope that the surface is a finished surface. These irregularities give a minute scattered light component when the laser beam used in the foreign substance inspection device is incident. Compared to such a foreign substance, the scattered light observed over a wide area rather than locally may have a sudden change in signal intensity at a certain place like the foreign substance when viewed along the movement of the irradiation position of the laser beam. Instead, it gives a constant strength continuously.

In other words, a direct current component (DC component) or a background component can be said. That is, if a sudden signal change such as a foreign substance is removed and a continuous scattered light component is observed, it means that the surface unevenness is monitored exactly.
It is called.

The haze is generally the intensity of specularly reflected light or the ratio of the intensity of scattered light to the intensity of incident light (unit: pp).
m). However, since the detection positions of the incident light and the scattered light are different in each device, it is difficult to compare the absolute values.

Further, the scattered light intensity is generally at most about several tens of ppm, so that the ratio to the regular reflected light and the ratio to the incident light are almost the same.

Each of the commercially available foreign-matter inspection apparatuses is devoted to the incident angle, wavelength, monitor position of scattered light, and the like of the laser light.

However, it is a well-known fact that laser light used as incident light does not completely reflect on the surface but also penetrates into silicon, and the depth of the penetration depends on the wavelength.

The porous silicon has a structure in which a number of fine holes are formed by etching from the surface of a silicon wafer, and the side walls of the holes scatter the permeated laser light.

That is, if laser light is made incident on the surface of the porous silicon and the scattered light is observed, information reflecting the surface of the porous layer and the porous structure near the surface can be obtained.

The present inventors have found that in forming a non-porous single-crystal silicon layer on porous silicon, the haze value immediately before the formation of the non-porous single-crystal silicon layer, that is, immediately after the pre-bake process, is reduced. Was found to be correlated with the density of crystal defects introduced into the crystal.

The porous silicon was placed in an epitaxial growth apparatus, the temperature was raised, a silicon source gas was introduced, heat treatment was performed immediately before the formation of the non-porous single-crystal silicon layer, and the haze of the porous silicon taken out of the apparatus was increased. It has been found that by controlling the value to a certain range, the crystal defect density of the non-porous single-crystal silicon layer can be suppressed.

The porous silicon is HF-C ₂ H ₅ OH-
Anodized in a H ₂ O mixed solution, and then
Heat treated at 0 ° C. for 1 hour in an oxygen atmosphere (Preoxi
dation). Then, 25% HF aqueous solution
It was immersed for about a second, washed with water, dried and then placed in an epitaxial growth apparatus.

After performing only a heat treatment at 950 ° C. and 600 Torr and taking out from the epitaxial growth apparatus,
FIG. 5 shows the result of measuring the haze value with the foreign matter inspection device.

The haze value was about 6 after preoxidation, but was 9
Rose to the extent.

The haze value starts to increase as the time of the heat treatment described above is increased in the epitaxial growth apparatus. It increased to 11.9 in 2 seconds, 12.7 in 30 seconds, 16.3 in 60 seconds, and 25.7 in 120 seconds. The haze value of the surface of a commercially available silicon wafer was 0.18.

FIG. 6 shows the correlation between the haze value and the stacking fault density obtained by variously changing the temperature and time of the heat treatment performed before the growth of the non-porous single crystal layer.

It was found that the stacking fault density was kept low when the increase in the haze value was within 3.5 times, more preferably within 2 times. It is considered that the increase in the haze value due to the heat treatment is accompanied by a change in the porous structure.

FIGS. 7A and 7B show a state immediately before installation in an epitaxial growth apparatus (a), 950 ° C., 2 seconds (b), 110
It is a photograph in which the surface of the porous silicon layer was observed with a high-resolution scanning electron microscope after taking out from the epitaxial growth apparatus after performing the treatment at 0 ° C. for 2 seconds (c). The respective haze values were 9, 11.9 and 45. FIG. 8
7 schematically show FIGS. 7A, 7B, and 7C, respectively.

FIG. 7A is a schematic view of an SEM image of the surface of the porous silicon immediately before being installed in the epitaxial growth apparatus. Holes having a diameter of about 10 nm are formed at a density of 10 ¹¹ / cm ² . FIG. 7B is a schematic view of an SEM image of the porous silicon surface subjected to only the heat treatment at 950 ° C. and 600 Torr for 2 seconds. Although the pore density is somewhat reduced, it is still on the order of 10 ¹⁰ / cm ² .

On the other hand, when the porous surface treated at 1100 ° C. for 2 seconds was observed, the pore density was remarkably reduced to about 10 ⁶
/ Cm ² . As shown in FIG. 7 (c), the diameter of the remaining holes was large, and some of the holes reached a diameter of 40 nm. The increase in the pore diameter is caused by oxidation due to residual oxygen and moisture, etching, enlargement by surface diffusion, coalescence of adjacent pores, and the like. As is clear from the figure, as the heat treatment strength increases, the pore density generally decreases on the porous surface, and a smooth surface is formed. However, the diameter of the residual holes is increasing, indicating that the silicon atoms move strongly on the surface and in the vicinity of the surface. Cross-sectional observation confirmed that the porous structure immediately below the surface had undergone structural changes, such as an increase in pore size, along with an increase in heat treatment strength. That is, the haze value changes as shown in FIG. 7 (a) → (b) → (c).
Means that the influence of the structural change on the surface of the porous layer and the structural change in the porous layer is reflected. The stacking fault density is 1 × 10 ² / cm ² in FIG. 7B, and ² × 10 ² / cm ² in FIG.
It was 10 ⁴ pieces / cm ² .

The haze value of the porous layer due to the heat treatment from the introduction of the substrate having porous silicon to the introduction of the silicon source gas into an epitaxial growth apparatus capable of suppressing the etching amount of silicon to 2 nm, more preferably 1 nm or less. Is suppressed within 4 times, more preferably within 2 times, so that the crystal defect density of the conventional 10 ³ to 10 is suppressed.
It was clarified that the amount could be reduced from about ⁴ / cm ² to about 1 × 10 ² / cm ² . However, as described above, it is difficult to reduce defects at low temperature in a system in which the amount of silicon etching is large because the amount of oxidation is large. This is because a growth system in which the etching amount of single crystal silicon is large has a large oxidation amount at the time of temperature rise.

Incidentally, if a small amount of silicon atoms or a silicon source gas is supplied in the early stage of the growth as shown in Japanese Patent Application Laid-Open No. Hei 9-100197, the reduction of crystal defects according to the present invention is made more effective. The step of supplying a small amount of silicon atoms or the like in the early stage of the growth may be referred to as a pre-injection step.

As an example of the present invention, hydrogen 43 (1 / mi)
n), 750 ° C. in an atmosphere of a pressure of 600 Torr
A porous substrate is placed on a susceptor coated with carbon CVD-SiC kept at a temperature of about 10 ° C. through a load lock, and is heated at a rate of about 100 ° C./min.
After the temperature was raised to 50 ° C. and maintained for 2 seconds, a concentration of about 28 ppm was added for a certain period of time using a trace amount of SiH _4, and then the flow rate of the silicon source gas was increased to increase the flow rate of the non-porous single crystal silicon having a desired thickness. A film was formed. FIG. 9 shows SiH ₄
The dependence of stacking fault density on the treatment time was shown. S
It is apparent that the crystal defect density is reduced by performing the iH ₄ trace addition treatment.

After the initial growth by supplying a small amount of silicon, the substrate was taken out from the epitaxial growth apparatus and the haze value was measured. The result is shown in FIG. As is clear from the figure, the haze value is once increased by the supply processing of the trace amount of silicon, and then starts to decrease again. As shown in FIG. 10, it is effective to carry out the step of supplying a small amount of silicon at least until the haze value tends to decrease.

The porous silicon is HF-C ₂ H ₅ OH-
Anodized in a H ₂ O mixed solution to produce
Heat treatment was performed in an oxygen atmosphere at a temperature of 1 ° C. for 1 hour. Then, 1.2
It was immersed in a 5% HF aqueous solution for about 25 seconds, washed with water, dried, and set in an epitaxial growth apparatus.

The supply of a small amount of constituent atoms of the film or the supply of the source gas has the effect of promoting the removal of oxides and suppressing the generation of defects caused by oxides.

That is, according to the present invention, the pre-epi heat treatment in which the etching amount of single-crystal silicon is extremely small is performed within a range in which the decrease in the haze value of the surface of the porous silicon is suppressed to four times, and more preferably within two times. By carrying out, the stacking fault density of the non-porous single crystal silicon layer formed on the porous layer is less than 1000 / cm ² ,
It became clear that what we could do in cm ² . Further, by reducing the supply amount of the silicon raw material to the growth surface in the initial stage of the growth of the non-porous single crystal silicon, the defect reduction of the present invention can be further improved. The present invention also relates to a method for managing a haze value derived from a DC level of scattered light in a device for observing scattered light intensity by irradiating a substrate surface with laser light such as a commercially available foreign matter inspection device. To easily suppress the process conditions and increase the crystal defect density to 1000
/ Cm ² or less, more preferably 100 / cm ² or less.

Further, in the present invention, the heat treatment temperature, especially the heat treatment temperature before sealing the holes, can be lowered as shown in FIG. Of the porous layer can be suppressed, so that the selectivity in the selective etching of the porous layer in the subsequent step by the ELTRAN method (registered trademark) is not deteriorated. That is, in removing the porous layer, the crystallinity of the non-porous single-crystal silicon layer can be improved without generating any residue. Also, in the FIPOS method, the oxidation rate of the selective oxidation of the porous layer is not deteriorated.

The present inventor conducted the following experiment in order to examine the correlation between the stacking fault density and the pressure during prebaking.

As a sample, a wafer having a non-resistance of 0.013 to 0.017 Ωcm obtained by doping boron into a substrate (100) Si was prepared. Anodizing conditions are as follows: approximately 8 mA / cm 2 in a solution in which 49% HF and ethanol are mixed at a ratio of 1: 1.
The current of No. ² was passed for 11 minutes to form a porous layer. About 2
The porosity was 0%.

After being immersed in a 1.25% HF solution for 25 seconds, it was washed with water and dried. Thereafter, a heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere, and the silicon oxide film was immersed in a 1.25% HF solution for about 5 nm to be etched, washed with water, and dried. .

Next, regarding epitaxial growth on the porous layer, the epi apparatus was performed in a reaction vessel provided with a load lock chamber. 80 Torr, 600 in hydrogen atmosphere
Heat treatment was performed at Torr for 120 seconds. Then, the concentration 28
SiH ₄ was added to a hydrogen carrier gas so that the concentration became ppm, and the treatment was performed for 120 seconds. Thereafter, the addition of SiH ₄ was completed, the pressure was reduced to 80 Torr, the temperature was reduced to 900 ° C., and a 2 μm epi layer was formed. The stacking fault temperature at each heat treatment temperature was examined.

FIG. 11 shows the result. As a result, the pressure increases the surface diffusion of silicon atoms on the porous silicon surface.
It has been found that this has a significant effect on the alteration of the pore structure, and that the lower the pressure, the lower the onset of the stacking fault density reduction.

FIG. 12 shows the dependency of the stacking fault density on the heat treatment time before growth in the heat treatment at 950 ° C. and 600 Torr in a hydrogen atmosphere for the sample prepared in the same manner as in FIG. It has been found that the heat treatment increases by a factor of about 2 over 120 seconds, up to 60 seconds.

[0092]

(Embodiment 1) FIG. 13 (a)
Is an example of a system for determining conditions for appropriately performing prebaking of a porous layer.

This is based on the fact that the change in the haze value before and after the pre-bake has a correlation with the stacking fault density, as is apparent from Experiment 3.

After the formation of the porous layer, the haze value of the porous layer immediately before the pre-bake treatment is measured (the measured haze value is referred to as d.
₀ ).

Then, a pre-bake treatment is performed, and the haze value is measured (the measured haze value is d ₁ ).

Thereafter, a change in the haze value is evaluated. In particular

[0097]

[Outside 1] If 1 ≦ r ≦ 3.5, the subsequent steps such as epitaxial growth are performed under the same pre-bake processing conditions.

Conversely, if r> 3.5, the pre-bake processing conditions are changed. Then, conditions are determined so as to satisfy 1 ≦ r ≦ 3.5.

Specifically, the temperature and time are changed, or the water and oxygen in the apparatus for performing the pre-bake treatment are reduced.

Note that it is not necessary to perform the above-described evaluation on all the silicon wafers that have been put in, and it is possible to reduce
It is sufficient to evaluate one or several sheets. In particular, it is effective to carry out a test for determining a process condition in a new apparatus, or a test after remodeling, repairing, cleaning the reaction vessel, etc. of the apparatus. Further, even when the quality of the obtained semiconductor substrate becomes abnormal, the cause can be quickly extracted by performing the evaluation method of the present invention.

When the haze value d ₁ itself after the pre-bake treatment can be evaluated, the measurement of d ₀ can be omitted. FIG. 13 (b) is based on the determined conditions.
This is a series of systems for performing a pre-bake process and manufacturing a desired semiconductor substrate. Of course, before the epitaxial growth step, it is also preferable to measure the haze value to confirm whether the pre-baking is properly performed.

(Embodiment 2) FIG. 14 shows a method for forming a semiconductor substrate according to the present invention.

As shown in FIG. 14A, a substrate 1 having a porous silicon layer 90 at least on the surface side is prepared. Reference numeral 2 denotes a hole, and 3 denotes a hole wall.

Next, if necessary, as shown in FIG. 14B, a thin protective film 4 is formed on the hole walls 3 of the porous single crystal silicon layer (pre-oxidation step).

Since a protective film 5 such as a silicon oxide film is formed on the surface of the porous silicon layer for the pre-oxidation, the protective film 5 is immersed in a low-concentration HF aqueous solution to remove the protective film on the surface of the porous silicon. (HF dip step). FIG. 14C schematically shows this cross section.

Next, the substrate on which the porous single-crystal silicon was formed was set in an epitaxial growth apparatus, and heat-treated (pre-baked) as shown in FIG.
A non-porous single crystal layer 6 is formed as shown in FIG.

The pre-baking conditions are as follows: the etching amount of the porous silicon layer, that is, the reduction amount of the thickness (t) of the porous silicon layer is 2 nm or less, more preferably 1 nm or less (condition 1); The condition (condition 2) is that the rate of change r of the haze value of the high quality silicon layer is within 3.5, more preferably within 2.0 (condition 2).

[0108] etching amount te, when the layer thickness of the porous silicon layer before the heat treatment starting t _0, the layer thickness of the porous silicon layer during the heat treatment termination was t _1, represented by te = t ₀ -t ₁ be able to. The rate of change r of the haze value is represented by d _{0 as} the haze value of the heat treatment starting eye and d _{1 as} the haze value after the heat treatment.

[0109]

[Outside 2] Can be represented by

The atmosphere during the heat treatment is preferably an atmosphere containing no silicon-based gas, more preferably a reducing atmosphere containing hydrogen. Further, an inert gas atmosphere or an ultra-high vacuum may be used.

The heat treatment will be described below.

Installation in Apparatus The substrate having a porous silicon layer formed on the surface was treated with a residual oxygen content,
It is installed in a reaction vessel in which the amount of water is suppressed (not shown).
The heat treatment used in the present invention can be functionally divided into two steps, a temperature raising step and a natural oxide film removing step.
Note that the natural oxide film here refers to a silicon oxide film that is formed on the surface of the porous silicon layer unintentionally after the HF dip step and a silicon oxide film that cannot be completely removed in the HF dip step. is there.

The amount of etching can be suppressed by suppressing the amount of residual oxygen and the amount of water in the reaction vessel during the temperature raising step and the natural oxide film removing step. The residual oxygen content in the reaction vessel and the suppression of the water content are controlled not only by suppressing the oxygen content and the water content contained in the supply gas system, but also by carrying in and out the substrate into the reaction vessel through the load lock chamber. It is effective to prevent the inner surface of the reaction vessel from coming into direct contact with the atmosphere.

It is also effective to install a purifier for purifying hydrogen, which is a carrier gas, near the device as necessary. It is also desirable to increase the airtightness of the piping system and the container. By controlling these, as described above, the amount of etching of the porous silicon layer in at least two steps of the temperature raising step and the natural oxide film removing step is at least 2 nm.
Or less, more preferably 1 nm or less. However, the method of suppressing the etching amount is not necessarily limited to the above-described method.

Heating Step After the substrate having the porous silicon layer formed on the surface is placed in a reaction vessel, the substrate is heated. When the reaction vessel is made of a light transmissive material such as a quartz material, the reaction vessel is heated by irradiation with an infrared lamp from outside the reaction vessel. In addition to the lamp heating, there are induction heating by high frequency, resistance heating and the like. The reaction vessel material includes stainless steel in addition to quartz and SiC. The higher the heating rate, the faster the oxidation by residual moisture and oxygen.
Less etching is required. Preferably, 1 ° C./sec
The temperature is more preferably 5 ° C./sec or more.

In the case where the substrate is loaded into the reaction vessel without passing through the load lock chamber, the substrate is loaded and purged sufficiently to remove oxygen and water mixed in the vessel, and then heat the substrate. And raise the temperature. In any case, it is desired to perform the treatment in an ultra-high vacuum or a non-oxidizing atmosphere.

Natural oxide film removing step A natural oxide film removing step is performed following the temperature raising step. In other words, in hydrogen, or in a reducing atmosphere containing hydrogen, or
At this time, the natural oxide film is removed by heat treatment in an ultra-high vacuum.
However, the conditions are set to be within 3.5, more preferably within 2. Note that r is 1 or more.

In order to realize the above conditions, the temperature reached during the heat treatment is preferably from 850 ° C. to 1000 ° C.
More preferably, it is 870 ° C or more and 970 ° C or less.

The pressure is not particularly limited, but is preferably not higher than the atmospheric pressure, and is preferably not higher than 700 Torr, more preferably not higher than 100 Torr.

The heat treatment time excluding the temperature raising step is within 100 seconds, preferably within 60 seconds, more preferably 10 seconds.
The temperature should be within seconds, and then the temperature should be lowered immediately.

The natural oxide film is SiO ₂ + Si−> 2Si
Since it is desorbed into the gas phase by the reaction of O ↑, if the natural oxide film thickness is large, the silicon on the surface of the porous silicon layer and near the surface is etched.

During the water washing after the HF dip, the natural oxide film
After washing and drying, it is formed in the atmosphere until it is installed in the epitaxial growth apparatus, during installation in the epitaxial growth apparatus, and during the temperature raising step. In particular, if residual moisture and oxygen remain during the temperature raising step, silicon is oxidized to form a silicon oxide film in combination with the rise in temperature. As a result, the formed silicon oxide reacts with the adjacent silicon to etch the silicon.

In addition, the thicker the silicon oxide film formed during the temperature rise, the longer the heat treatment time required to completely remove the formed silicon oxide film. If the heat treatment time is long, the structural change of the porous silicon surface proceeds as described later, which is not preferable.

In the present invention, the etching amount is at least 2
Although it must be less than nm, more preferably less than 1 nm, a small silicon etching amount is nothing less than a small degree of oxidation of silicon in the device.

When this heat treatment is continued, migration of surface atoms occurs on the surface of the porous silicon to smooth the minute roughness and reduce the surface energy, and most of the pores on the surface disappear.

Load-lock type CVD epitaxial growth
In a long device, carbon is coated with CVD-SiC.
Temperature of the susceptor to 750 ° C in advance in the reaction vessel.
Load a silicon wafer with porous silicon
Install via lock. Then, 600 Torr, water
Under the condition of elementary temperature 43 (1 / min), up to 1100 degrees Celsius
And the temperature was raised at 100 degrees / minute and held at 1100 degrees for 2 seconds.
And, it cools down to 750 degrees at 100 degrees / minute,
When the wafer is taken out through the
Before treatment, 10 holes with an average diameter of about 10 nm¹¹/ C
m^Two The pore density was 10⁶ / Cm^Two Decreases to
In both cases, the pore size was enlarged to 20 to 40 nm. This condition
Subsequent to the heat treatment described above, the silicon source gas
To the single crystal silicon layer by adding
Stacking fault density of 10 ^Four / Cm^Two Becomes
Was. On the other hand, the heat treatment at 1100 degrees is replaced with 950 degrees,
If the holding time is equal to 2 seconds, the pore density after heat treatment
The degree decrease was at most an order of magnitude. Also, the hole diameter almost increased.
It didn't matter. After this heat treatment condition, silicon saw
Single-crystal silicon layer by adding
If grown axially, the stacking fault density will be 10^Two / Cm^Two When
Compared to the case of 1100 degrees, it decreased sharply to 1/100.

The crystal lattice on the surface of the porous silicon is distorted due to the stress acting between the porous silicon and the non-porous single-crystal silicon substrate. It is considered that the crystal defect is likely to be introduced into the residual hole portion because it is concentrated in the portion.

In this method, the supply of the silicon source gas to the porous silicon surface is started for the eyes in which the residual pores are reduced by the heat treatment for removing the natural oxide film, so that the distortion of the residual pores due to the decrease in the pore density is reduced. It prevents concentration and suppresses the introduction of crystal defects. This method became feasible for the first time by removing a naturally heated oxide film with a very small silicon etching amount.

In particular, the present invention relates to a method for managing a haze value introduced from the DC level of scattered light in a device for observing scattered light intensity by irradiating a substrate surface with laser light such as a commercially available foreign matter inspection device. The process conditions are simply and nondestructively controlled to suppress the crystal defect density to 1000 / cm ² or less, more preferably 100 / cm ² or less.

For removing the natural oxide film, another method such as the use of HF gas may be adopted or used as long as the etching amount of silicon is suppressed to the above-mentioned range.

The temperature raising step and the natural oxide film removing step in the present invention are not particularly limited as long as silicon etching is suppressed and a film is not formed on the porous surface by heat treatment. It is desirable to perform the treatment in a vacuum or in a hydrogen atmosphere.

Measurement of Haze Value The measurement of the haze value is obtained by measuring the scattered light intensity when parallel light such as laser light is incident on the substrate surface. If a commercially available foreign matter inspection device using a laser beam is used, measurement can be easily performed. As the wavelength of the laser beam, a short wavelength such as 488 nm of an Ar laser is suitably used. The shorter the wavelength, the shorter the penetration length of light into the porous layer, so that a structural change near the surface of the porous layer that directly affects the crystallinity of the epitaxially grown layer can be detected sharply. In addition, when the incident angle is large, that is, when the light is incident at a shallow angle with respect to the substrate surface, the penetration length into the porous layer is shortened, and a measurement sensitive to a structural change near the surface becomes possible. .

Epitaxial Growth After the heat treatment step (pre-bake), a source gas is supplied to close the porous holes, and a non-porous single crystal film is formed to a desired thickness. In this manner, a non-porous single crystal layer with reduced stacking fault density can be formed on porous silicon.

As the non-porous single crystal, even if silicon is homoepitaxially grown, SiGe, SiC, GaAs, InP, or heteroepitaxially grown silicon may be used.
It may be AlGaAs, GaN, or the like.

(Porous Silicon Layer) The porous Si used in the present invention is essentially the same as the porous silicon which has been studied since the discovery of Uhril et al. Chemical formation (Anodizatio
n) or the like, but is not limited to impurities, plane orientation, preparation method and the like of the substrate as long as it is porous Si.

When porous silicon is formed by anodization, the chemical conversion solution is water-soluble with hydrofluoric acid as a main component. During the anodization, gas adheres to the electrodes and the silicon surface, and the porous layer tends to be non-uniform.
t Angle) is increased to accelerate the desorption of the attached air bubbles (Enhance) so that the chemical conversion occurs uniformly. Of course, the porosity is formed without adding alcohol. FIPO porous silicon according to the present invention
When used in the S method, the porosity is about 56%, and when used in the bonding method, the porosity is low (approximately 50% or less,
More preferably 30% or less). However, it is not limited to this.

Since the porous silicon is formed by the etching as described above, the surface of the porous silicon is not limited to the hole penetrating to the inside of the porous material, and the field emission is not limited to the field emission.
type Scanning Electron
There are also holes that are shallower, such as irregularities that are shallow enough to be observed by Microscope (FESEM). The lower the porosity (Prosity (%)) of the porous silicon, the lower the stacking fault density on the porous material. Porous silicon having a low porosity can be realized by, for example, a method of increasing the HF concentration during anodization, decreasing the current density, or increasing the temperature.

In the porous single-crystal silicon layer, only the main surface layer of the Si substrate may be made porous, or the entire Si substrate may be made porous.

The porous layer is formed by implanting rare gas ions such as He, Ne and Ar or hydrogen ions into non-porous single-crystal silicon and subjecting it to a heat treatment as necessary, thereby forming microbubbles. (Micro-bubbles) can be generated and made porous. Regarding this point, see JP-A-5-5-2.
This is disclosed in Japanese Patent Publication No. 11128.

(Pre-Oxidation) In the present invention, a protective film may be formed on the pore wall of the porous silicon layer, if necessary.

Since the thickness of the wall between adjacent holes of the porous silicon is very thin, several nm to several tens of nm, the porous silicon may be porous at the time of epitaxial growth, thermal oxidation of the epitaxially grown layer, or heat treatment after bonding. Adjacent pores in the layer may aggregate and coarsen, further dividing. Agglomeration of the pores of this porous layer (agglomara)
tion) and coarsening (Coarsening) phenomenon
In some cases, the selective etching rate of the porous silicon is reduced and the selectivity is deteriorated. In FIPOS, the progress of the oxidation of the porous layer is hindered by the increase in the thickness of the hole wall and the division of the holes, and it becomes difficult to completely oxidize the porous layer. Therefore, after forming the porous layer, a thin protective film is previously formed on the hole walls by a method such as thermal oxidation to suppress aggregation and coarsening of the holes. In forming the protective film, it is essential to leave a region of single-crystal silicon inside the hole wall, especially in the case of oxidation. Therefore, a film thickness of several nm is sufficient.

On the other hand, in the case where an SOI substrate is manufactured by the bonding method, if the temperature of the post-process such as heat treatment after the bonding is sufficiently lowered and the change in the porous structure is suppressed, this process is omitted. It is also possible.

(HF Dip) The pre-oxidized porous silicon layer may be subjected to an HF dip treatment.

Regarding the HF dip, Sato et al. (N. Sa)
to, K. Sakaguchi, K .; yamagata
a, Y. Fujiyama, and T.M. Yoneha
ra, Proc. of the Seventh In
t. Symp. on Silicon Mater. S
ci. and Tech. , Semiconducto
r Silicon, (Pennington, the
Electrochem. Soc. Inc. , 199
4), p. According to 443), it is reported that the stacking fault can be reduced to about 10 ³ / cm ² by lengthening the time of the HF dip. Depending on the annealing temperature, the structure of the porous layer may be coarsened, and an unetched portion (etching residue) may be generated during the etching of the porous silicon. Therefore, it is necessary to control the HF dip time in an appropriate range. desirable.

After the HF dip, washing and drying are performed to reduce the concentration of residual HF in the porous pores.

(Clogging of holes due to supply of a small amount of raw material)
In the present invention, the initial growth period in which the porous pores are closed is increased.
In the process, SiH _TwoCl_Two, SiH_Four, SiHCl_Three, S
iCl_FourAnd Si_TwoH₆Uses silicon source gas such as
And 20 nm. / Min or less, more preferably 10n
m. / Min. Hereinafter, more preferably, 2 nm / mi
n. Set the source gas flow rate so that the growth rate is below
Good to do. Silane, which is a gas at normal temperature and pressure, is supplied.
It is more preferable from the viewpoint of controllability of the supply amount. As a result,
Depression is further reduced. As in the MBE method, Si
When the substrate temperature is as low as 800 degrees or less.
It is expected that the growth rate is 0.1 nm / min or less.
Good. A small amount of raw material supply process (“Pre-injection
After the closure of the hole is completed
The growth rate is not particularly limited.

The conditions may be the same as those for normal growth on bulk silicon. Alternatively, the growth may be continued at the same growth rate as in the above-mentioned trace amount raw material supply step, and even if the gas type is changed, the requirements of the present invention are not hindered at all. Further, even if the process of supplying a small amount of the raw material is a continuous process, the supply of the raw material may be temporarily interrupted, and then the desired raw material may be supplied again for growth. In addition, N. Sato et. al. Jpn. J. App
l. Phys. 35 (1996) 973. Reported that the stacking fault density was reduced as compared with the conventional method by reducing the supply of a small amount of SiH ₂ Cl _{2 in} the initial stage of growth. However, in such a method, the stacking fault density remains unchanged by increasing the pre-epi pre-bake temperature, and etching residue due to the coarsening of the structure of the porous layer may occur as described above. . In the present invention, the heat treatment before growth is performed at 950 ° C.
Therefore, the porous structure is unlikely to be coarsened.

According to the embodiment of the present invention, a substrate having a porous silicon layer is provided in an apparatus having a small silicon etching amount, and the heat treatment time before growth is controlled.
High-temperature heat treatment as in the conventional method can be avoided. In this case, the crystal defect density can be reduced, and the porous structure can be coarsened and pores can be prevented from being separated.

Further, since the growth temperature, pressure, gas flow rate, etc. can be controlled independently of the above-mentioned initial growth step, the processing temperature is lowered to increase the structure of the porous silicon, or to remove boron from the porous silicon. Auto-doping of impurities such as phosphorus, solid-phase diffusion suppression, raising the growth temperature and increasing the flow rate of the silicon source gas to increase the growth rate to form a thick non-porous single-crystal silicon film in a short time. You may.

Further, the non-porous single crystal layer to be grown is not limited to silicon as described above.
It may be a group IV heteroepitaxy material such as e or SiC, or a compound semiconductor represented by GaAs. In the above-mentioned trace material supply step, a silicon-based gas may be used, and thereafter, another gas may be used for heteroepitaxial growth.

After the step of sealing the pores on the surface of the porous layer (pre-bake, pre-injection), and before the growth of the desired film, the temperature is higher than that of the pre-bake or pre-injection and the semiconductor film does not contain the source gas. It is also preferable to perform heat treatment in an atmosphere (for example, a reducing atmosphere containing hydrogen). The heat treatment is performed by an intermediate baking (interbakin).
g).

(Embodiment 3) An example in which a semiconductor substrate having a non-porous single-crystal silicon layer having a low defect density on a porous single-crystal silicon layer will be described.

A substrate 10 having a porous silicon layer 11 by making at least one surface portion of a single crystal Si substrate porous
(FIG. 15A).

A method similar to that shown in the embodiment example 2, that is, the silicon etching amount is 2 nm or less (more preferably 1 nm or less), and the rate of change r of the haze value of the porous silicon is 3.5 15 (more preferably, within 2) (FIG. 15)
(B)). Thereafter, a non-porous single crystal layer 12 is formed on the porous single crystal silicon layer (FIG. 15C).

Note that the pre-oxidation and the HF dip described above may be performed prior to the heat treatment. Further, it is also preferable to close holes by supplying a small amount of raw material (pre-injection) after the heat treatment.

Next, an SOI substrate is manufactured by a bonding method. First, an insulating layer is formed on at least one of the main surfaces of the non-porous single-crystal silicon and the second substrate. To form a multilayer structure (FIG. 1)
5 (d)). After performing a heat treatment for increasing the bonding strength as necessary, the epitaxial growth layer on the porous silicon is removed from the second substrate through a step of removing the porous silicon by selective etching or the like (FIG. 15E). If it is moved upward, an SOI structure can be obtained.

When the bonding strength is sufficient to withstand the subsequent steps, the process proceeds to the subsequent steps. The back surface side of the substrate on which the porous layer is formed is removed by a mechanical method such as grinding or a chemical method such as etching to expose the porous layer. Alternatively, from the multilayer structure to the substrate 1 at the porous layer
The porous layer may be exposed by peeling (separating) the 15 nonporous portions of 0.
The separation may be performed mechanically by inserting a wedge or the like from the end face or by spraying a fluid like a water jet, or may use ultrasonic waves, thermal stress, or the like. It is preferable that a high porosity layer having low mechanical strength is partially formed in the porous layer in advance to facilitate separation. For example, the configuration of the porous layer 11 is changed from the non-porous single crystal layer 12 side to the first porous layer (10% to 30%).
% Porosity), under which the second porous layer (30% to 7%)
0% porosity).

(Porous Selective Etching) The porous layer remaining on the non-porous single crystal layer 12 is removed by selective etching. Selective etchants are HF, H ₂ O ₂ , H ₂
A mixture of O ₂ is preferably used. In order to remove bubbles generated during the reaction, ethyl alcohol in the mixture,
Isopropyl alcohol or a surfactant may be added.

In this method, since the structural change and coarsening of the porous layer and the division of the pores are suppressed, the deterioration of the selectivity in the selective etching is small.

The second substrate to which the non-porous single-crystal silicon layer formed on the porous silicon is bonded is not particularly limited. A silicon wafer, a silicon wafer on which a thermally oxidized silicon film is formed, a transparent substrate such as a quartz wafer, a sapphire wafer or the like, the non-porous single-crystal silicon surface,
Alternatively, it is sufficient that the film has a smoothness capable of being in close contact with the surface of the film formed thereon. When bonding an insulating substrate, the insulating layer 14 can be omitted.

The non-porous single-crystal silicon layer may be bonded to the second substrate as it is, or a film may be formed before bonding. Films to be formed include silicon oxide, silicon nitride, SiGe, SiC, III-V compound, II
A single crystal film such as a -VI compound may be formed, or a plurality of these films may be stacked.

Before bonding, it is preferable to clean the bonded surface cleanly. The cleaning may employ a preceding step used in a normal semiconductor process. Irradiation with nitrogen plasma or the like before bonding can increase the bonding strength.

After bonding, it is desirable to perform a heat treatment to increase the bonding strength.

(Hydrogen annealing) There are irregularities reflecting the period of the holes and side walls of the surface porous silicon after the removal of the porous silicon. This is because this surface corresponds to the interface between non-porous single-crystal silicon and porous silicon, but both are single-crystal silicon in the first place, and the only difference is whether or not there is a hole. The surface irregularities can be removed by polishing or the like. However, when heat treatment is performed in a hydrogen atmosphere, the irregularities can be removed without substantially reducing the thickness of the non-porous single-crystal silicon. Hydrogen annealing can be performed under any of atmospheric pressure, high pressure, and slightly reduced pressure.

The annealing temperature is from 800 ° C. to the melting point of silicon, more preferably from 900 ° C. to 135 ° C.
0 ° C. or less.

(Control of Boron Concentration) On the other hand, the crystallinity of the epitaxial layer on the porous silicon is generally P ⁺ Si
^(- 0.01Ω · cm boron doped) who made porous to ^{have, P - Si (- 0.01Ω ·} cm bo
Although it is much better than the case of forming boro-doped, high-concentration Boron sometimes diffuses into the epitaxial silicon layer by auto-doping or solid-phase diffusion during epitaxial growth. Boron diffused into the epitaxial silicon layer remains even after porous silicon is removed, which may hinder the suppression of the impurity concentration of the active layer in SOI. To solve this, Sato et al. (N. Sato, and T. Yone)
hara, Appl. Phys. Lett. 65 (19
94) p. By annealing the substrate having the SOI structure completed in 1924) in hydrogen, S having a low boron diffusion rate is obtained.
By removing the natural oxide film on the surface of the OI layer and diffusing boron in the SOI layer to the outside, a low concentration is realized. However, excessive boron diffusion into the epitaxial silicon layer causes boron to be taken into the buried oxide film, resulting in a longer hydrogen annealing, increasing the process cost, or controlling the boron concentration in the buried oxide film. In some cases, problems such as deterioration of the product may occur. In order to solve this problem, it is effective to suppress the diffusion of boron by lowering the conditions for forming the epitaxial silicon layer. According to the present invention, conditions for forming the epitaxial silicon layer can be set independently of blockage of the holes, so that appropriate conditions can be set.

(FIPOS Method) Even after the epitaxial growth layer is partially removed by the FIPOS method without performing the bonding process, the SOI structure may be formed by selectively oxidizing the porous silicon by the oxidation treatment. good. In the present method, since the structural change and coarsening of the porous layer and the separation of the pores are suppressed, the selectivity is less deteriorated even in the selective oxidation.

(Heteroepitaxy) or GaAs
A compound semiconductor such as s and a group IV heteroepitaxy such as SiC and SiGe may be performed. In heteroepitaxy, porous silicon acts as a stress buffering material, which can relieve stress due to lattice mismatch, and can reduce the crystal defect density of the non-porous single crystal silicon layer. The defect density of the epitaxial growth layer is also reduced. In the present method, since the structural change and coarsening of the porous layer and the division of the pores are suppressed, the deterioration of the stress buffering effect is small.

(Other Applications) Since porous silicon has a gettering action, a MOS transistor and a bipolar transistor can be formed on the non-porous single-crystal silicon layer manufactured according to the present invention without forming the SOI structure as described above. If a substrate is formed directly, a substrate having high resistance to impurity contamination such as metal contamination during the process can be obtained.

In the present method, the heat treatment temperature,
In particular, since the heat treatment temperature before sealing the holes can be lowered, aggregation, expansion, and division of the holes in the porous layer can be suppressed, so that the porous layer can be selectively etched in a later step of the bonding method. Does not degrade the selectivity of That is, in removing the porous layer, the crystallinity of the non-porous single-crystal silicon layer can be improved without generating any residue. Also, in the FIPOS method, the oxidation rate of the selective oxidation of the porous layer is not deteriorated.

Hereinafter, specific examples of the present invention will be described.

Example 1-950 ° C., 600 Torr
Prebake (2s, 120s), Preinjec
1) Boron is added as a p-type impurity, and the specific resistance is 0.01.
^{5Ω · cm + / - 0.005Ω ·} CZ6 inch (100) were in cm were prepared p ⁺ silicon wafer.

2) 49% HF and ethyl alcohol in 2:
Anode the silicon wafer in a solution mixed at a ratio of 1.
And a silicon wafer with a 6-inch diameter platinum plate as the cathode
They were installed facing each other. Back side of the silicon wafer
The side is through the same solution, another p ⁺With the front side of the Si wafer
Opposite, the endmost wafer is a 6 inch diameter platinum plate
Faced. Solution between wafers is separated by wafer
And arranged so as not to energize. The silicon wafer
And current density between 10mA / cm^TwoFor 12 minutes
To anodize the silicon wafer in the previous period (Anodi
ze), forming a porous silicon 12 μm thick on the surface
Was.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in an oxygen atmosphere at 400 degrees for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer was exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to form an ultra-thin silicon oxide formed on the surface of the porous layer as overflow rinse. The film was removed.

5) Thereafter, as a pre-bake step, 110
Heat treatment was performed at 0 ° C. for 120 seconds.

The haze value immediately before prebaking was 9.1 pp.
m, and the haze value after prebaking was 34.5 ppm.
Met. That is, r = 3.8 (> 3.5).

Then, the rate of change r of the haze value is 1 ≦ r ≦
When the heat treatment conditions were variously changed so as to satisfy 3.5, when the heat treatment was performed at 950 ° C. for 120 seconds, the change rate h of the haze value was 2.8 (<3.5). I understand.

After pre-baking under the condition that r = 2.8, the pressure was 600 Torr in the same reaction vessel.
Then, SiH ₄ is added to a carrier gas of hydrogen so as to have a concentration of 28 ppm, and a treatment is performed for 200 seconds. Then, the addition of SiH ₄ is completed.
℃, and then the concentration of SiH ₂ Cl ₂ is 0.5 mol
% To form a non-porous single-crystal silicon film of 2 μm. Then, the wafer was subjected to defect revealing etching to reveal the crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects had a stacking fault of 99% or more.
The stacking fault density was 160 / cm ² .

On the other hand, when the rate of change of the haze value was r = 3.8, when the epitaxial growth was carried out under the same conditions, the stacking fault density was found to be 1.5 × 10 ⁴ / cm ² . From the above, it was confirmed that a single crystal Si layer having a very low stacking fault density can be formed by performing pre-baking under the condition that the haze value is within a certain range.

The stacking faults were observed under a microscope after etching to reveal the defects. Specifically, K ₂ Cr ₂ in the Secco etching method is used as an etching solution.
An aqueous solution of a mixture of O ₇ (0.15M) and 49% -HF (2: 1) diluted with pure water was used to reduce the etching rate, and introduced into the non-porous single-crystal silicon layer on the wafer surface. After clarifying the crystal defects, observation was performed with a Nomarski differential interference microscope to determine the stacking fault density.

(Example 2-950 ° C., 600 Torr)
Prebake (2s, 120s), Preinjec
1) Boron is added as a p-type impurity, and the specific resistance is 0.01.
^{5Ω · cm + / - 0.005Ω ·} CZ6 inch (100) were in cm were prepared p ⁺ silicon wafer.

2) In a solution in which a 49% HF aqueous solution and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a 6-inch diameter platinum plate was set as a cathode so as to face the silicon wafer. The back side of the silicon wafer was opposed to the front side of another p ⁺ Si wafer through the same solution, and the platinum wafer having a diameter of 6 inches was opposed to the endmost wafer. The solution between the wafers was separated by the wafer and arranged so as not to conduct. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer to form a 12 μm thick porous silicon on the surface.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour.

In this oxidation treatment, only an oxide film of approximately 50 ° or less is formed. Therefore, the silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside. Have been.

4) The wafer was exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to form an ultra-thin silicon oxide formed on the surface of the porous layer as overflow rinse. The film was removed.

5) The wafer is placed in a load lock chamber in which a wafer is put into a wafer carrier and set, and a load lock chamber of an epitaxial CVD growth apparatus in which a transfer chamber in which a wafer transfer robot is set and a process chamber are connected. Was set in a wafer carrier.

The pressure in the load lock chamber was reduced to 1 Torr or less from the atmospheric pressure by a dry pump, and then N ₂ gas was supplied to 80 Torr. The transfer chamber is N ₂
And kept at 80 Torr. Process chamber has CVD on carbon to hold wafers
-A susceptor coated with SiC is provided. The susceptor has been previously heated to about 750 ° C. by an IR lamp. In the process chamber, a hydrogen purifier using a heated palladium alloy supplies purified hydrogen gas from the purifier to the process chamber through an approximately 10-meter polished stainless steel pipe.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) When the pressure in the process chamber is 600
After setting to Torr, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C. per minute.
After holding at 950 ° C. for 2 seconds, the temperature was lowered to 750 ° C., and the wafer was again taken out of the load lock chamber via the transfer chamber by the transfer robot. The other wafer was kept at 950 ° C. for 120 seconds, and the rest was returned to the load lock chamber by performing the same processing as the above-described wafer.

7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze on the surface of the porous layer was observed with a foreign matter inspection device. The average haze value of the porous material on the wafer after 2 seconds treatment was 11.9 ppm. The haze value of the porous material after the treatment for 120 seconds was 25.7, which was about 1.3 and 2.8 times the haze value of the sample before being installed in the epitaxial growth apparatus, 9.1 ppm. That is, r = 1.
3,2.8.

8) The SOI substrate prepared in advance is dipped in HF, washed with water and dried, and then the thickness of the SOI layer is measured with an optical interference thickness meter. After processing, it was removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm in all cases.

9) The wafer after the processing of 4) is completed,
Was transferred to the process chamber of the epitaxial growth apparatus by the method described in (1).

10) The pressure of the process chamber was set to 600
After setting to Torr, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C. per minute.
After holding at 950 ° C. for 2 seconds as a heat treatment (pre-bake treatment), SiH ₄ is added to a hydrogen carrier gas so as to have a concentration of 28 ppm, and a treatment is performed for 200 seconds, and the addition of SiH ₄ is completed. 90 to 80 Torr
The temperature was lowered to 0 ° C., and the concentration of SiH ₂ Cl ₂ was 0.5mo.
1%, a non-porous single-crystal silicon film is formed to a thickness of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is again loaded through the transfer chamber by the transfer robot. I took it out of the room. Another wafer was prebaked at 950 ° C. in a hydrogen atmosphere for 12 hours.
The time was set to 0 second, and the same processing was carried out except for this, and returned to the load lock chamber. When the SiH ₄ gas having a concentration of 28 ppm is added, the growth rate is 3.3 nm / min.

11) The wafer after the processing of 10) is removed.
Revealing etching to non-porous single crystal silicon layer
After revealing the introduced crystal defects, the Nomarski differentiation
Observed with an interference microscope. The observed defects were 9 stacking faults.
9% or more. Stacking fault density is 2 seconds pre-baked
In case of 84 pieces / cm^Two, For pre-bake 60 seconds, 1
60 pieces / cm^TwoIn the case of pre-baking 1100 ° C for 120 seconds
1.5 × 10^Four/ Cm^TwoCompared with, it decreased sharply. Especially 9
100 pieces / cm in pre-baking at 50 ° C for 2 seconds ^TwoBelow
Stacking fault density was obtained.

(Example 3-950 ° C., 600 Torr)
Prebake (2e), Preinjection,
Epi-0.32 μm ELTRAN) 1) Boron is added as a p-type impurity and the specific resistance is 0.01
^{5Ω · cm + / - 0.01Ω ·} CZ8 inch (100) were in cm were prepared p ⁺ silicon wafer.

2) In a solution in which a 49% HF aqueous solution and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a 6-inch diameter platinum plate was set as a cathode so as to face the silicon wafer. The back side of the silicon wafer was opposed to the front side of another p ⁺ Si wafer through the same solution, and the platinum wafer having a diameter of 6 inches was opposed to the endmost wafer. The solution between the wafers was separated by the wafer and arranged so as not to conduct. An electric current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anode).
size), a plurality of 12 μm-thick porous silicon were formed on the surface.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour. Since this oxidation treatment forms only an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside.

4) In an aqueous HF solution diluted to 1.25%,
The wafer was exposed for about 30 seconds, then immersed in pure water for 10 minutes, and overflow rinsed to remove the ultra-thin silicon oxide film formed on the surface of the porous layer.

5) Set the wafer in the wafer carrier
Set of load lock chamber and wafer transfer robot
Transfer chamber and process chamber are connected
In front of load lock chamber of epitaxial CVD growth equipment
The wafer was placed in a wafer carrier. Rhodoulo
The pressure chamber is reduced from atmospheric pressure to less than 1 Torr by dry pump.
After decompression, N_TwoTo 80 Torr. Transfer
Loading chamber is N _TwoAnd kept at 80 Torr
Have been. Holds wafer in process chamber
Susceptor with CVD-SiC coated on carbon
is set up. The susceptor is set in advance by an IR lamp.
The temperature has been raised to about 750 ° C. Process chamber
Inside the furnace is a hydrogen purifier using a heated palladium alloy.
The purified hydrogen gas within about 10m from the refiner.
Surface polished stainless steel piping to process chamber
Supplied.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) The wafer transferred on the susceptor is
Heating with a lamp, the temperature was increased at a rate of 100 ° C. per minute, and the temperature was held at 950 ° C. for 2 seconds as a pre-bake treatment. Met.

Next, SiH ₄ Cl ₂ is added to a hydrogen carrier gas so as to have a concentration of 28 ppm, and a treatment is performed for 200 seconds. Then, the addition of SiH ₄ is completed.
The temperature was lowered to 00 ° C and the concentration of SiH ₄ Cl ₂ was 0.5 m
ol% to form a non-porous single crystal silicon film having a thickness of 0.32 μm.
The temperature was lowered to ° C., and the wafer was again taken out of the load lock chamber via the transfer chamber by the transfer robot. The thickness of the formed non-porous single-crystal silicon layer is 0.32 μm on average.
m, maximum value-minimum value = 8 nm.

7) A wafer in which non-porous single-crystal silicon is epitaxially grown is placed in a vertical furnace, and a wafer containing a mixture of water vapor and residual oxygen formed by burning oxygen and hydrogen is used.
The surface of the non-porous single crystal silicon was oxidized by heat treatment at 00 ° C. to form a silicon oxide film having a thickness of 208 nm.

8) After the above-mentioned wafer and the second silicon wafer are cleanly cleaned in a cleaning line of a silicon semiconductor process, the first main surfaces of both wafers are gently overlapped with each other.
When the center was pressed, the two wafers were integrated.

9) Subsequently, the integrated wafer set was placed in a vertical furnace and heat-treated at 1100 ° C. for 1 hour in an oxygen atmosphere.

10) The back surface of the wafer on which the porous silicon was formed was ground with a grinder to expose the porous silicon over the entire surface of the wafer.

11) When the exposed porous silicon layer was immersed in a mixed solution of HF and hydrogen peroxide solution, all the porous silicon was removed in about 2 hours, and the entire surface of the wafer was replaced with a non-porous single crystal silicon layer. An interference color due to the thermally oxidized silicon film was observed.

12) The wafer after the treatment of 11) is cleaned by a cleaning line generally used in a silicon semiconductor device process, and then set in a vertical hydrogen annealing furnace at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere. Heat treatment was performed. Hydrogen gas is purified by a commercially available hydrogen purifier using a palladium alloy connected to the apparatus by an approximately 7 m internally polished stainless steel pipe.

13) Thus, an SOI structure wafer having a 200 nm silicon oxide layer and a 200 nm single crystal silicon layer laminated on the second silicon wafer was manufactured.

The average thickness of the single crystal silicon layer is 201 n.
m, maximum value-minimum value = 8 nm.

14) After removing the single-crystal silicon layer by 130 nm from the wafer by defect revealing etching, 49
% HF for 3 minutes. As a result, the buried oxide film is etched by HF from the portion of the crystal defect remaining in the single crystal silicon layer etched by the defect revealing etching, and the defect density can be easily measured with a Nomarski differential interference microscope. The observed defect density was 64 defects / cm
^{Was 2} . Stacking faults introduced into the non-porous single-crystal silicon layer were reduced by the hydrogen annealing treatment. A thin film SOI layer having a defect density of less than 100 defects / cm ² and a uniform film thickness was obtained.

(Example 4-950 ° C., 600 Torr)
Prebake (2s, 120s), No Prein
(Jection, Epi-2 μm) 1) Boron is added as a p-type impurity, and the specific resistance is 0.01.
5Ω · cm ⁺ / ^- was to 0.005Ω · cm, was prepared to 6 inches (100) p ⁺ silicon wafers (CZ wafers).

2) 49% HF and ethyl alcohol are used in 2:
Anode the silicon wafer in a solution mixed at a ratio of 1.
And a silicon wafer with a 6-inch diameter platinum plate as the cathode
They were installed facing each other. Back side of the silicon wafer
The side is through the same solution, another p ⁺With the front side of the Si wafer
Opposite, the endmost wafer is a 6 inch diameter platinum plate
Faced. Solution between wafers is separated by wafer
And placed so as not to conduct. The silicon wafer
And current density between 10mA / cm^TwoFor 12 minutes
To anodize the silicon wafer (Anodi)
ze), forming a porous silicon 12 μm thick on the surface
Was.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer is exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and the ultra-thin oxidation formed on the surface of the porous layer The silicon film was removed.

5) The wafer is placed in a load lock chamber of an epitaxial CVD growth apparatus in which a process chamber is connected to a load lock chamber in which a wafer is loaded and set in a wafer carrier, and a transfer chamber in which a wafer transfer robot is set. It was installed in a carrier.

After the pressure in the load lock chamber is reduced from the atmospheric pressure to 1 Torr or less by a dry pump, N ₂ is supplied to the load lock chamber for 8 hours.
0 Torr.

The transfer chamber was set to 80 T by flowing N ₂ in advance.
orr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC for holding a wafer is provided. The susceptor has been previously heated to about 750 ° C. by an IR lamp. In the process chamber, a hydrogen purifier using a heated palladium alloy supplies purified hydrogen gas from the purifier to the process chamber through an approximately 10-meter polished stainless steel pipe.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and set on the susceptor.

6) Set the pressure of the process chamber to 600 T
After that, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C./min.
After holding at 50 ° C. for 2 seconds, the temperature was lowered to 750 ° C.
The wafer was taken out again into the load lock chamber via the transfer chamber by the transfer robot. Another wafer is 95
The temperature was maintained at 0 ° C. for 60 seconds, and the same treatment was carried out except for this, and returned to the load lock chamber.

7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze value of the surface of the porous layer was measured with a foreign matter inspection device. The haze value of the porous material after the treatment for 60 seconds was 16.3, and the haze value of the sample before being set in the epitaxial growth apparatus was 9.1, respectively.
3, 1.8 times.

8) The SOI substrate prepared in advance is dipped in HF, washed with water and dried, and then
The thickness of the layer was measured by an optical interference type thickness meter, subjected to the processes of 5) and 6), and taken out from the load lock. SOI again
When the thickness of the layer was measured, the amount of decrease in the thickness of the SOI layer was
All were less than 1 nm.

9) The wafer subjected to the processing of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).

10) When the pressure in the process chamber is 600
After setting to Torr, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C. per minute.
After holding at 950 ° C. for 2 seconds as a pre-bake treatment, the temperature was lowered to 900 ° C., the pressure was set to 80 Torr, and SiH ₂
Cl ₂ is added to a concentration of 0.5 mol% to form a non-porous single-crystal silicon film of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is transferred again by the transfer robot. It was taken out to the load lock chamber via the chamber. The other wafer was returned to the load lock chamber by performing the same processing except that the pre-bake processing time in a hydrogen atmosphere at 950 ° C. was 60 seconds.

11) The wafer having been subjected to the process 10) was subjected to defect revealing etching to reveal the crystal defects introduced into the non-porous single-crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 9 stacking faults.
9% or more. The stacking fault density was 170 defects / cm ^{2 in} the case of pre-baking for 2 seconds, and in the case of pre-baking for 60 seconds.
In 270 / cm ^2, compared to 1.5 × 10 ⁴ / cm ² in the case of prebaking 1100 ° C. 120 seconds, depleted.

Example 5—900 ° C., 450 Torr
Prebake (2s, 120s), Preinjec
1) Boron is added as a p-type impurity, and the specific resistance is 0.02 μm.
^{15Ω · cm + / - 0.005Ω ·} 6 inches (100), which was in cm were prepared p ⁺ silicon wafers (CZ wafers).

2) 49% HF and ethyl alcohol:
Anode the silicon wafer in a solution mixed at a ratio of 1.
And a silicon wafer with a 6-inch diameter platinum plate as the cathode
They were installed facing each other. Back side of the silicon wafer
The side is through the same solution, another p ⁺With the front side of the Si wafer
Opposite, the endmost wafer is a 6 inch diameter platinum plate
Faced. Solution between wafers is separated by wafer
And placed so as not to conduct. The silicon wafer
And current density between 10mA / cm^TwoFor 12 minutes
To anodize the silicon wafer (Anodi)
ze), forming a porous silicon 12 μm thick on the surface
Was.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and ultra-thin oxidation formed on the surface of the porous layer The silicon film was removed.

5) Set the wafer in the wafer carrier
Set of load lock chamber and wafer transfer robot
Transfer chamber and process chamber are connected
In front of load lock chamber of epitaxial CVD growth equipment
The wafer was placed in a wafer carrier. Rhodoulo
The pressure chamber is reduced from atmospheric pressure to less than 1 Torr by dry pump.
After decompression, N_TwoTo 80 Torr. Transfer
Loading chamber is N _TwoAnd kept at 80 Torr
Have been. Holds wafer in process chamber
Susceptor with CVD-SiC coated on carbon
is set up. The susceptor is set in advance by an IR lamp.
The temperature has been raised to about 750 ° C. Process chamber
Inside the furnace is a hydrogen purifier using a heated palladium alloy.
The purified hydrogen gas within about 10m from the refiner.
Surface polished stainless steel piping to process chamber
Supplied.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) When the pressure of the process chamber is 450 T
After that, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C./min.
After holding at 00 ° C for 2 seconds, the temperature was lowered to 750 ° C,
The wafer was taken out again into the load lock chamber via the transfer chamber by the transfer robot. Another wafer is 90
The temperature was kept at 0 ° C. for 120 seconds, and the same treatment was carried out except for this, and returned to the load lock chamber.

7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze value of the surface of the porous layer was measured with a foreign matter inspection device. The average haze value of the porous material after the treatment for 60 seconds was 14.3, which was about 1.3 and 1.6 times the average haze value 9.2 of the sample before being placed in the epitaxial growth apparatus, respectively. .

8) The SOI substrate prepared in advance is dipped in HF, washed with water and dried, and then
The thickness of the layer was measured by an optical interference type thickness meter, subjected to the processes of 5) and 6), and taken out from the load lock. SOI again
When the thickness of the layer was measured, the amount of decrease in the thickness of the SOI layer was
All were less than 1 nm.

9) The wafer after the processing of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).

10) The pressure of the process chamber was set at 450
After setting to Torr, the wafer transferred on the susceptor was heated by an IR lamp and heated at a rate of 100 ° C. per minute.
After holding at 900 ° C. for 2 seconds as a pre-bake treatment, SiH ₄ was added to the hydrogen carrier gas so that the concentration became 28 ppm.
, And treated for 200 seconds to complete the addition of SiH _4. Then, the pressure is reduced to 80 Torr, the temperature is reduced to 900 ° C., and then, SiH ₂ Cl ₂ is added to a concentration of 0.7 mol%. To make the non-porous single-crystal silicon film 2 μm
The wafer was formed, the temperature was lowered to 750 ° C. in a hydrogen atmosphere, and the wafer was again taken out of the load lock chamber via the transfer chamber by the transfer robot. Another wafer 900 ° C
The pre-bake processing time in a hydrogen atmosphere was set to 60 seconds, and the same processing was performed except for this, and the pre-baking processing was returned to the load lock chamber.

11) The wafer subjected to the processing of 10) was subjected to defect revealing etching to reveal the crystal defects introduced into the non-porous single-crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 9 stacking faults.
9% or more. The stacking fault density was 350 defects / cm ^{2 in} the case of pre-baking for 2 seconds, and in the case of pre-baking for 60 seconds.
At 400 pieces / cm ^2, it is significantly reduced compared to 1.5 × 10 ⁴ / cm ² in the case of pre-baking 1100 ° C. for 120 seconds, and 100
A defect density of less than 0 / cm ² was realized.

Example 6-870 ° C., 80 Torr P
rebake (5s, 60s), Preinjecti
on, Epi-2 μm) 1) Boron is added as a p-type impurity to have a specific resistance of 0.0
^{15Ω · cm + / - 0.005Ω ·} 6 inches (100), which was in cm were prepared p ⁺ silicon wafers (CZ wafers).

2) 49% HF and ethyl alcohol in 2:
Anode the silicon wafer in a solution mixed at a ratio of 1.
And a silicon wafer with a 6-inch diameter platinum plate as the cathode
They were installed facing each other. Back side of the silicon wafer
The side is through the same solution, another p ⁺With the front side of the Si wafer
Opposite, the endmost wafer is a 6 inch diameter platinum plate
Faced. Solution between wafers is separated by wafer
And placed so as not to conduct. The silicon wafer
And current density between 10mA / cm^TwoFor 12 minutes
To anodize the silicon wafer (Anodi)
ze), forming a porous silicon 12 μm thick on the surface
Was.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer is exposed to an aqueous HF solution diluted to 1.3% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and the ultra-thin oxidation formed on the surface of the porous layer The silicon film was removed.

5) Set the wafer in the wafer carrier
Set of load lock chamber and wafer transfer robot
Transfer chamber and process chamber are connected
In front of load lock chamber of epitaxial CVD growth equipment
The wafer was placed in a wafer carrier. Rhodoulo
The pressure chamber is reduced from atmospheric pressure to less than 1 Torr by dry pump.
After decompression, N_TwoTo 80 Torr. Transfer
Loading chamber is N _TwoAnd kept at 80 Torr
Have been. Holds wafer in process chamber
Susceptor with CVD-SiC coated on carbon
is set up. The susceptor is set in advance by an IR lamp.
The temperature has been raised to about 750 ° C. Process chamber
Inside the furnace is a hydrogen purifier using a heated palladium alloy.
The purified hydrogen gas within about 10m from the refiner.
Surface polished stainless steel piping to process chamber
Supplied.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) The pressure of the process chamber was set to 80
rr, the wafer transferred on the susceptor was heated by an IR lamp, and the temperature was increased at a rate of 100 ° C./min.
After holding for 2 seconds, the temperature was decreased to 750 ° C., and the wafer was again taken out of the load lock chamber via the transfer chamber by the transfer robot. The other wafer is 60
After holding for 2 seconds, the same processing was carried out except for this, and returned to the load lock chamber.

7) The load lock chamber was opened to the atmosphere, and the wafer was taken out.
scan 6 with oblique incidence of argon laser
When the haze value of the porous layer surface was measured at 420,
The average haze value of the porous material on the wafer processed in seconds is 10.
The average haze value of the porous material treated for 2, 30 seconds was 19.5.
The average haze value of the sample before being set in the epitaxial growth apparatus was 8.5, which was about 1.2 to 2.3 times, respectively.

8) The SOI substrate prepared in advance is dipped in HF, washed with water and dried, and then the thickness of the SOI layer is measured by an optical interference type thickness meter. After processing, it was removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm in all cases.

9) The wafer having undergone the processing of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).

10) When the pressure in the process chamber is 80 T
After setting to orr, the wafer transferred on the susceptor was heated by an IR lamp, heated at a rate of 100 ° C./min, and held at 860 ° C. for 2 seconds as a pre-bake treatment.
SiH ₄ was added to the hydrogen carrier gas so that the concentration became 5 ppm, and the treatment was performed for 150 seconds, and the addition of SiH ₄ was completed.
Thereafter, SiH ₂ Cl ₂ is added to a concentration of 1 mol% to form a non-porous single-crystal silicon film of 2 μm,
The temperature was lowered to 750 ° C. in a hydrogen atmosphere, and the wafer was again taken out of the load lock chamber via the transfer chamber by the transfer robot. The other wafer was returned to the load lock chamber by performing the same processing except that the pre-bake processing time was 60 seconds.

11) The wafer subjected to the processing of 10) was subjected to defect revealing etching to reveal the crystal defects introduced into the non-porous single-crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 9 stacking faults.
9% or more. The stacking fault density is 120 defects / cm ^{2 in} the case of pre-baking for 5 seconds, and in the case of pre-baking for 30 seconds.
At 430 pieces / cm ² , the pre-bake was drastically reduced compared to 1.5 × 10 ⁴ / cm ² at 1100 ° C. for 120 seconds.
A defect density of less than 0 / cm ² was realized.

Example 7-950 ° C., Prebake
(2s), Preinjection, Epi-0.3
2 μm) 1) Boron is added as a p-type impurity, and the specific resistance is
0.015Ω · cm ⁺ / ^- is 0.01Ω · cm, 8
Inch plane orientation (100) p ⁺ silicon wafer (CZ
Wafer).

2) The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (min) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 5 (mA · cm ⁻² ) Thickness of porous Si: 5 (μm) Further, current density: 50 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 10 (sec) Thickness of porous Si: up to 0.2 (μm) In anodization performed at 50 (mA · cm ⁻² ), porous S
The porosity of the i-layer was increased and a structurally fragile high porosity thin layer was formed. That is, a low-porosity porous layer and a high-porosity porous layer were formed in this order from the surface side of the silicon wafer.

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment (pre-oxidation) for one hour in an oxygen atmosphere at 400 degrees. Since this oxidation process forms only an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and a single-crystal silicon region remains inside.

4) The wafer is exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to form an ultra-thin silicon oxide formed on the surface of the porous layer as an overflow rinse. The film was removed.

5) A load lock chamber in which a wafer is placed in a wafer carrier and set therein, a transfer chamber in which a wafer transfer robot is set, and a load lock chamber of an epitaxial CVD growth apparatus in which a process chamber is connected. The wafer was set in a wafer carrier.

After the pressure in the load lock chamber is reduced from the atmospheric pressure to 1 Torr or less by a dry pump, N ₂ is supplied to the load lock chamber for 8 hours.
0 Torr.

[0259] transport chamber is flushed beforehand N ₂ 80
Torr. The process chamber contains
A susceptor in which carbon is coated with CVD-SiC for holding a wafer is provided. The susceptor has been previously heated to about 750 ° C. by an IR lamp. In the process chamber, a hydrogen purifier using a heated palladium alloy supplies purified hydrogen gas from the purifier to the process chamber through an approximately 10-meter polished stainless steel pipe.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) The wafer transferred on the susceptor is
After heating with a lamp and increasing the temperature at a rate of 100 ° C./min, and holding at 950 ° C. for 2 seconds as a heat treatment (pre-bake treatment),
Si as hydrogen carrier gas to a concentration of 28 ppm
H ₄ was added and the treatment was performed for 200 seconds, and the addition of SiH ₄ was completed. Then, the temperature was lowered to 900 ° C.
H ₂ Cl ₂ was added to a concentration of 0.5 mol% to form a non-porous single-crystal silicon film of 0.32 μm, the temperature was lowered to 750 ° C. in a hydrogen atmosphere, and the wafer was transferred to the transfer robot again. Out of the load lock chamber via the transfer chamber. The thickness of the formed non-porous single-crystal silicon layer was 0.32 μm on average, and maximum value−minimum value = 8 nm. The haze value before the heat treatment was 9.5, whereas the haze value after the heat treatment was 11.4. That is, r = 1.2.

The SOI substrate prepared in advance is H
After F-dip, washing with water and drying, the thickness of the SOI layer was measured with an optical interference type thickness meter, and the treatments 5) and 6) were performed, and the film was taken out from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was 1 nm.
Was less than.

7) A wafer on which non-porous single-crystal silicon was epitaxially grown was placed in a vertical furnace, and a wafer containing 10% water and a mixture of water vapor and residual oxygen formed by burning oxygen and hydrogen.
The surface of the non-porous single-crystal silicon was oxidized by heat treatment at 00 ° C. to form a silicon oxide film having a thickness of 208 nm.

8) After the above wafer and the second silicon wafer have been cleanly cleaned in a cleaning line of a silicon semiconductor process, the first main surfaces of both wafers are gently overlapped with each other.
When the center was pressed, the two wafers were integrated.

9) Subsequently, the integrated wafer set was placed in a vertical furnace and processed at 1100 ° C. for 1 hour in an oxygen atmosphere.

10) When a water jet was sprayed on the side surface of the bonded wafer, the high porosity layer was cracked and split. The splitting method is to apply external pressure such as pressure, pull, shear, wedge, etc. in addition to water jet,
There are a method of applying ultrasonic waves, a method of applying heat, a method of expanding porous Si from the periphery by oxidation and applying an internal pressure in the porous Si, a method of applying heat stress in a pulse shape, and a method of softening the porous Si. . It is possible to separate in any of these ways.

11) A second silicon wafer having an exposed porous silicon layer on its surface was immersed in a mixed solution of HF and hydrogen peroxide solution. All of the porous silicon was removed in about 2 hours, and the entire surface of the wafer was removed. As a result, interference colors between the non-porous single-crystal silicon layer and the thermally oxidized silicon film were observed.

12) The wafer after the treatment of 11) is cleaned by a cleaning line generally used in a silicon semiconductor device process, and then set in a vertical hydrogen annealing furnace at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere. Heat treatment was performed. Hydrogen gas is purified by a commercially available hydrogen purifier using a palladium alloy connected to the apparatus by an approximately 7 m internally polished stainless steel pipe.

13) Thus, a SOI-structured wafer having a 200 nm silicon oxide layer and a 200 nm single crystal silicon layer laminated on the second silicon wafer was manufactured.

The average thickness of the single crystal silicon layer is 201 n.
The difference between the maximum value and the minimum value of m and height was 8 nm.

14) The wafer of 13) was subjected to defect revealing etching to remove the single crystal silicon layer by 130 nm, and then immersed in 49% HF for 3 minutes. As a result, the buried oxide film is etched by HF from the portion of the crystal defect remaining in the single crystal silicon layer etched by the defect revealing etching, and the defect density can be easily measured with a Nomarski differential interference microscope. The observed defect density was 64
Pieces / cm ² . Stacking faults introduced into the non-porous single-crystal silicon layer were reduced by the hydrogen annealing treatment. A thin film SOI layer having a defect density of less than 100 defects / cm ² and a uniform film thickness was obtained.

Example 8-950 ° C., 80 Torr P
rebak (2s), Prejection, E
pi-0.01 μm Hetero-epitaxy) 1) Specific resistance 0.01 Ω · cm having a thickness of 615 μm
P-type or n-type (100) single crystal S having a diameter of 6 inches
By anodizing four i-substrates in a solution diluted with HF alcohol, a porous Si layer was formed on one of the mirror-finished main surfaces.

2) Anodizing conditions were as follows.

Current density: 7 mA / cm ² Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1:
1 hour: 12 minutes Thickness of porous Si layer: 10 μm Porosity: 20%

3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment in a 400 ° C. oxygen atmosphere for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, the silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside.

4) The wafer is exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and ultra-thin oxidation formed on the surface of the porous layer The silicon film was removed.

5) Set the wafer in the wafer carrier
Set of load lock chamber and wafer transfer robot
Transfer chamber and process chamber are connected
In front of load lock chamber of epitaxial CVD growth equipment
The wafer was placed in a wafer carrier. Rhodoulo
The pressure chamber is reduced from atmospheric pressure to less than 1 Torr by dry pump.
After decompression, N_TwoTo 80 Torr. Transfer
Loading chamber is N _TwoAnd kept at 80 Torr
Have been. Holds wafer in process chamber
Susceptor with CVD-SiC coated on carbon
is set up. The susceptor is set in advance by an IR lamp.
The temperature has been raised to about 750 ° C. Process chamber
Inside the furnace is a hydrogen purifier using a heated palladium alloy.
The purified hydrogen gas within about 10m from the refiner.
Surface polished stainless steel piping to process chamber
Supplied.

The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot, and was set on the susceptor.

6) The wafer transferred on the susceptor is
After heating with a lamp and increasing the temperature at a rate of 100 ° C./min, and holding at 950 ° C. for 2 seconds as a heat treatment (pre-bake treatment),
Si as hydrogen carrier gas to a concentration of 28 ppm
H ₄ is added and the treatment is performed for 200 seconds, and the addition of SiH ₄ is completed. Thereafter, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is again loaded through the transfer chamber by the transfer robot. Removed to the lock room. The thickness of the formed non-porous single-crystal silicon layer was 0.03 μm on average. In addition, the haze value before heat treatment was 8.5, after heat treatment was 8.5.

On this porous Si, MOCVD (Meta
l Organic Chemical Vapor
1 μm of single-crystal GaAs by Deposition method.
m was epitaxially grown. The growth conditions were as follows.

Source gas: TMG / AsH ₃ / H ₂ Gas pressure: 80 Torr Temperature: 700 ° C.

As a result of observing the cross section with a transmission electron microscope, G
No crystal defects were introduced into the aAs layer, and it was confirmed that a GaAs layer having good crystallinity was formed. At the same time, it was also confirmed that an extremely steep interface was formed between the porous Si layer whose surface was sealed with Si.

Further, the number of crystal defects revealed by an optical microscope by the defect revealing etching was counted, and the defect density was determined. The result was about 1 × 10 ⁴ / cm ² .

[0284]

As described above, according to the present invention,
The heat treatment (pre-bake) conditions performed prior to the growth of the non-porous single crystal layer on the porous silicon layer can be determined using the haze value change rate r, which is easy to measure.

Further, as described above, according to the present invention, the heat treatment (pre-bake) is performed such that the change rate r of the haze value of the surface of the porous silicon before and after the heat treatment is within 3.5, more preferably within 2 The stacking fault density of the non-porous single-crystal silicon layer formed on the porous layer is reduced to 1000 by performing the heat treatment under the condition that the silicon etching amount in the heat treatment is suppressed to 2 nm or less, more preferably 1 nm or less.
/ Cm ² , and about 100 / cm ² . Further, by reducing the supply amount of the silicon raw material to the growth surface in the initial stage of the growth of the non-porous single crystal silicon, the defect reduction of the present invention can be further improved.

As a result, when the present invention is applied to the bonding method, it is possible to obtain an SOI layer having a uniform film thickness and extremely few crystal defects.

In other words, the present invention suppresses the amount of the natural oxide film on the porous surface formed in the epitaxial growth apparatus, thereby shortening the heat treatment time and temperature for removing the natural oxide film in a short time. It is. At the same time, the structural change in the surface of the porous layer and in the vicinity of the surface is suppressed, and before the deterioration of the surface structure of the porous layer becomes apparent, the formation of a non-porous single-crystal silicon film is started, whereby the crystal defects are reduced. An epitaxial silicon layer having a density of less than 1000 cm ² is obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for forming a non-porous single crystal layer on a porous silicon layer.

FIG. 2 is a diagram showing an example of a device with a load lock chamber.

FIG. 3 is a diagram illustrating a silicon etching amount in an epitaxial growth apparatus.

FIG. 4 is a diagram for explaining a relationship between a heat treatment temperature and a defect density by using a different epitaxial growth apparatus.

FIG. 5 is a diagram illustrating a change in haze value due to heat treatment of porous silicon.

FIG. 6 is a diagram illustrating a relationship between a change rate of a haze value and a defect density.

FIG. 7 is an SEM image illustrating a change in surface pores of a porous layer due to heat treatment.

FIG. 8 is a schematic diagram illustrating a change in surface pores of a porous layer due to heat treatment.

FIG. 9 is a diagram for explaining the relationship between the time and the defect density in the trace silicon material supply step.

FIG. 10 is a diagram illustrating a change in a haze value due to the supply of a small amount of silicon.

FIG. 11 is a diagram for explaining a difference in a relationship between a heat treatment temperature and a defect density due to a difference in pressure during heat treatment.

FIG. 12 is a diagram illustrating a relationship between a heat treatment time and a defect density.

FIG. 13 is an example of a system for determining conditions for appropriately performing pre-bake processing.

FIG. 14 is a schematic diagram illustrating a process of the present invention.

FIG. 15 is a schematic view illustrating a step of manufacturing an SOI substrate according to the present invention.

FIG. 16 is a conceptual diagram of an observation method of the foreign substance inspection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate having a porous silicon layer 2 Hole 3 Hole wall 4 Protective film 5 Protective coating 6 Non-porous single crystal layer 10 Base 11 Porous silicon layer 13 Incident light 14 Reflected light 15 Scattered light 16 Silicon wafer 17 Observation area

Claims (36)

[Claims] 1. A method for manufacturing a semiconductor substrate having a non-porous single-crystal layer on a porous silicon layer, wherein prior to the step of forming the non-porous single-crystal layer on the porous silicon layer, A heat treatment of the porous silicon layer in an atmosphere containing no source gas for the non-porous single crystal layer, and a rate of change of the haze value r (r = ( The semiconductor substrate is characterized in that the heat treatment conditions are determined so that the haze value of the surface of the porous silicon layer after the heat treatment / (the haze value of the surface of the porous silicon layer before the heat treatment) falls within a certain range. Production method. 2. The method according to claim 1, wherein the predetermined range is 1 ≦ r ≦ 3.5. 3. A semiconductor comprising a step of preparing a substrate having a porous silicon layer, a heat treatment step of heat treating the porous silicon layer, and a growth step of growing a non-porous single crystal layer on the porous silicon layer. In the method for manufacturing a substrate, the heat treatment is performed in an atmosphere not containing a source gas for the non-porous single crystal layer, and an etching amount of silicon by the heat treatment is 2 nm or less, and a haze value of a surface of the porous silicon layer is reduced. A method for manufacturing a semiconductor substrate, wherein the rate of change r (r = haze value after the heat treatment / haze value before the heat treatment) satisfies 1 ≦ r ≦ 3.5. 4. A step of preparing a first substrate having a porous silicon layer, a heat treatment step of heat treating the porous silicon layer, a growth step of growing a non-porous single crystal layer on the porous silicon layer, And a step of transferring the non-porous single crystal layer on the first substrate to a second substrate, wherein the heat treatment includes a source gas for the non-porous single crystal layer. In an atmosphere without heat, the amount of silicon etched by the heat treatment is 2 nm or less, and the rate of change of the haze value r (r = haze value after the heat treatment / haze value before the heat treatment) on the surface of the porous silicon layer is 1 A method for manufacturing a semiconductor substrate, which is performed so as to satisfy ≦ r ≦ 3.5. 5. The method according to claim 1, wherein the growth of the non-porous single crystal layer is 20 nm.
5. The method of manufacturing a semiconductor substrate according to claim 3, wherein the method is performed at a growth rate of not more than / min. 6. The growth of said non-porous single crystal layer is 10 nm.
5. The method of manufacturing a semiconductor substrate according to claim 3, wherein the method is performed at a growth rate of not more than / min. 7. The method according to claim 1, wherein the growth of the non-porous single crystal layer is 2 nm /
5. The method for manufacturing a semiconductor substrate according to claim 3, wherein the method is performed at a growth rate of not more than min. 8. The method for manufacturing a semiconductor substrate according to claim 1, wherein said rate of change r is 1 ≦ r ≦ 2. 9. The method according to claim 3, wherein the etching amount is 1 nm or less. 10. The method according to claim 1, wherein the non-porous single crystal is a non-porous single-crystal silicon layer. 11. The non-porous single-crystal layer is made of SiGe,
5. A semiconductor device comprising SiC or a compound semiconductor.
A method for manufacturing a semiconductor substrate as described above. 12. The step of transferring the non-porous single crystal layer onto the second substrate, wherein the first substrate and the second substrate are moved so that the non-porous single crystal layer is located inside. The method for manufacturing a semiconductor substrate according to claim 4, wherein the method is performed by a bonding step of bonding and a step of removing the porous silicon layer. 13. The step of transferring the non-porous single crystal layer onto the second substrate, wherein the first substrate and the second substrate are moved such that the non-porous single crystal layer is located inside. The method for manufacturing a semiconductor substrate according to claim 2, wherein the method is performed by a bonding step of bonding, and a step of separating at the porous silicon layer. 14. The method for manufacturing a semiconductor substrate according to claim 12, wherein the bonding step is a step of bonding the first substrate and the second substrate via an insulating layer. 15. The non-porous single crystal and a second insulating layer,
The method for manufacturing a semiconductor substrate according to claim 14, wherein the insulating layer is formed on at least one of the substrates. 16. The method according to claim 4, wherein the second substrate is a single crystal Si substrate. 17. The method according to claim 4, wherein the second substrate is a quartz wafer. 18. The heat treatment step includes a temperature raising step and a natural oxide film removing step.
The method is carried out at a temperature of 0 ° C or more and 1000 ° C or less.
3. The method for manufacturing a semiconductor substrate according to any one of items 3 and 4. 19. The heat treatment step includes a temperature raising step and a natural oxide film removing step, wherein the natural oxide film removing step includes:
5. The method for manufacturing a semiconductor substrate according to claim 1, wherein the processing time is within 200 seconds. 20. The porous silicon layer is subjected to the heat treatment step after forming a protective film on the pore wall.
3. The method for manufacturing a semiconductor substrate according to any one of items 3 and 4. 21. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a step of removing an oxide film formed on a surface of said porous single crystal silicon layer before said heat treatment step. 22. The semiconductor according to claim 1, wherein said growth step includes a growth step performed at a first growth rate and then performed at a second growth rate higher than said first growth rate. How to make a substrate. 23. The method according to claim 1, wherein the heat treatment step and the growth step are performed in a reaction vessel provided with a load lock chamber. 24. The method of manufacturing a semiconductor substrate according to claim 1, wherein a pressure in the heat treatment step is higher than a pressure in the growth step. 25. The method for manufacturing a semiconductor substrate according to claim 1, wherein said porous single-crystal silicon layer is obtained by anodizing at least a part of non-porous single-crystal silicon. 26. The method of manufacturing a semiconductor substrate according to claim 25, wherein the anodization is performed using a solution containing hydrofluoric acid, water, and alcohol. 27. The substrate having the porous silicon layer,
The depletion level is doped with impurities.
5. The method for forming a semiconductor substrate according to item 4. 28. The method according to claim 1, wherein the heat treatment step is performed in a non-oxidizing atmosphere containing hydrogen. 29. The method for manufacturing a semiconductor substrate according to claim 1, wherein the heat treatment step is performed in a reducing atmosphere containing hydrogen gas, a nitrogen gas atmosphere, or an inert gas atmosphere. 30. The method according to claim 1, wherein the heat treatment step is performed in an ultra-high vacuum. 31. The heat treatment step is performed at 870 ° C. or higher and 97
5. The method for producing a semiconductor substrate according to claim 1, wherein the method is performed at 0 ° C. or lower. 32. The method according to claim 1, wherein the etching amount is an etching amount in a temperature raising step for performing the heat treatment step at a set temperature. 33. The method according to claim 22, wherein the growing step performed at the first growth rate is performed until the haze value after the first growing step starts to decrease. 34. The method of measuring a haze value, wherein a laser beam is incident on a surface of a porous silicon layer and a scattering intensity is measured, wherein the wavelength of the laser beam is 500 nm or less. 3. The method for manufacturing a semiconductor substrate according to 1 or 2. 35. A semiconductor substrate obtained by the method according to claim 1. 36. A method for forming an integrated circuit, comprising forming an integrated circuit using the semiconductor substrate according to claim 35.