JP3748500B2 - Method for manufacturing semiconductor substrate - Google Patents

Description

を求め、１≦ｒ≦３．５であれば、同じプリベーク処理条件でエピタキシャル成長等の以降の工程を行う。
【００９８】
逆にｒ＞３．５であれば、プリベーク処理条件の変更を行う。そして、１≦ｒ≦３．５を満足するように条件を定める。
【００９９】
具体的には、温度や時間の変更、あるいはプリベーク処理を行う装置内の水分、酸素の低減を図る。
【０１００】
なお、投入されたすべてのシリコンウエハについて上記評価を行う必要はなく、数枚〜数百枚に１枚あるいは数枚を評価すれば十分である。特に、新しい装置において、プロセス条件を決定するための条件出し試験、あるいは装置の改造、修理、反応容器のクリーニング等を行ったあとの、テストの際に行うことが有効である。又、得られる半導体基板の品質に異常をきたした場合にも、本願の評価方法を行えば、原因の抽出を迅速に行うことができる。
【０１０１】
また、プリベーク処理後のヘイズ値ｄ₁ 自体で評価が可能である場合は、ｄ₀ の測定は省略することもできる。図１３（ｂ）は、決定された条件を基に、プリベーク処理を行い、所望の半導体基板を作製するための一連のシステムである。もちろん、エピタキシャル成長工程前に、ヘイズ値を測定して適切にプリベークが成されているか、確認することも好ましいものである。
【０１０２】
（実施態様例２）
図１４は本発明による半導体基板の形成方法を示す。
【０１０３】
図１４（ａ）に示すように、少なくとも表面側に多孔質シリコン層９０を有する基板１を用意する。２は孔、３は孔壁を示している。
【０１０４】
次に、必要に応じて図１４（ｂ）に示すように、前記多孔質単結晶シリコン層の孔壁３に薄い保護膜４を形成する（プリ酸化工程）。
【０１０５】
このプリ酸化のために多孔質シリコン層表面には酸化シリコン膜などの保護被膜５が形成されているので、これを低濃度のＨＦ水溶液に浸けて多孔質シリコン表面の保護膜を除去する（ＨＦディップ工程）。図１４（ｃ）にこの断面を模式的に示す。
【０１０６】
次に、多孔質単結晶シリコンが形成された基体をエピタキシャル成長装置に設置し、図１４の（ｄ）に示すように熱処理（プリベーク）を行った後、図１４Ｎの（ｅ）に示すように非多孔質単結晶層６を形成する。
【０１０７】
プリベーク時の条件は、多孔質シリコン層のエッチング量、即ち多孔質シリコン層の層厚（ｔ）の減少量が２ｎｍ以下、より好ましくは１ｎｍ以下となる条件（条件１）と、多孔質シリコン層のヘイズ値の変化率ｒが３．５以内、より好ましくは２．０以内になる条件（条件２）と、を満たすことが条件である。
【０１０８】
エッチング量ｔｅは、熱処理開始前の多孔質シリコン層の層厚をｔ₀ 、熱処理終了時の多孔質シリコン層の層厚をｔ₁ とした時に、ｔｅ＝ｔ₀ −ｔ₁ で表すことができる。ヘイズ値の変化率ｒは熱処理開始眼のヘイズ値をｄ₀ ，熱処理終了後のヘイズ値をｄ₁ とした時に、
【０１０９】
【外２】

で表わすことができる。
【０１１０】
そして、この熱処理時の雰囲気はシリコン系ガスを含まない雰囲気、より好ましくは水素を含む還元性雰囲気にするとよい。また、不活性ガス雰囲気、超高真空中であってもよい。
【０１１１】
以下のこの熱処理について述べる。
【０１１２】
▲１▼装置への設置
多孔質シリコン層を表面に形成した基体を残量酸素分、水分量が抑制された反応容器に設置する（図示せず）。本発明に用いられる熱処理としては、昇温工程、自然酸化膜除去工程の２工程に機能的に分けることもできる。なお、ここでいう自然酸化膜とは、ＨＦディップ工程以降に意図せずに多孔質シリコン層の表面に形成される酸化シリコン膜、およびＨＦディップ工程で除去しきれなかった酸化シリコン膜のことである。
【０１１３】
エッチング量の抑制は昇温工程、自然酸化膜除去工程中の反応容器内の残留酸素分、水分量を抑制することにより実現される。前記反応容器内の残留酸素分、水分量の抑制は、供給ガス系に含有する酸素分、水分を抑制するだけでなく、反応容器への基体の搬入・搬出をロードロック室を通して行うことにより、反応容器内面が大気と直接接触することを防止することが有効である。
【０１１４】
また、必要に応じてキャリアガスである水素の純化装置（Ｐｕｒｉｆｉｅｒ）を装置近くに設置することも有効である。また、配管系、容器の気密性を高くすることも望ましい。これらを制御すると、前記したように昇温工程、自然酸化膜の除去工程の２工程における多孔質シリコン層のエッチング量が少なくとも２ｎｍ以下、より好ましくは１ｎｍ以下に維持できる。しかし、エッチング量を抑制する方法は、上記した方法に必ずしも限定されない。
【０１１５】
▲２▼昇温工程
多孔質シリコン層を表面に形成した基体を反応容器に設置後、基体を昇温させる。反応容器が石英材等の光透過性材料で構成されている場合には、反応容器外からの赤外ランプ照射で加熱する。その他、ランプ加熱の他にも高周波による誘導加熱、抵抗加熱等がある。反応容器材は石英材やＳｉＣの他、ステンレス鋼などがある。昇温速度は速ければ速いほど残留水分、酸素分による酸化・エッチングが少なくて良い。好ましくは、１℃／ｓｅｃ以上、さらに好ましくは５℃／ｓｅｃ以上である。
【０１１６】
反応容器への基体の搬入をロードロック室を介さずに行う場合には、基体搬入後、十分にパージを行い、容器内に混入した酸素分、水分を除去してから基体を加熱して昇温させる。いずれにしても、超高真空又は非酸化性雰囲気で行うことが望まれる。
【０１１７】
▲３▼自然酸化膜除去工程
昇温工程に引き続き自然酸化膜除去工程を行う。つまり、水素中、又は水素を含む還元性雰囲気中あるいは、超高真空中での熱処理により、自然酸化膜を除去するこの時、多孔質シリコン層の表面のヘイズ値の変化率ｒが、３．５以内、より好ましくは２以内となるような条件で行う。なお、ｒは１以上である。
【０１１８】
上記条件を実現するためには、熱処理時の到達温度は、好ましくは８５０℃以上１０００℃以下、より好適には８７０℃以上９７０℃以下である。
【０１１９】
また、圧力は特に限定されるものではないが、好ましくは大気圧以下であり、７００Ｔｏｒｒ以下、更には１００Ｔｏｒｒ以下で行うことも好ましい。
【０１２０】
昇温工程を除く熱処理時間は、１００秒以内、より好ましくは６０秒以内、さらに好ましくは１０秒以内とし、その後は直ちに降温させるとよい。
【０１２１】
自然酸化膜は、ＳｉＯ₂ ＋Ｓｉ−＞２ＳｉＯ↑
という反応により気相中に脱離するため、自然酸化膜厚が厚いと多孔質シリコン層表面、表面近傍のシリコンがエッチングされることになる。
【０１２２】
自然酸化膜は、ＨＦディップ後の水洗中、水洗・乾燥後、エピタキシャル成長装置へ設置するまでの大気中、エピタキシャル成長装置への設置中、および、昇温工程中に形成される。特に昇温工程中に残留水分・酸素分が残留していると、温度の上昇とあいまって、シリコンを酸化して酸化シリコン膜を形成してしまう。結果、形成された酸化シリコンは近接するシリコンと反応して、シリコンをエッチングすることになってしまう。
【０１２３】
また、昇温中に形成される酸化シリコン膜が厚ければ厚いほど、形成された酸化シリコン膜を完全に除去するのに必要な熱処理時間が長くなる。かかる熱処理時間が長くなると、後に述べるように多孔質シリコン表面の構造変化が進行してしまうので、好ましくない。
【０１２４】
本発明では、エッチング量が少なくとも２ｎｍ以下、より好ましくは１ｎｍ以下でなければならないが、シリコンエッチング量が少ないということは、装置内でのシリコンの酸化の程度が小さいということに他ならない。
【０１２５】
この熱処理を継続すると、多孔質シリコンの表面では微小な荒れを平滑化し表面エネルギーを下げるべく表面原子のマイグレーションが生じ、表面の孔の大半が消失する。
【０１２６】
ロードロック式のＣＶＤエピタキシャル成長装置において、カーボンをＣＶＤ−ＳｉＣでコートしたサセプタを反応容器内で予め７５０度に昇温しておき、多孔質シリコンを形成したシリコンウエハをロードロックを介して設置する。その後、６００Ｔｏｒｒ、水素４３（１／ｍｉｎ）、の条件下で、摂氏１１００度まで１００度／分で昇温し、１１００度で２秒保持したのち、１００度／分で７５０度まで降温し、ロードロックを介し、ウエハを取り出した場合、多孔質表面孔は、熱処理前には平均直径がおよそ１０ｎｍの孔が１０¹¹／ｃｍ² だったのが、孔密度は１０⁶ ／ｃｍ² に減少すると共に、孔径は２０〜４０ｎｍに拡大していた。この条件で上に記した熱処理に引き続いて、シリコンソースガスを水素ガスに添加して単結晶シリコン層をエピタキシャル成長すれば、積層欠陥密度は１０⁴ ／ｃｍ² となった。一方、１１００度での熱処理を９５０度に代えて、保持時間は２秒で等しくした場合には、熱処理後の孔密度の減少はせいぜい１桁であった。また、孔径は殆ど増大していなかった。この熱処理条件の後、シリコンソースガスを水素ガスに添加して単結晶シリコン層をエピタキシャル成長すれば、積層欠陥密度は１０² ／ｃｍ² と１１００度の場合と比べて、１／１００に激減した。
【０１２７】
多孔質シリコンと非多孔質単結晶シリコン基板の間に作用する応力により、多孔質シリコンの表面の結晶格子は歪んでいるが、孔密度が減少した場合、この歪みが残留孔の周縁部に集中するため、残留孔部分に結晶欠陥が導入されやすくなると考えられる。
【０１２８】
本方法では、残留孔が自然酸化膜除去のため熱処理で減少する眼に多孔質シリコン表面へシリコンソースガスの供給を開始することにより、孔密度の減少による残留孔部分への歪みの集中を防ぎ、結晶欠陥の導入を抑制するものである。本方法は、シリコンのエッチング量が極めて小さい、昇温自然酸化膜除去によって初めて実現可能になった。
【０１２９】
特に本発明は、市販の異物検査装置等のレーザー光を基板表面に入射し、散乱光強度を観測する装置において、散乱光のＤＣレベルから導入するヘイズ値を管理する方法であり、非破壊で簡便にプロセス条件を制御し、結晶欠陥密度を１０００／ｃｍ² 以下、より好ましくは１００／ｃｍ² 以下に抑制する。
【０１３０】
自然酸化膜の除去は、シリコンのエッチング量が上で述べた範囲に抑制されるならば、ＨＦガスを用いるなど、他の方法を採用したり、援用してもよい。
【０１３１】
本発明における昇温工程、自然酸化膜除去工程は、シリコンエッチングが抑制されること、および多孔質表面に熱処理によって被膜が形成されなければよいのであって、特に限定されないが、超高真空中、ないしは、水素雰囲気中で行うことが望ましい。
【０１３２】
▲４▼ヘイズ値の測定
ヘイズ値の測定は、レーザー光等の平行光を基板表面に入射した際の散乱光強度を測定することによって得られる。市販のレーザー光を用いた異物検査装置を用いれば、簡便に測定可能である。レーザー光の波長は、例えばＡｒレーザーの４８８ｎｍなど、短波長が好適に用いられる。短波長ほど、光の多孔質層への侵入長が短いため、エピタキシャル成長層の結晶性に直接影響を及ぼす多孔質層の表面近傍の構造変化を鋭敏に検知できる。また、入射角は大きい方が、すなわち、基板表面に対して浅い角度で入射する方が多孔質層内への侵入長を短くし、表面近傍の構造変化に対して敏感な測定が可能となる。
【０１３３】
▲５▼エピタキシャル成長
熱処理工程（プリベーフ）を経た後には、ソースガスを供給し、多孔質の孔を塞ぎ、非多孔質単結晶膜を所望の膜厚まで形成する。こうして多孔質シリコン上に積層欠陥密度の低減した非多孔質単結晶層を形成することができる。
【０１３４】
非多孔質単結晶としては、ホモエピタキシャル成長させたシリコンであっても、ヘテロエピタキャシル成長させたＳｉＧｅ、ＳｉＣ、ＧａＡｓ、ＩｎＰ、ＡｌＧａＡｓ、ＧａＮ等であってもよい。
【０１３５】
（多孔質シリコン層）
本発明に用いられる多孔質Ｓｉは、１９６４年にＵｈｌｉｒらが発見して以来現在に至るまで研究されている多孔質シリコンと本質的には同一であり、陽極化成（Ａｎｏｄｉｚａｔｉｏｎ）などの方法により作製されるが、多孔質Ｓｉであるかぎり、基板の不純物、面方位、作成方法等に限定されない。
【０１３６】
陽極化成により多孔質シリコンを形成する場合、化成液はフッ酸を主たる成分とする水溶性である。陽極化成中には、電極やシリコン表面に気体が付着し、多孔質層を不均一にしやすいので、一般にはエタノールなどのアルコールを添加して接触角（Ｃｏｎｔａｃｔ Ａｎｇｌｅ）を大きくして、付着した気泡の脱離を加速し（Ｅｎｈａｎｃｅ）、化成が均一に起こるようにしている。もちろん、アルコールを添加せずとも多孔質は形成される。本発明による多孔質シリコンをＦＩＰＯＳ法に用いる場合には、多孔質は５６％付近が、貼り合わせ法に用いる場合には低い多孔質（概ね５０％以下、より好ましくは３０％以下）が好適である。しかし、これに限定されるものではない。
【０１３７】
多孔質シリコンは以上のようにエッチングにより形成されるため、その表面には多孔質の内部まで貫通する孔以外にも表面からＦｉｅｌｄ Ｅｍｉｓｓｉｏｎｔｙｐｅ Ｓｃａｎｎｉｎｇ Ｅｌｅｃｔｒｏｎ Ｍｉｃｒｏｓｃｏｐｅ（ＦＥＳＥＭ）で観察可能な程度に浅い凹凸といった方がより浅い孔も存在する。多孔質シリコンの多孔度（Ｐｒｏｓｉｔｙ（％））は低い方が多孔質上の積層欠陥密度は低減される。低多孔質度の多孔質シリコンは例えば、陽極化成時のＨＦ濃度を高める、電流密度を下げる、温度を上げるなどの方法によって、実現される。
【０１３８】
また、多孔質単結晶シリコン層は、Ｓｉ基板の主表面層のみを多孔質化しても、Ｓｉ基板の全部を多孔質化してもよい。
【０１３９】
なお、多孔質層の形成は、非多孔質単結晶シリコンに、Ｈｅ、Ｎｅ、Ａｒのような希ガスイオン又は水素イオンを打込んで、必要に応じて熱処理することにより、微小気泡（マイクロバブル）を生成させ、多孔質化することもできる。こと点に関しては特開平５−２１１１２８号公報に開示がある。
【０１４０】
（プリ酸化）
本発明においては、必要に応じて多孔質シリコン層の孔壁に保護膜を形成してもよい。
【０１４１】
多孔質シリコンの隣接する孔の間の壁の厚みは数ｎｍ〜数十ｎｍと非常に薄いため、エピタキシャル成長時、エピタキシャル成長層の熱酸化時、あるいは、貼り合わせ後の熱処理によっては多孔質層中の隣接する孔が凝集・粗大化し、さらには分断してしまうことがある。この多孔質層の孔の凝集（ａｇｇｌｏｍａｒａｔｉｏｎ）・粗大化（Ｃｏａｒｓｅｎｉｎｇ）現象は、多孔質シリコンの選択エッチング速度の低下と選択比の劣化を招いてしまうことがある。ＦＩＰＯＳにおいては孔壁厚みの増加と孔の分断のために多孔質層の酸化の進行が妨げられ、多孔質層を完全に酸化することが困難になってしまう。そこで、多孔質層形成後に熱酸化等の方法により、あらかじめ孔壁に薄い保護膜を形成して、孔の凝集・粗大化を抑制することができる。保護膜の形成に際しては、特に酸化による場合は孔壁内部に単結晶シリコンの領域を残すことが必須である。従って、膜厚は数ｎｍあれば十分である。
【０１４２】
一方で、貼り合わせ法によりＳＯＩ基板を作製する場合に、貼り合わせ後の熱処理などの後工程の低温化が十分になされ、多孔質の構造変化が抑制されれば、この工程は省略することも可能である。
【０１４３】
（ＨＦディップ）
上記プリ酸化された多孔質シリコン層は、ＨＦディップ処理することもできる。
【０１４４】
ＨＦディップに関して、佐藤ら（Ｎ．Ｓａｔｏ，Ｋ．Ｓａｋａｇｕｃｈｉ，Ｋ．ｙａｍａｇａｔａ，Ｙ．Ｆｕｊｉｙａｍａ，ａｎｄ Ｔ．Ｙｏｎｅｈａｒａ，Ｐｒｏｃ．ｏｆ ｔｈｅ Ｓｅｖｅｎｔｈ Ｉｎｔ．Ｓｙｍｐ．ｏｎ Ｓｉｌｉｃｏｎ Ｍａｔｅｒ．Ｓｃｉ．ａｎｄ Ｔｅｃｈ．，Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｓｉｌｉｃｏｎ，（Ｐｅｎｎｉｎｇｔｏｎ，ｔｈｅ Ｅｌｅｃｔｒｏｃｈｅｍ．Ｓｏｃ．Ｉｎｃ．，１９９４），ｐ．４４３）によればＨＦディップの時間を長くすることにより、積層欠陥を１０³ ／ｃｍ² 程度まで低減できると報告しているが、既述の通り長時間ＨＦディップをした場合、貼り合わせ後のアニール温度によっては多孔質層の構造粗大化が進行し、多孔質シリコンのエッチングに際し、エッチングされない部分（エッチング残渣）が生じることがあるため、ＨＦディップ時間は適当な範囲に制御する必要することが望ましい。
【０１４５】
ＨＦディップの後、水洗・乾燥を行い、多孔質の孔中の残留ＨＦ濃度を低下させることができる。
【０１４６】
（微量の原料供給による孔の閉塞）
なお、本発明においては、多孔質の孔の閉塞させる成長初期過程にて、ＳｉＨ₂ Ｃｌ₂ ，ＳｉＨ₄ ，ＳｉＨＣｌ₃ ，ＳｉＣｌ₄ や、Ｓｉ₂ Ｈ₆ 等のシリコン系ソースガスを用いて、２０ｎｍ．／ｍｉｎ以下、より好ましくは１０ｎｍ．／ｍｉｎ．以下、さらに好ましくは２ｎｍ／ｍｉｎ．以下の成長速度になるようソースガスの流量を設定するとよい。なお、常温・常圧で気体であるシランが供給量の制御性の点からより好ましい。これにより結晶欠陥がさらに低減される。ＭＢＥ法のようにＳｉを固体ソースから供給し、基板温度が８００度以下と低い場合には成長速度は、０．１ｎｍ／ｍｉｎ以下であることが望ましい。微量の原料供給工程（「プリインジェクション」と呼ぶこともある）により、孔の閉塞が完了した後は、成長速度は特に制約されない。
【０１４７】
通常のバルクシリコン上の成長と同条件であっても構わない。あるいは、上記した微量の原料供給工程と同じ成長速度で引き続き成長をつづけてもよいし、ガス種等を変更しても何等本発明の要件を阻害するものではない。また、微量の原料供給工程とは連続した工程であっても、一旦、原料の供給を中断したのち、改めて所望の原料を供給して成長としても構わない。なお、Ｎ．Ｓａｔｏ ｅｔ．ａｌ．Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．３５（１９９６）９７３．では、微量の成長初期のＳｉＨ₂ Ｃｌ₂ の供給量を減じることにより、従来法に比して積層欠陥密度が低減されることが報告された。しかしながら、かかる方法では積層欠陥密度は、エピ前プリベーク温度を高くすることで低減される傾向に変わりはなく、上記したような多孔質層の構造粗大化に伴うエッチング残さが発生することがあった。本発明では、成長前の熱処理を従来よりも低温の９５０℃程度で行うことができるので、多孔質の構造の粗大化は生じにくい。
【０１４８】
本発明の形態によれば、シリコンのエッチング量の少ない装置に多孔質シリコン層を有する基体を設置して、成長前の熱処理時間を制御することにより、従来法のように高温の熱処理を避けることもできる。こうすれば、結晶欠陥密度を低減でき、多孔質の構造粗大化と孔の分断抑止し得る。
【０１４９】
また、成長温度・圧力・ガス流量等は上記成長初期工程とは独立に制御できるので、処理温度を低温にして、多孔質シリコンの構造粗大化、あるいは、多孔質シリコンからのボロン、燐等の不純物のオートドーピング、固相拡散を抑制したり、成長温度を上げ、シリコンソースガスの流量を増やすことで成長速度を高めて、厚い非多孔質単結晶シリコン膜を短時間で形成してもよい。
【０１５０】
また、成長する非多孔質単結晶層は、前述したとおりシリコンに限られるものではなく、ＳｉＧｅ，ＳｉＣ等のＩＶ族系のヘテロエピタキシー材料、あるいは、ＧａＡｓに代表される化合物半導体であっても構わない。又、前記微量原料供給工程ではシリコン系ガスを用い、その後は別のガスを用いてヘテロエピタキシャル成長させても構わない。
【０１５１】
なお、多孔質層表面の孔の封止工程（プリベーク、プリインジェクション）後、所望の膜の成長前に、プリベーク、プリインジェクションよりも高い温度で、かつ半導体膜の原料ガスを含まない雰囲気（たとえば水素を含む還元性雰囲気）で熱処理することも好ましい。当該熱処理を中間ベーク（ｉｎｔｅｒ ｂａｋｉｎｇ）という。
【０１５２】
（実施態様例３）
多孔質単結晶シリコン層上に低欠陥密度の非多孔質単結晶シリコン層を有する半導体基板を応用した例について説明する。
【０１５３】
単結晶Ｓｉ基板の少なくとも一表面側の部分を多孔質化し多孔質シリコン層１１を有する基体１０を作製する（図１５（ａ））。
【０１５４】
実施態様例２に示したのと同様の方法、すなわちシリコンのエッチング量が２ｎｍ以下で、（より好ましくは１ｎｍ以下）、かつ多孔質シリコンのヘイズ値の変化率ｒが、３．５以内、（より好ましくは、２以内）となる熱処理（プリベーク）を行う（図１５（ｂ））。その後で該多孔質単結晶シリコン層上に非多孔質単結晶層１２を形成する（図１５（ｃ））。
【０１５５】
なお、熱処理に先だって、前述のプリ酸化、ＨＦディップを行ってもよい。更には、熱処理後に微量の原料供給（プリインジェクション）による孔の閉塞を行うことも好ましい。
【０１５６】
次に貼り合わせ法によりＳＯＩ基板を作製するが、まず非多孔質単結晶シリコン、第２の基体の少なくともどちらか一方の主面に絶縁層を形成し、その後、両主面を貼り合わせ、多層構造体を形成する（図１５（ｄ））。必要に応じて貼り合わせ強度を高めるための熱処理を行った後、多孔質シリコンの選択エッチング等による除去の工程（図１５（ｅ））を経て、多孔質シリコン上のエピタキシャル成長層を第２の基板上に移設すれば、ＳＯＩ構造を得ることができる。
【０１５７】
なお、貼り合わせ強度が、後の工程に耐えるのに十分であれば、後工程に進む。研削等の機械的方法、エッチング等の化学的方法などにより、多孔質層が形成された基板の裏面側を除去して多孔質層を表出する。あるいは、多孔質層を境に、多層構造体から基体１０のうちの多孔質化されていない１５の部分を剥離（分離）することによって、多孔質層を表出させてもよい。剥離は、くさび等を端面から挿入することや、ウォータージェットのように流体を噴きつけることにより、機械的に剥離させてもよいし、超音波や、熱応力等を利用してもよい。予め多孔質層中に機械的強度の弱い高多孔度層を部分的に形成しておくことにより、分離しやすくしておくとよい。例えば、多孔質層１１の構成を、非多孔質単結晶層１２側から、第１の多孔質層（１０％〜３０％の多孔度）、その下に、第２の多孔質層（３０％〜７０％の多孔度）とするものである。
【０１５８】
（多孔質の選択エッチング）
非多孔質単結晶層１２上に残留した多孔質層は、選択エッチングにより除去する。選択エッチング液はＨＦ、Ｈ₂ Ｏ₂ 、Ｈ₂ Ｏ₂ の混合液が好適に用いられる。反応中に生成される気泡を除去するために、混合液中にエチルアルコール、イソプロピルアルコールや界面活性剤を添加してもよい。
【０１５９】
本方法では、多孔質層の構造変化・粗大化、孔の分断が抑制されているので、選択エッチングにおいて選択性の劣化が少ない。
【０１６０】
なお、多孔質シリコン上に形成した非多孔質単結晶シリコン層を貼り合わせる第２の基体は特に限定されない。シリコンウエハ、熱酸化シリコン膜を形成したシリコンウエハ、石英ウエハなどの透明基板、サファイアウエハなど、前記非多孔質単結晶シリコン表面、ないしは、その上に形成した膜の表面と密着できる平滑さを有していればよい。絶縁性基体を貼り合わせる場合には、絶縁層１４は省ける。
【０１６１】
また、非多孔質単結晶シリコン層はそのまま第２の基体を貼り合わせても貼り合わせる前に膜を形成してもよい。形成する膜は、酸化シリコン、窒化シリコンの他、ＳｉＧｅ，ＳｉＣ，ＩＩＩ−Ｖ化合物、ＩＩ−ＶＩ化合物などの単結晶膜を形成したものであってもよいし、これらの複数の膜を積層したものであってもよい。
【０１６２】
貼り合わせ前には貼り合わせ面を清浄に洗浄することが好適である。洗浄は通常の半導体プロセスで用いられる先行工程を採用してもよい。また、貼り合わせ前に窒素プラズマ等を照射すると接着強度を高めることができる。
【０１６３】
貼り合わせ後には、熱処理を行って貼り合わせ強度を高めることが望ましい。
【０１６４】
（水素アニール）
多孔質シリコンの除去後の表面多孔質シリコンの孔と側壁の周期を反映した凹凸が存在する。なぜなら、この表面は非多孔質単結晶シリコンと多孔質シリコンの界面に相当するが、そもそもどちらも単結晶シリコンであり、孔があるかどうかだけの差であるためである。この表面凹凸は研磨等によっても除去できるが、水素雰囲気中で熱処理を行うと、非多孔質単結晶シリコンの膜厚を殆ど減じることなく凹凸を除去できる。水素アニールは、大気圧下、高圧下、微減圧下いずれでも行うことができる。
【０１６５】
また、アニール温度は、８００℃からシリコンの融点以下、より好ましくは、９００℃から１３５０℃以下である。
【０１６６】
（ボロン濃度制御）
一方、多孔質シリコン上のエピタキシャル層の結晶性は一般にＰ⁺ Ｓｉ（^- ０．０１Ω・ｃｍ ｂｏｒｏｎ ｄｏｐｅｄ）を多孔質化した方が、Ｐ^- Ｓｉ（^- ０．０１Ω・ｃｍ ｂｏｒｏｎ ｄｏｐｅｄ）を化成した場合と比べはるかに良好であるが、高濃度Ｂｏｒｏｎがエピタキシャル成長時にオートドーピング、あるいは、固相拡散してエピタキシャルシリコン層に拡散してしまう場合がある。エピタキシャルシリコン層に拡散したボロンは多孔質シリコン除去後にも残留してしまい、ＳＯＩにおける活性層の不純物濃度の抑制に支障を来す場合がある。これを解決するために佐藤ら（ｎ．Ｓａｔｏ，ａｎｄ Ｔ．Ｙｏｎｅｈａｒａ，Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．６５（１９９４）ｐ．１９２４）でＳＯＩ構造が完成した基板を水素中でアニールすることで、ボロンの拡散速度の低いＳＯＩ層表面の自然酸化膜を除去し、ＳＯＩ層中のボロンを外部に拡散することで、低濃度化を実現している。しかしながら、エピタキシャルシリコン層への過度のボロン拡散は、埋め込み酸化膜中へのボロン取り込みを招き、水素アニールの長時間化を招き、プロセスコストの増大、あるいは、埋め込み酸化膜中のボロン濃度の制御性の悪化などの問題が生じることがあった。この課題の解決には、エピタキシャルシリコン層の形成条件を低温化するなどしてボロンの拡散を抑制することが有効である。本発明によれば、エピタキシャルシリコン層の形成は、孔の閉塞とは独立に条件を設定できるので、適切な条件を設定可能である。
【０１６７】
（ＦＩＰＯＳ法）
マタハ、貼り合わせ工程を行わずＦＩＰＯＳ法により、エピタキシャル成長層を部分的に除去した後、酸化処理により多孔質シリコンを選択的に酸化して、ＳＯＩ構造を形成しても良い。本方法では、多孔質層の構造変化・粗大化、孔の分断が抑制されているので、選択酸化においても選択性の劣化が少ない。
【０１６８】
（ヘテロエピタキシー）
あるいは、ＧａＡｓ等の化合物半導体、ＳｉＣ，ＳｉＧｅ等のＩＶ族系のヘテロエピを実施しても良い。ヘテロエピタキシーにおいては、多孔質シリコンが応力の緩衝材料として作用し、格子不整合による応力を緩和することができる上に、非多孔質単結晶シリコン層の結晶欠陥密度が低減できているので、ヘテロエピタキシャル成長層の欠陥密度も低減される。本方法では、多孔質層の構造変化・粗大化、孔の分断が抑制されているので、応力の緩衝効果の劣化が少ない。
【０１６９】
（その他の応用）
多孔質シリコンにはゲッタリング作用があるため、上記したようなＳＯＩ構造を形成せずとも、本発明により作製した非多孔質単結晶シリコン層にＭＯＳトランジスタ、バイポーラトランジスタ等を直接形成すれば、工程中の金属汚染等の不純物汚染耐性の高い基板となる。
【０１７０】
本方法では、従来法に比べ、熱処理温度、特に孔の封止前の熱処理温度を低温化できるため、多孔質層中の孔の凝集・拡大、分断等を抑制できるため、貼り合わせ法での後の工程での多孔質層の選択エッチングでの選択性を劣化させない。すなわち、多孔質層除去において、残さを発生させないで、非多孔質単結晶シリコン層の結晶性を向上できる。また、ＦＩＰＯＳ法においては、多孔質層の選択酸化の酸化速度を劣化せしめない。
【０１７１】
以下、本発明の具体的な実施例について説明する。
【０１７２】
（実施例１−９５０℃，６００Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｓ，１２０ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−２μｍ）
１）ｐ型不純物としてボロンを添加し、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．００５Ω・ｃｍにしたＣＺ６インチ（１００）ｐ⁺ シリコンウエハを用意した。
【０１７３】
２）４９％ＨＦとエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウエハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、通電しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前期シリコンウエハを陽極化成し（Ａｎｏｄｉｚｅ）、表面に１２μｍ厚の多孔質シリコンを形成した。
【０１７４】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないためので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０１７５】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスとして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０１７６】
５）その後プリベーク工程として、１１００℃、１２０秒間の熱処理を行った。
【０１７７】
プリベーク直前のヘイズ値は、９．１ｐｐｍであり、プリベーク後のヘイズ値は、３４．５ｐｐｍであった。すなわち、ｒ＝３．８（＞３．５）であった。
【０１７８】
そこで、ヘイズ値の変化率ｒが、１≦ｒ≦３．５を満たすよう様々に熱処理条件を変えて行ったところ、９５０℃で１２０秒間の熱処理を行った場合、ヘイズ値の変化率ｒは、２．８（＜３．５）となることが分った。
【０１７９】
ｒ＝２．８となる条件で、プリベークを行った後、同じ反応容器内において、圧力６００Ｔｏｒｒで、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加して、２００秒処理し、ＳｉＨ₄ の添加は終了し、その後、圧力を８０Ｔｏｒｒに温度を９００℃に下げて、今度はＳｉＨ₂ Ｃｌ₂ を濃度０．５ｍｏｌ％となるように添加して、非多孔質単結晶シリコン膜を２μｍ形成した。そしてウエハを欠陥顕在化エッチングして、非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化した後、ノマルスキー微分干渉顕微鏡で観察した。観察された欠陥は積層欠陥が９９％以上であった。積層欠陥の密度は、１６０個／ｃｍ² であった。
【０１８０】
一方、ヘイズ値の変化率ｒ＝３．８の場合は同様の条件でエピタキシャル成長すると、積層欠陥密度は、１．５×１０⁴ ／ｃｍ² となっていることが分かった。以上のことより、ヘイズ値が一定の範囲内になる条件でプリベークを行うことで、非常に積層欠陥密度の低い単結晶Ｓｉ層の形成が可能であることが確認できた。
【０１８１】
なお、積層欠陥の観察は、欠陥顕在化エッチングして顕微鏡で観察した。具体的には、エッチング液として、Ｓｅｃｃｏエッチング法におけるＫ₂ Ｃｒ₂ Ｏ₇（０．１５Ｍ）と４９％−ＨＦ（２：１）の混合水溶液を、エッチング速度を下げるために、純水で希釈したものを用い、ウエハ表面の非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化させた後、ノマルスキー微分干渉顕微鏡で観察し積層欠陥密度を求めた。
【０１８２】
（実施例２−９５０℃，６００Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｓ，１２０ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−２μｍ）
１）ｐ型不純物としてボロンを添加し、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．００５Ω・ｃｍにしたＣＺ６インチ（１００）ｐ⁺ シリコンウエハを用意した。
【０１８３】
２）４９％ＨＦ水溶液とエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウエハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、導通しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前記シリコンウエハを陽極化成し、表面に１２μｍ厚の多孔質シリコンを形成した。
【０１８４】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。
【０１８５】
この酸化処理は、概ね５０Å以下の酸化膜しか形成しないので、酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０１８６】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスとして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０１８７】
５）ウエハをウエハキャリアに入れてセットするロードロック室と、ウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に、前記ウエハをウエハキャリアに入れて設置した。
【０１８８】
ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ ガスを流して、８０Ｔｏｒｒにした。移載チャンバーは、予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０１８９】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０１９０】
６）プロセスチャンバー内の圧力を６００Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、９５０℃で２秒保持した後、温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは９５０℃で１２０秒保持し、これ以外は、前述のウエハと同じ処理をしてロードロック室に戻した。
【０１９１】
７）ロードロック室を大気開放してウエハを取り出し、異物検査装置で多孔質層表面のヘイズを観察したところ、２秒処理のウエハ上の多孔質の平均ヘイズ値は、１１．９ｐｐｍであり、１２０秒処理の多孔質のヘイズ値は、２５．７で、エピタキシャル成長装置に設置する前のサンプルのヘイズ値９．１ｐｐｍのそれぞれ約１．３、２．８倍であった。すなわち、ｒ＝１．３，２．８であった。
【０１９２】
８）また、予め用意しておいたＳＯＩ基板をＨＦディップし、水洗して乾燥させたのち、ＳＯＩ層の膜厚を光式干渉膜厚計により測定し、５）、６）の処理を施し、ロードロックより取り出した。再びＳＯＩ層の膜厚を測定したところ、ＳＯＩ層の膜厚減少量は、いずれも１ｎｍ未満であった。
【０１９３】
９）４）の処理が終了したウエハを、５）に記載した方法により、エピタキシャル成長装置のプロセスチャンバーに移載した。
【０１９４】
１０）プロセスチャンバーの圧力を６００Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、熱処理（プリベーク処理）として９５０℃で２秒保持した後、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加し、２００秒処理をし、ＳｉＨ₄ の添加は終了し、その後、圧力を８０Ｔｏｒｒに温度を９００℃に下げて、今度はＳｉＨ₂ Ｃｌ₂ を濃度０．５ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を２μｍ形成し、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは９５０℃水素雰囲気中でのプリベーク処理時間を１２０秒とし、これ以外は同じ処理をしてロードロック室に戻した。なお、濃度２８ｐｐｍのＳｉＨ₄ ガスを添加した場合、成長速度は、３．３ｎｍ／ｍｉｎである。
【０１９５】
１１）１０）の処理が終了したウエハを欠陥顕在化エッチングして、非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化した後、ノマルスキー微分干渉顕微鏡で観察した。観察された欠陥は積層欠陥が９９％以上であった。積層欠陥の密度は、プリベーク２秒の場合、８４個／ｃｍ² 、プリベーク６０秒の場合、１６０個／ｃｍ² で、プリベーク１１００℃１２０秒の場合の１．５×１０⁴ ／ｃｍ² に比べ、激減した。特に９５０℃２秒でプリベークでは、１００個／ｃｍ² を下回る積層欠陥密度が得られた。
【０１９６】
（実施例３−９５０℃，６００Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｅ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−０．３２μｍ ＥＬＴＲＡＮ）
１）ｐ型不純物としてボロンを添加し、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．０１Ω・ｃｍにしたＣＺ８インチ（１００）ｐ⁺ シリコンウエハを用意した。
【０１９７】
２）４９％ＨＦ水溶液とエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、導通しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前記シリコンウエハを陽極化成し（Ａｎｏｄｉｚｅ）、表面に１２μｍ厚の多孔質シリコンを複数枚形成した。
【０１９８】
３）つづいて、多孔質シリコン層を形成したウエハに、４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないので、酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０１９９】
４）１．２５％に希釈したＨＦ水溶液に、前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２００】
５）ウエハをウエハキャリアに入れてセットするロードロック室とウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に前記ウエハをウエハキャリアに入れて設置した。ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。移載チャンバーは予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２０１】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２０２】
６）サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、プリベーク処理として９５０℃で２秒保持した、このときの条件は、シリコンのエッチング量１ｎｍ未満であり、ヘイズ変化率ｒ＝１．３であった。
【０２０３】
つぎに、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ Ｃｌ₂ を添加して、２００秒処理をし、ＳｉＨ₄ の添加は終了し、その後、温度を９００℃に下げて、今度はＳｉＨ₄ Ｃｌ₂ を濃度０．５ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を０．３２μｍ形成し、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。形成された非多孔質単結晶シリコン層の膜厚は平均０．３２μｍ、最大値−最小値＝８ｎｍであった。
【０２０４】
７）非多孔質単結晶シリコンをエピタキシャル成長したウエハを縦形炉に設置して、酸素と水素を燃焼して形成された水蒸気と残留酸素の混合気中、１０００℃で熱処理により前記非多孔質単結晶シリコンの表面を酸化して、２０８ｎｍの酸化シリコン膜を形成した。
【０２０５】
８）上記ウエハと第２のシリコンウエハをシリコン半導体プロセスの洗浄ラインで清浄に洗浄したのち、両ウエハの第１の主面同士を静かに重ね合わせ、中央を押圧したところ、両ウエハは一体化した。
【０２０６】
９）続いて、一体化したウエハ組を縦形炉に設置して、酸素雰囲気中１１００℃で１時間熱処理した。
【０２０７】
１０）多孔質シリコンを形成したウエハの裏面側をグラインダーにより：研削し、多孔質シリコンをウエハ全面に渡って露出させた。
【０２０８】
１１）露出した多孔質シリコン層をＨＦと過酸化水素水の混合溶液に漬けたところ、およそ２時間で多孔質シリコンはすべて除去され、ウエハ全面で、非多孔質単結晶シリコン層と熱酸化シリコン膜による干渉色が観察された。
【０２０９】
１２）１１）の処理が終了したウエハをシリコン半導体デバイスプロセスで一般的に用いる洗浄ラインで洗浄した後、縦形水素アニール炉に設置して、水素１００％雰囲気中で１１００℃４時間の熱処理を行った。水素ガスは装置とおよそ７ｍの内面研磨ステンレス配管で接続されたパラジウム合金を用いた市販の水素精製装置で純化されている。
【０２１０】
１３）こうして、第２のシリコンウエハ上に２００ｎｍの酸化シリコン層と２００ｎｍの単結晶シリコン層が積層されたＳＯＩ構造のウエハが作製された。
【０２１１】
単結晶シリコン層の膜厚は平均２０１ｎｍ、最大値−最小値＝８ｎｍであった。
【０２１２】
１４）のウエハを欠陥顕在化エッチングにより単結晶シリコン層を１３０ｎｍ除去したのち、４９％ＨＦに３分漬けた。この結果、欠陥顕在化エッチングによりエッチングされた単結晶シリコン層に残留する結晶欠陥の部分から埋め込み酸化膜がＨＦによりエッチングされ、ノマルスキー微分干渉顕微鏡で容易に欠陥密度を測定できる。観察された欠陥の密度は、６４個／ｃｍ² であった。水素アニール処理により、非多孔質単結晶シリコン層に導入された積層欠陥が減少していた。欠陥密度１００個／ｃｍ² を下回り、かつ、膜厚の均一な薄膜ＳＯＩ層が得られた。
【０２１３】
（実施例４−９５０℃，６００Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｓ，１２０ｓ），Ｎｏ Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−２μｍ）
１）ｐ型不純物としてボロンを添加し、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．００５Ω・ｃｍにした、６インチ（１００）ｐ⁺ シリコンウエハ（ＣＺウエハ）を用意した。
【０２１４】
２）４９％ＨＦとエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウエハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、導通しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前記シリコンウエハを陽極化成し（Ａｎｏｄｉｚｅ）、表面に１２μｍ厚の多孔質シリコンを形成した。
【０２１５】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないためので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０２１６】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２１７】
５）ウエハをウエハキャリアに入れてセットするロードロック室とウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に前記ウエハをウエハキャリアに入れて設置した。
【０２１８】
ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。
【０２１９】
移載チャンバーは予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２２０】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２２１】
６）プロセスチャンバーの圧力を６００Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、９５０℃で２秒保持した後、温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは９５０℃で６０秒保持し、これ以外は同じ処理をしてロードロック室に戻した。
【０２２２】
７）ロードロック室を大気開放してウエハを取り出し、異物検査装置で多孔質層表面のヘイズ値を測定したところ、２秒処理のウエハ上の多孔質表面の平均ヘイズ値は、１１．９であり、６０秒処理の多孔質のヘイズ値は、１６．３で、エピタキシャル成長装置に設置する前のサンプルのヘイズ値９．１のそれぞれ約１．３、１．８倍であった。
【０２２３】
８）また、予め用意しておいたＳＯＩ基板をＨＦディップし、水洗いして乾燥させたのち、ＳＯＩ層の膜厚を光干渉式膜厚計により測定し、５）、６）の処理を施し、ロードロックより取り出した。再びＳＯＩ層の膜厚を測定したところ、ＳＯＩ層の膜厚減少量は、いずれも１ｎｍ未満であった。
【０２２４】
９）４）の処理が終了したウエハを５）により、エピタキシャル成長装置のプロセスチャンバーに移載した。
【０２２５】
１０）プロセスチャンバーの圧力を６００Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、プリベーク処理として９５０℃で２秒保持した後、温度を９００℃に下げて圧力を８０Ｔｏｒｒにし、ＳｉＨ₂ Ｃｌ₂ を濃度０．５ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を２μｍ形成し、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは９５０℃水素雰囲気中でのプリベーク処理時間を６０秒とし、これ以外は同じ処理をしてロードロック室に戻した。
【０２２６】
１１）１０）の処理が終了したウエハを欠陥顕在化エッチングして、非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化した後、ノマルスキー微分干渉顕微鏡で観察した。観察された欠陥は積層欠陥が９９％以上であった。積層欠陥の密度は、プリベーク２秒の場合、１７０個／ｃｍ² 、プリベーク６０秒の場合、２７０個／ｃｍ² で、プリベーク１１００℃１２０秒の場合の１．５×１０⁴ ／ｃｍ² に比べ、激減した。
【０２２７】
（実施例５−９００℃，４５０Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｓ，１２０ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−２μｍ）
１）ｐ型不純物としてボロンを添加して、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．００５Ω・ｃｍにした６インチ（１００）ｐ⁺ シリコンウエハ（ＣＺウエハ）を用意した。
【０２２８】
２）４９％ＨＦとエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウエハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、導通しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前記シリコンウエハを陽極化成し（Ａｎｏｄｉｚｅ）、表面に１２μｍ厚の多孔質シリコンを形成した。
【０２２９】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないためので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０２３０】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２３１】
５）ウエハをウエハキャリアに入れてセットするロードロック室とウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に前記ウエハをウエハキャリアに入れて設置した。ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。移載チャンバーは予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２３２】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２３３】
６）プロセスチャンバーの圧力を４５０Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、９００℃で２秒保持した後、温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは９００℃で１２０秒保持し、これ以外は同じ処理をしてロードロック室に戻した。
【０２３４】
７）ロードロック室を大気開放してウエハを取り出し、異物検査装置で多孔質層表面のヘイズ値を測定したところ、２秒処理のウエハ上の多孔質の平均ヘイズ値は、１２．１であり、６０秒処理の多孔質の平均ヘイズ値は、１４．３で、エピタキシャル成長装置に設置する前のサンプルの平均ヘイズ値９．２のそれぞれ約１．３、１．６倍であった。
【０２３５】
８）また、予め用意しておいたＳＯＩ基板をＨＦディップし、水洗いして乾燥させたのち、ＳＯＩ層の膜厚を光干渉式膜厚計により測定し、５）、６）の処理を施し、ロードロックより取り出した。再びＳＯＩ層の膜厚を測定したところ、ＳＯＩ層の膜厚減少量は、いずれも１ｎｍ未満であった。
【０２３６】
９）４）の処理が終了したウエハを５）により、エピタキシャル成長装置のプロセスチャンバーに移載した。
【０２３７】
１０）プロセスチャンバーの圧力を４５０Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、プリベーク処理として９００℃で２秒保持した後、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加して、２００秒処理をし、ＳｉＨ₄ の添加は終了し、その後、圧力を８０Ｔｏｒｒに温度を９００℃に下げて、今度はＳｉＨ₂ Ｃｌ₂ を濃度０．７ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を２μｍ形成し、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハ９００℃水素雰囲気中でのプリベーク処理時間を６０秒とし、これ以外は同じ処理をしてロードロック室に戻した。
【０２３８】
１１）１０）の処理が終了したウエハを欠陥顕在化エッチングして、非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化した後、ノマルスキー微分干渉顕微鏡で観察した。観察された欠陥は積層欠陥が９９％以上であった。積層欠陥の密度は、プリベーク２秒の場合、３５０個／ｃｍ² 、プリベーク６０秒の場合、４００個／ｃｍ² で、プリベーク１１００℃１２０秒の場合の１．５×１０⁴ ／ｃｍ² に比べ、激減し、１０００個／ｃｍ² 未満の欠陥密度が実現された。
【０２３９】
（実施例６−８７０℃，８０Ｔｏｒｒ Ｐｒｅｂａｋｅ（５ｓ，６０ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−２μｍ）
１）ｐ型不純物としてボロンを添加して、比抵抗０．０１５Ω・ｃｍ⁺ ／^- ０．００５Ω・ｃｍにした６インチ（１００）ｐ⁺ シリコンウエハ（ＣＺウエハ）を用意した。
【０２４０】
２）４９％ＨＦとエチルアルコールを２：１の比で混合した溶液中で前記シリコンウエハを陽極に、６インチ径の白金板を陰極としてシリコンウエハと向かい合うように設置した。前記シリコンウエハの裏面側は同じ溶液を介して、別のｐ⁺ Ｓｉウエハの表面側と対向させ、もっとも端のウエハは６インチ径の白金板を対向させた。ウエハとウエハの間の溶液はウエハで隔てられ、導通しないように配置した。前記シリコンウエハと白金の間に電流密度１０ｍＡ／ｃｍ² で１２分間電流を流して前記シリコンウエハを陽極化成し（Ａｎｏｄｉｚｅ）、表面に１２μｍ厚の多孔質シリコンを形成した。
【０２４１】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０２４２】
４）１．３％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２４３】
５）ウエハをウエハキャリアに入れてセットするロードロック室とウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に前記ウエハをウエハキャリアに入れて設置した。ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。移載チャンバーは予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２４４】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２４５】
６）プロセスチャンバーの圧力を８０Ｔｏｒｒとし、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、８７０℃で５秒保持した後、温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハは８６０℃で６０秒保持し、これ以外は同じ処理をしてロードロック室に戻した。
【０２４６】
７）ロードロック室を大気開放してウエハを取り出し、市販の異物検査装置として、波長４８８ｎｍのアルゴンレーザーを斜め入射するサーフスキャン６４２０で多孔質層表面のヘイズ値を測定したところ、５秒処理のウエハ上の多孔質の平均ヘイズ値は、１０．２、３０秒処理の多孔質の平均ヘイズ値は、１９．５で、エピタキシャル成長装置に設置する前のサンプルの平均ヘイズ値８．５のそれぞれ約１．２、２．３倍であった。
【０２４７】
８）また、予め用意しておいたＳＯＩ基板をＨＦディップし、水洗して乾燥させたのち、ＳＯＩ層の膜厚を光干渉式膜厚計により測定し、５）、６）の処理を施し、ロードロックより取り出した。再びＳＯＩ層の膜厚を測定したところ、ＳＯＩ層の膜厚減少量は、いずれも１ｎｍ未満であった。
【０２４８】
９）４）の処理が終了したウエハを５）により、エピタキシャル成長装置のプロセスチャンバーに移載した。
【０２４９】
１０）プロセスチャンバーの圧力を８０Ｔｏｒｒに設定した後、サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、プリベーク処理として８６０℃で２秒保持した後、濃度３５ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加して、１５０秒処理し、ＳｉＨ₄ の添加は終了し、その後、ＳｉＨ₂ Ｃｌ₂ を濃度１ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を２μｍ形成し、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。もう１枚のウエハはプリベーク処理時間を６０秒とし、これ以外は同じ処理をしてロードロック室に戻した。
【０２５０】
１１）１０）の処理が終了したウエハを欠陥顕在化エッチングして、非多孔質単結晶シリコン層に導入された結晶欠陥を顕在化した後、ノマルスキー微分干渉顕微鏡で観察した。観察された欠陥は積層欠陥が９９％以上であった。積層欠陥の密度は、プリベーク５秒の場合、１２０個／ｃｍ² 、プリベーク３０秒の場合、４３０個／ｃｍ² で、プリベーク１１００℃１２０秒の場合の１．５×１０⁴ ／ｃｍ² に比べて激減し、１０００個／ｃｍ² 未満の欠陥密度が実現された。
【０２５１】
（実施例７−９５０℃，Ｐｒｅｂａｋｅ（２ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−０．３２μｍ）
１）ｐ型不純物としてボロンが添加され、比抵抗値が、０．０１５Ω・ｃｍ⁺ ／^- ０．０１Ω・ｃｍである、８インチの面方位（１００）のｐ⁺ シリコンウエハ（ＣＺウエハ）を用意した。
【０２５２】
２）この第１の単結晶Ｓｉ基板の表面層をＨＦ溶液中において陽極化成を行った。
【０２５３】
陽極化成条件は以下の通りであった。
【０２５４】
電流密度：７（ｍｉｎ）
陽極化成溶液：ＨＦ：Ｈ₂ Ｏ：Ｃ₂ Ｈ₅ ＯＨ＝１：１：１
時間：５（ｍＡ・ｃｍ^-2）
多孔質Ｓｉの厚み：５（μｍ）
さらに、
電流密度：５０（ｍＡ・ｃｍ^-2）
陽極化成溶液：ＨＦ：Ｈ₂ Ｏ：Ｃ₂ Ｈ₅ ＯＨ＝１：１：１
時間：１０（ｓｅｃ）
多孔質Ｓｉの厚み：〜０．２（μｍ）
５０（ｍＡ・ｃｍ^-2）で行った陽極化成では、多孔質Ｓｉ層の多孔度（ｐｏｒｏｓｉｔｙ）は大きくなり、構造的に脆弱な高多孔度薄層が形成された。すなわち、シリコンウエハの表面側から、低多孔度の多孔質層、高多孔度の多孔質層がこの順に形成された。
【０２５５】
３）つづいて、多孔質シリコン層を形成したウエハに、４００度の酸素雰囲気中で１時間酸化処理（プリ酸化）を施した。この酸化処理は、概ね５０Å以下の酸化膜しか形成しないので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０２５６】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスとして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２５７】
５）ウエハをウエハキャリアに入れてセットするロードロック室と、ウエハ移載用ロボットのセットされた移載チャンバーと、プロセスチャンバーとが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に、前記ウエハをウエハキャリアに入れて設置した。
【０２５８】
ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。
【０２５９】
移載チャンバーは、予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２６０】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２６１】
６）サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、熱処理（プリベーク処理）として９５０℃で２秒保持した後、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加して、２００秒処理をし、ＳｉＨ₄ の添加は終了し、その後、温度を９００℃に下げて、今度はＳｉＨ₂ Ｃｌ₂ を濃度０．５ｍｏｌ％になるように添加して、非多孔質単結晶シリコン膜を０．３２μｍ形成し水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。形成された非多孔質単結晶シリコン層の膜厚は平均０．３２μｍ，最大値−最小値＝８ｎｍであった。なお、熱処理前のヘイズ値９．５に対して、熱処理後は、１１．４であった。すなわち、ｒ＝１．２であった。
【０２６２】
また、予め用意しておいたＳＯＩ基板をＨＦディップし、水洗して乾燥させたのち、ＳＯＩ層の膜厚を光干渉式膜厚計により測定し、５）、６）の処理を施し、ロードロックより取り出した。再びＳＯＩ層の膜厚を測定したところ、ＳＯＩ層の膜厚減少量は、１ｎｍ未満であった。
【０２６３】
７）非多孔質単結晶シリコンをエピタキシャル成長したウエハを縦形炉に設置して、酸素と水素を燃焼して形成された水蒸気と残留酸素の混合気中、１０００℃で熱処理により前記非多孔質単結晶シリコンの表面を酸化して，２０８ｎｍの酸化シリコン膜を形成した。
【０２６４】
８）上記ウエハと第２のシリコンウエハをシリコン半導体プロセスの洗浄ラインで清浄に洗浄したのち、両ウエハの第１の主面同士を静かに重ね合わせ、中央を押圧したところ、両ウエハは一体化した。
【０２６５】
９）続いて、一体化したウエハ組を縦形炉に設置して、酸素雰囲気中１１００℃で１時間処理した。
【０２６６】
１０）貼り合わせウエハの側面にウォータージェットを噴きつけたところ、高多孔度層に亀裂が生じ分割された。分割方法は、ウォータージェット以外に加圧、引っ張り，せん断、楔、等の外圧をかける方法、超音波を印加する方法、熱をかける方法、酸化により多孔質Ｓｉを周辺から膨張させ多孔質Ｓｉ内に内圧をかける方法、パルス状に加熱し、熱応力をかける、あるいは軟化させる方法等がある。そのどの方法でも分離することは可能である。
【０２６７】
１１）露出した多孔質シリコン層を表面に有する第２のシリコンウエハを、ＨＦと過酸化水素水の混合溶液に漬けたところ、およそ２時間で多孔質シリコンはすべて除去され、ウエハ全面で、非多孔質単結晶シリコン層と熱酸化シリコン膜による干渉色が観察された。
【０２６８】
１２）１１）の処理が終了したウエハをシリコン半導体デバイスプロセスで一般的に用いる洗浄ラインで洗浄した後、縦形水素アニール炉に設置して、水素１００％雰囲気中で１１００℃４時間の熱処理を行った。水素ガスは装置とおよそ７ｍの内面研磨ステンレス配管で接続されたパラジウム合金を用いた市販の水素精製装置で純化されている。
【０２６９】
１３）こうして、第２のシリコンウエハ上に２００ｎｍの酸化シリコン層と２００ｎｍの単結晶シリコン層が積層されたＳＯＩ構造のウエハが作製された。
【０２７０】
単結晶シリコン層の膜厚は平均２０１ｎｍ、高さの最大値と最小値の差は８ｎｍであった。
【０２７１】
１４）１３）のウエハを欠陥顕在化エッチングにより単結晶シリコン層を１３０ｎｍ除去したのち、４９％ＨＦに３分漬けた。この結果、欠陥顕在化エッチングによりエッチングされた単結晶シリコン層に残留する結晶欠陥の部分から埋め込み酸化膜がＨＦによりエッチングされ、ノマルスキー微分干渉顕微鏡で容易に欠陥密度を測定できる。観察された欠陥の密度は、６４個／ｃｍ² であった。水素アニール処理により、非多孔質単結晶シリコン層に導入された積層欠陥が減少していた。欠陥密度１００個／ｃｍ² を下回り、かつ、膜厚の均一な薄膜ＳＯＩ層が得られた。
【０２７２】
（実施例８−９５０℃，８０Ｔｏｒｒ Ｐｒｅｂａｋｅ（２ｓ），Ｐｒｅｉｎｊｅｃｔｉｏｎ，Ｅｐｉ−０．０１μｍ Ｈｅｔｅｒｏ−ｅｐｉｔａｘｙ）
１）６１５μｍの厚みを持った比抵抗０．０１Ω・ｃｍのｐ型あるいはｎ型の６インチ径の（１００）単結晶Ｓｉ基板４枚をＨＦアルコールで希釈した溶液中で陽極化成することにより、その鏡面である一方の主面に多孔質Ｓｉ層を形成した。
【０２７３】
２）陽極化成条件は以下の通りであった。
【０２７４】
電流密度：７ｍＡ／ｃｍ²
陽極化成溶液：ＨＦ：Ｈ₂ Ｏ：Ｃ₂ Ｈ₅ ＯＨ＝１：１：１
時間：１２分
多孔質Ｓｉ層の厚み：１０μｍ
多孔度：２０％
【０２７５】
３）つづいて、多孔質シリコン層を形成したウエハに４００度の酸素雰囲気中で１時間酸化処理を施した。この酸化処理は概ね５０Å以下の酸化膜しか形成しないので酸化シリコン膜は多孔質シリコンの表面と孔の側壁にしか形成されておらず、内部には単結晶シリコンの領域が残されている。
【０２７６】
４）１．２５％に希釈したＨＦ水溶液に前記ウエハを３０秒程度曝し、続いて１０分間純水に漬けて、オーバーフローリンスして、多孔質層の表面に形成された極薄酸化シリコン膜を除去した。
【０２７７】
５）ウエハをウエハキャリアに入れてセットするロードロック室とウエハ移載用ロボットのセットされた移載チャンバーとプロセスチャンバーが接続されたエピタキシャルＣＶＤ成長装置のロードロック室に前記ウエハをウエハキャリアに入れて設置した。ロードロック室は、大気圧からドライポンプで１Ｔｏｒｒ以下に減圧したのち、Ｎ₂ を流して、８０Ｔｏｒｒにした。移載チャンバーは予めＮ₂ を流して８０Ｔｏｒｒに保持されている。プロセスチャンバーには、ウエハを保持するためにカーボンにＣＶＤ−ＳｉＣを被覆したサセプタが設置されている。サセプタは、ＩＲランプによって予め摂氏７５０℃程度に昇温してある。プロセスチャンバー内には加熱したパラジウム合金を用いた水素精製機により、精製された水素ガスが精製機からおよそ１０ｍの内面研磨したステンレス配管によりプロセスチャンバーに供給されている。
【０２７８】
ウエハはロードロック室から移載チャンバーを経由してプロセスチャンバーへ移載ロボットにより搬送され、サセプタ上に設置された。
【０２７９】
６）サセプタ上に移載されたウエハをＩＲランプで加熱して毎分１００℃の速度で昇温し、熱処理（プリベーク処理）として９５０℃で２秒保持した後、濃度２８ｐｐｍになるように水素のキャリアガスにＳｉＨ₄ を添加して、２００秒処理をし、ＳｉＨ₄ の添加は終了し、その後、水素雰囲気下で温度を７５０℃まで降温し、ウエハを再び移載ロボットにて移載チャンバーを経由しロードロック室に取り出した。形成された非多孔質単結晶シリコン層の膜厚は平均０．０３μｍであった。なお、熱処理前のヘイズ値８．５に対して、熱処理後は、１１．２であった。
【０２８０】
この多孔質Ｓｉ上にＭＯＣＶＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法により単結晶ＧａＡｓを１μｍの厚みにエピタキシャル成長した。成長条件は以下の通りであった。
【０２８１】
ソースガス：ＴＭＧ／ＡｓＨ₃ ／Ｈ₂
ガス圧力：８０Ｔｏｒｒ
温度：７００℃
【０２８２】
透過電子顕微鏡による断面観察の結果、ＧａＡｓ層に結晶欠陥が導入されておらず、良好な結晶性を有するＧａＡｓ層が形成されたことが確認された。同時に、表面をＳｉにより封止された多孔質Ｓｉ層との間には極めて急峻な界面が形成されていることも確認された。
【０２８３】
さらに欠陥顕在化エッチングにより、光学顕微鏡により顕在化された結晶欠陥をカウントし欠陥密度を求めたところ，およそ１×１０⁴ ／ｃｍ² であった。
【０２８４】
【発明の効果】
以上説明したように、本発明によれは、多孔質シリコン層上への非多孔質単結晶層の成長に先立って行われる熱処理（プリベーク）条件を、測定が簡易なヘイズ値の変化率ｒを利用して定めることができる。
【０２８５】
また、以上説明したように、本発明によれば、熱処理（プリベーク）を、多孔質シリコンの表面のヘイズ値の熱処理前後での変化率ｒを３．５以内、より好ましくは２以内、かつ、該熱処理でのシリコンエッチング量を２ｎｍ以下、より好ましくは１ｎｍ以下に抑制する条件で実施することにより、多孔質層上に形成される非多孔質単結晶シリコン層の積層欠陥密度を１０００／ｃｍ² 未満、さらには、１００／ｃｍ² 程度にできた。さらに非多孔質単結晶シリコンの成長初期のシリコン原料の成長表面への供給量を微量にすることで、本発明の欠陥低減をさらに向上させることができる。
【０２８６】
その結果、本発明を、貼り合わせ法に適用すれば、膜厚が均一で、かつ、結晶欠陥が極めて少ないＳＯＩ層を得ることが可能である。
【０２８７】
本発明は言い換えるとエピタキシャル成長装置内で形成されてしまう多孔質表面の自然酸化膜の量を抑制することで、自然酸化膜除去のための熱処理時間・温度を短時間、低温化するものである。そして同時に多孔質層の表面及び、表面近傍の構造変化を抑制し、多孔質層の表面構造の変質が顕在化する前に、非多孔質単結晶シリコン膜の形成を開始することにより、結晶欠陥密度１０００・ｃｍ² 未満のエピタキシャルシリコン層を得るものである。
【図面の簡単な説明】
【図１】多孔質シリコン層上への非多孔質単結晶層の形成方法を示すフローチャートである。
【図２】ロードロック室付の装置の一例を示す図である。
【図３】エピタキシャル成長装置におけるシリコンエッチング量を説明する図である。
【図４】熱処理温度と欠陥密度の関係をエピタキシャル成長装置の違いによって説明する図である。
【図５】多孔質シリコンの熱処理によるヘイズ値の変化を説明する図である。
【図６】ヘイズ値の変化率と欠陥密度の関係を説明する図である。
【図７】多孔質層の表面孔の熱処理による変化を説明するＳＥＭ像である。
【図８】多孔質層の表面孔の熱処理による変化を説明する模式図である。
【図９】微量シリコン原料供給工程の時間と欠陥密度の関係を説明する図である。
【図１０】微量シリコン供給によるヘイズ値の変化を説明する図である。
【図１１】熱処理時の圧力の違いによる熱処理温度と欠陥密度の関係の違いを説明する図である。
【図１２】熱処理時間と欠陥密度の関係を説明する図である。
【図１３】プリベーク処理を適切に行うための条件を決定するシステムの一例である。
【図１４】本発明の工程を説明する模式図である。
【図１５】本発明によるＳＯＩ基板の作製工程を説明する模式図である。
【図１６】異物検査装置の観測方法の概念図である。
【符号の説明】
１ 多孔質シリコン層を有する基板
２ 孔
３ 孔壁
４ 保護膜
５ 保護被膜
６ 非多孔質単結晶層
１０ 基体
１１ 多孔質シリコン層
１３ 入射光
１４ 反射光
１５ 散乱光
１６ シリコンウエハ
１７ 観察領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to a non-porous semiconductor layer formed on a porous semiconductor layer and a method for forming the same. Furthermore, the present invention relates to a method for evaluating a semiconductor substrate, particularly a porous layer surface shape / state, and a method for producing a semiconductor substrate using the evaluation method.
[0002]
The present invention also relates to a semiconductor substrate used as a substrate of an integrated circuit mainly using MOSFETs, bipolar transistors, and the like, and a method for forming the same.
[0003]
[Prior art]
In silicon-based semiconductor devices and integrated circuit technology, the silicon-on-insulator (SOI) structure in which a single-crystal silicon film is placed on an insulator is used to increase the speed and reduce the consumption of transistors by reducing parasitic capacitance and facilitating element isolation. Numerous studies have been made so far for technologies that provide power, high integration, and reduced total cost.
[0004]
As a method of forming this SOI structure, there is a FIPOS (Fully Isolation by Porous Silicon) method proposed by Imai, which was popular from the 1970s to the early 1980s. (K. Imai, Solid State Electronics 24 (1981) P. 159). This method forms an SOI structure by utilizing the accelerated oxidation phenomenon of porous silicon, but has a specific problem that the surface silicon layer can be formed only in an island shape.
[0005]
One of the SOI forming technologies that has been attracting attention recently is wafer bonding technology, which is a surface silicon layer having an SOI structure, an arbitrary thickness of a buried silicon oxide layer, and crystallinity of the surface silicon layer. Various techniques have been proposed for their goodness.
[0006]
A bonding method for bonding wafers without an intermediate layer such as an adhesive was proposed by Nakamura et al. B. Lasky et al. (JB Lasky, SR Stiffler, FR White, and JR Abnerthey, technical Digestof the International Electron Meeting, IEEE 1988, New York, P. 5). Since 1984, the method of thinning one of the combined wafers and the operation of the MOS transistor formed thereon have been reported.
[0007]
In the Lasky method, a first wafer having a low-concentration or n-type epitaxial silicon layer formed on a single-crystal silicon wafer to which boron is added at a high concentration is prepared, and the first wafer and the surface thereof are prepared. When the second wafer on which the oxide film has been formed is cleaned as necessary and then brought into close contact, the two wafers are bonded by van der Waals force. When heat treatment is further performed, a covalent bond is formed between the two wafers, and the bonding strength increases to a level that does not hinder device fabrication. After that, the first wafer is etched from the back surface with a mixed solution of hydrofluoric acid, nitric acid and acetic acid, and p⁺Lasky et al. (Single Etch-stop method) selectively removes the silicon wafer and leaves only the epitaxial silicon layer on the second wafer. However, p⁺Silicon and epitaxial silicon (P^-Alternatively, the ratio of the etching rate of n) is as low as several tens, and further improvement has been desired in order to leave an epitaxial silicon layer having a uniform film thickness on the entire wafer surface.
[0008]
Therefore, a method of performing selective etching in two steps has been devised. That is, as the first substrate, p is formed on the surface of the low impurity concentration silicon wafer substrate.⁺⁺A layer in which a Si layer and a low impurity concentration layer are stacked is prepared, and this substrate is bonded to a second substrate similar to the above method. After that, the first substrate is thinned from the back surface by a mechanical method such as grinding or polishing. Next, p embedded in the first substrate⁺⁺Selective etching is performed until the Si layer is exposed on the entire surface. At this time, by using an alkali solution such as ethylenediamine pyrocatechol or KOH as an etching solution, selective etching is performed according to the difference in impurity concentration of the substrate. After that, p exposed by selective etching with a mixed solution of hydrofluoric acid, nitric acid and acetic acid as in the method of Lasky et al.⁺⁺If the Si layer is selectively removed, only the low-impurity concentration single-crystal Si layer is transferred onto the second substrate (Double Etch-stop method). In this method, the selective etching is performed a plurality of times to improve the overall etching selectivity, and as a result, the film thickness uniformity of the surface Si layer in the SOI is improved.
[0009]
However, in the thinning by selective etching using the impurity concentration of the substrate or the difference in composition as described above, it is predicted to be affected by the profile in the depth direction of the impurity concentration. In other words, if the heat treatment after bonding is increased to increase the bonding strength of the wafer, impurities in the buried layer are diffused, resulting in a deterioration in etching selectivity, resulting in a deterioration in film thickness uniformity. It was. Therefore, the heat treatment after bonding needs to be 800 degrees Celsius or less. Further, since the etching selectivity is low in each of the multiple etchings, the controllability at the time of mass production has been questioned.
[0010]
In the above-described method, the etching selectivity is determined by the impurity concentration or the difference in composition. However, in order to solve such a problem, Japanese Patent Laid-Open No. 5-21338 seeks the etching selectivity to the difference in structure. Yes. That is, the surface area per unit volume is 200 m.² / Cm^Three Due to the difference in the structure of porous silicon and non-porous silicon, selective etching as high as 100,000 times is realized (selective etching method using a difference in structure using porous silicon). In this method, the surface of a single crystal Si wafer as a first substrate is made porous by anodization, and then a non-porous single crystal silicon layer is epitaxially grown to form a first substrate. After that, after bonding to the second substrate and increasing the bonding strength by heat treatment or the like, if necessary, the back surface of the first substrate is removed by grinding, polishing or the like to expose the porous silicon layer over the entire surface. Thereafter, the porous silicon is selectively removed by etching, and as a result, the previous non-porous single crystal silicon layer is transferred onto the second substrate. As a result of obtaining a high selectivity ratio of 100,000 times, the film thickness uniformity of the obtained SOI layer is hardly damaged by etching, and the uniformity during the growth of the epitaxially grown single crystal silicon layer is reflected as it is. It was revealed. That is, for example, 1.5 to 3% or less is realized in the SOI-Si layer as uniformity within the wafer realized by a commercially available CVD epitaxial growth apparatus. In this method, porous silicon which has been a material for selective oxidation by FIPOS is used as a material for selective etching. Therefore, Porosity is not limited to around 56%, but rather a low value of around 20% is preferable. The method for producing the SOI structure disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-21338 has been reported by Yonehara et al. (T. Yonehara, K. Sakaguchi, N. Sato, Appl. Phys. Lett. 64 (1994) p. 2108) and named ELTRAN (registered trademark).
[0011]
Further, since it does not become a structural material of the final porous silicon, structural change and coarsening of the porous silicon are allowed within a range that does not impair the etching selectivity.
[0012]
Inventor Sato et al. (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama, and T. Yonehara, Proc. Of the Seventh Int. Symp. On Sci. On Sci. And Sci. (Pennigton, The Electrochem. Soc. Inc., 1994), P. 443) is SiHH as epitaxial growth on porous materials.₂ Cl₂ A CVD (Chemical Vapor Deposition) method is carried out using as a source gas, and the process temperature at that time is 1040 ° C. for the heat treatment performed before the epitaxial growth and 900-950 ° C. for the epitaxial growth.
[0013]
The structure of porous silicon is greatly roughened by high-temperature heat treatment, but Sato et al. Introduced a preoxidation process, which is a process of forming a protective film on the porous silicon pore wall prior to epitaxial growth. As a result, the coarsening of the porous silicon layer accompanying the heat treatment is substantially suppressed. This pre-oxidation is performed at 400 ° C. in an oxygen atmosphere, for example.
[0014]
In this method, one of the important techniques is how to form an epitaxial growth of non-porous single crystal silicon on porous silicon with few defects. In the SOI wafer thus formed, stacking faults are the main defects, and the stacking fault density in the epitaxial silicon layer on the porous silicon is 10^Three -10^Four / Cm² It is reported.
[0015]
[Problems to be solved by the invention]
In general, it has been pointed out that stacking faults may cause deterioration of the dielectric strength of an oxide film. This is considered to increase the leakage current of the pn junction and degrade the minority carrier lifetime when metal impurities are deposited at the transition portion surrounding the stacking fault. Even in other reports on the epitaxial growth on the above-described porous structure, the crystal defect is observed by the method of observing with an optical microscope after the defect revealing etching having a lower detection limit.^Three / Cm² There was no report that it was below. 10^Three -10^Four / Cm² Stacking fault of 1μm² Although the probability of being included in the gate region is as low as about 0.0001 to 0.00001, the defect density is still higher than that of the bulk silicon wafer, and the influence thereof is generally surfaced as the yield of the integrated circuit. is expected. When the SOI wafer obtained by the above method is put into practical use, the stacking fault density is at least 1000 / cm.² The following are required to be reduced.
[0016]
Moreover, the reason why many stacking faults are introduced when epitaxially growing non-porous single crystal silicon on a porous silicon layer is that the support substrate for epitaxial growth has a “porous structure”.
[0017]
Conventionally, as a method for evaluating (observing) this porous structure, particularly the surface shape and state thereof, a means for observing directly by SEM or the like has been mainly used, but the means is complicated and more There has been a demand for a method that can be easily evaluated.
[0018]
(Object of invention)
A first object of the present invention is to provide a semiconductor substrate having a non-porous single crystal layer with reduced crystal defects on a porous silicon layer and a method for manufacturing the substrate.
[0019]
The second object of the present invention is to provide a substrate having a non-porous crystal layer with a low crystal defect density on an insulator and a method for manufacturing the same.
[0020]
The third object of the present invention is to provide a simple evaluation method of the surface state of the porous layer, and to reduce the stacking fault density of a thin film formed on the porous using the evaluation method. is there.
[0021]
[Means for Solving the Problems]
  The present invention provides a method for producing a semiconductor substrate having a non-porous single crystal layer on a porous silicon layer, prior to the step of forming the non-porous single crystal layer on the porous silicon layer. A rate of change r (r = (the heat treatment) of the surface of the porous silicon layer before and after the heat treatment, including a step of heat-treating the silicon layer in an atmosphere containing no source gas of the non-porous single crystal layer. Haze value of the surface of the porous silicon layer after) / (haze value of the surface of the porous silicon layer before the heat treatment))1 ≦ r ≦ 3.5 is satisfiedIt is characterized by that.
[0022]
  Furthermore, the present invention includes a step of preparing a substrate having a porous silicon layer, a heat treatment step of heat-treating the porous silicon layer, and a growth step of growing a non-porous single crystal layer on the porous silicon layer. In the method for manufacturing a semiconductor substrate, the heat treatment is performed in an atmosphere that does not include a source gas of the non-porous single crystal layer, and an etching amount of silicon by the heat treatment is 2 nm or less, and a haze value of the surface of the porous silicon layer The rate of change r (r = the haze value after heat treatment / the haze value before heat treatment) is such that 1 ≦ r ≦ 3.5 is satisfied.
[0023]
The present invention also includes a step of preparing a first substrate having a porous silicon layer, a heat treatment step of heat-treating the porous silicon layer, a growth step of growing a non-porous single crystal layer on the porous silicon layer, And a step of transferring the non-porous single crystal layer on the first substrate onto a second substrate, wherein the heat treatment uses a source gas of the non-porous single crystal layer. In an atmosphere that does not contain, the etching amount of silicon by the heat treatment is 2 nm or less, and the change rate r of the haze value of the porous silicon layer surface (r = the haze value after the heat treatment / the haze value before the heat treatment), The process is performed so as to satisfy 1 ≦ r ≦ 3.5.
[0024]
Before describing embodiments of the invention, a method for forming a non-porous layer on a porous substrate will be described, and then experimental results leading to the present invention will be described.
[0025]
A method for forming a non-porous single crystal layer (epitaxial growth layer) on the porous silicon layer will be described with reference to the flowchart of FIG.
[0026]
First, a substrate having a porous silicon layer is prepared (S1). Next, prior to the growth of the non-porous single crystal layer, the porous silicon layer is heat-treated in an atmosphere that does not contain the source gas of the non-porous single crystal layer.
[0027]
This is called a pre-baking step (S2) and is a step of removing a natural oxide film adhering to the surface of the porous silicon layer.
[0028]
In addition, the above-mentioned “under the atmosphere not containing the source gas of the non-porous single crystal layer” specifically means a reducing atmosphere containing hydrogen gas or an inert gas atmosphere such as He, Ar, Ne, or the like. Heat treatment in ultra high vacuum.
[0029]
After the pre-baking step, a raw material gas is introduced to grow a non-porous single crystal layer (S3). Thus, a non-porous single crystal layer is formed on the porous silicon layer.
[0030]
Next, technical knowledge that has led to the present invention will be described.
[0031]
(Experiment 1: Difference in Si etching amount in temperature raising process before shrimp film growth)
FIG. 3 shows the time dependence of the amount of thickness reduction due to etching of the non-porous single crystal silicon surface in two epitaxial growth systems. System A is a system using a device with a load lock chamber, and System B is a system using a device having a reaction chamber that is open to the atmosphere without a load lock chamber.
[0032]
Specifically, the system A apparatus is provided with a load lock chamber, as described in detail below, so that wafers can be taken in and out without directly exposing the reaction chamber to the atmosphere.
[0033]
The amount of leakage in the reaction chamber is 20 mTorr / min or less, more preferably 10 mTorr / min or less.
[0034]
Further, the leakage amount of the gas panel of the supply gas system should be 0.5 psi / 24 h, more preferably 0.2 psi / 24 h or less.
[0035]
Furthermore, it is preferable to use a high-purity supply gas, specifically, for example, H₂ When prebaking with gas, it is preferable to use a gas purifier disposed within about 20 m, preferably within 10 m near the apparatus. As the purifier, a type that is equivalent to a heated palladium cell or a filter type that is equipped with an adsorbent is preferably used.
[0036]
The processing apparatus schematically shown in FIG. 2 was used.
[0037]
21 is a reaction chamber (process chamber), 22 is a load lock chamber, and 32 is a transfer chamber (transfer chamber). A gate valve 23 partitions the reaction chamber 21 and the transfer chamber 32, and a gate valve 24 partitions the transfer chamber 32 and the load lock chamber 22. Reference numeral 25 denotes a heater such as a lamp for heating the substrate W, 26 denotes a susceptor on which the substrate W is placed, and 27, 28, and 33 exhaust the reaction chamber 21 and the rod lock chamber 22 and the transfer chamber 32, respectively. An exhaust system 29 for supplying the processing gas into the reaction chamber 21, and a gas supply system 30 and 34 for introducing a gas for purging the inside of the transfer chamber 32 and the rod lock chamber 22 and for increasing the pressure. Gas supply system. Reference numeral 31 denotes a transfer arm for carrying the substrate W into and out of the reaction chamber 21. Reference numeral 35 denotes a wafer cassette.
[0038]
Further, as a modification, the rod lock chamber 22 may be integrated without partitioning the transport chamber 32 that houses the transport arm by the gate valve 24.
[0039]
The heat treatment performed using such a processing apparatus with a load lock chamber is referred to as “heat treatment in system A” for convenience.
[0040]
In this system A, the reaction chamber heater can be operated in advance, and the temperature of the susceptor or the like can be raised to about 600 ° C to 1000 ° C.
[0041]
By adopting this method, it is possible to raise the temperature of the wafer introduced into the reaction chamber to 600 ° C. to 1000 ° C. in about 10 seconds, shortening the temperature raising time, and pores on the surface of the porous silicon described later. It is possible to suppress the progress of the state change by this heat treatment.
[0042]
The heat treatment temperature is 1100 ° C. for system A, 1050 ° C. for system B, 600 Torr for system A, 760 Torr for system B, and the atmosphere is hydrogen gas. The etching amount was obtained by measuring the amount of decrease in the thickness of the SOI layer using an SOI substrate.
[0043]
In the system B, the etching amount is 7 nm or more even when the heat treatment time is zero. This means an etching amount when the temperature is lowered immediately after the substrate is heated to a set temperature. Only by raising the temperature, the silicon thickness decreases even near 7 nm.
[0044]
On the other hand, in the system A, the etching amount is 2 nm or less even after heat treatment for 10 minutes. In System A, it is known that the etching amount with respect to the heat treatment time is larger at 1100 ° C. than at the set temperature of 1050 ° C.
[0045]
This difference is explained by the oxidation of silicon and the etching of the formed silicon oxide in the temperature rising process with oxygen and moisture in the reaction vessel. The oxygen content / moisture in the reaction vessel is determined by the purity of the gas supplied, the adsorbed moisture in the supply pipe, minute leaks, the airtightness of the reaction vessel itself, and the incorporation of the substrate into the reaction vessel. The mixing of oxygen and hydrogen at the time of carrying in the substrate greatly affects whether the substrate is introduced into the reaction vessel via the load lock, or whether the substrate is carried in by directly opening the reaction vessel to the atmosphere.
[0046]
However, even if the reaction vessel is opened to the atmosphere, if the gas in the vessel is sufficiently replaced without raising the temperature thereafter, the residual oxygen / water concentration is reduced, but efficiency becomes a problem in mass production. The etching amount is also affected by the time required to raise the temperature to the set temperature. When supported by a substrate holder having a small heat capacity, it is possible to increase the rate of temperature increase.
[0047]
In addition, when a small amount of oxygen and moisture are present in the system, if these concentrations are low, etching silicon is
F. w. Smith et. al. J. et al. Electrochem. Soc. 129 1300 (1982) and
G. Ghidini et. al. J. et al. Electrochem. Soc. 131 2924 (1984).
[0048]
On the other hand, when the concentration of moisture or the like increases, silicon is oxidized to form silicon oxide. And this silicon oxide reacts with adjacent silicon with temperature rise, and will be etched. SiO₂ It reacts with + Si → 2SiO ↑.
[0049]
Eventually, oxygen and moisture remaining in the system are parasitic on the etching of silicon during the temperature rise, so that the amount of residual oxygen / water in the reaction vessel can be grasped by examining the etching amount of silicon.
[0050]
(Experiment 2: Relationship between prebaking temperature and stacking fault density)
FIG. 4 shows the dependence of the stacking fault density introduced into the non-porous single crystal silicon formed on the porous silicon layer in these systems A and B on the heat treatment temperature (prebake temperature). The pressure in the system A is 600 Torr, and the pressures in the systems B-1 and B-2 are both 760 Torr.
[0051]
System B-1 and System B-2 are data reported in Sato et al. (N. Sato et. Al. Jpn. J. Appl. Phys. 35 (1996) 973). The stacking fault density decreases as the pre-baking temperature is increased. In system B-2, the growth rate is remarkably suppressed by reducing the amount of silicon source gas supplied at the initial stage of growth. Although the stacking fault density is reduced to about 1/3 regardless of the temperature as compared with the system B-1, the defect density is reduced only when the heat treatment temperature is increased in any case.
[0052]
The reason why the stacking fault density is reduced by increasing the pre-baking temperature in this way is as follows. In systems B-1 and B-2 where the silicon etching amount is as large as about 7 nm, silicon oxide is temporarily formed on the silicon surface by residual oxygen and moisture during the temperature rising process. In the low temperature region, the formed silicon oxide cannot be removed, so the defect density is high. However, if sufficient heat treatment temperature and time are secured, it is considered that the density of crystal defects begins to decrease as a result of removing the formed silicon oxide.
[0053]
On the other hand, in system A, the crystal defect density is 10 in the high temperature region exceeding 1000 ° C.^Four / Cm² On the stage, the defect density does not decrease as significantly as the systems B-1 and B-2 even when the heat treatment temperature is increased. However, as the temperature is lowered, there is a minimum value of defect density around 950 ° C., and the defect density is 10% at 950 ° C.² / Cm² Decreased to a degree.
[0054]
That is, unlike the systems B-1 and B-2 with a large amount of silicon etching, it was found that the system A with a silicon etching amount as small as 2 nm or less can reduce the stacking fault density without accompanied by a porous structural change and coarsening. .
[0055]
From the above, the imperial silicon between the installation of the substrate on which the porous silicon layer is formed in the epitaxial growth apparatus and the introduction of the silicon source gas into the reaction vessel to start the formation of the non-porous single crystal layer It has been found that the amount of silicon etched from the surface of the layer, that is, the amount of decrease in the thickness of the porous silicon layer, plays an important role in introducing stacking faults into the non-porous single crystal silicon layer.
[0056]
(Experiment 3: Relationship between haze level and stacking fault density)
On the other hand, in the system A, the substrate on which the porous silicon layer is formed is subjected only to the prebake treatment in order to clarify the reason why the defect density takes a minimum value near 950 ° C. The surface haze level on which porous silicon was formed was measured with an inspection apparatus.
[0057]
For measuring the haze level, a foreign substance inspection apparatus is commercially available from a plurality of apparatus manufacturers as an apparatus for detecting the position, size, etc. of the foreign substance (Particle) on the mirror surface of the silicon wafer. It was. In these foreign matter inspection devices, laser light is incident on a silicon wafer, and foreign matter is detected by monitoring scattered light instead of regular reflection light. By moving the laser beam or the silicon wafer side, the position within the wafer where the laser beam is incident is moved, and the scattered light intensity at each location is monitored in correspondence with the coordinate position. When the laser beam reaches a place where there is a foreign object, the laser is scattered by the foreign object, so that the scattered light intensity increases.
[0058]
FIG. 16 is a conceptual diagram of observation in Tencor Surf Scan 6420. The method of calibrating this scattered light intensity in advance with standard particles such as latex particles and converting it to the size of foreign matter is a method adopted in many foreign-purpose foreign matter inspection apparatuses currently on the market. Incidentally, 50 is incident light, 51 is reflected light, 52 is scattered light, 53 is a silicon wafer, and 54 is an observation region.
[0059]
The surface of a silicon wafer is mirror-finished by mechanochemical polishing, etc., but when viewed microscopically, it is not a completely flat surface, but a surface composed of uneven components with various periods and amplitudes, such as minute roughness and long-period waviness It has been confirmed by observation with an atomic force microscope or an optical interference microscope. These irregularities give a minute scattered light component when a laser beam used in a foreign matter inspection apparatus is incident. Compared with such a foreign object, the scattered light observed over a wide area, not locally, does not have a sudden change in signal intensity at a certain place like a foreign object when viewed along the movement of the laser light irradiation position. Without giving a constant strength.
[0060]
In other words, it can be said to be a direct current component (DC component) or a background component. That is, if a sudden signal change such as a foreign object is removed and a continuous scattered light component is observed, it means that the surface unevenness is monitored, and this is called haze. .
[0061]
The haze is generally displayed as a specular reflection light intensity or a ratio (unit: ppm) of scattered light intensity to incident light intensity. However, since the detection positions of incident light and scattered light are different in each device, it is difficult to compare absolute values.
[0062]
Further, since the scattered light intensity is generally up to about several tens of ppm, the ratio to the regular reflection light and the ratio to the incident light are almost the same.
[0063]
Commercially available foreign matter inspection apparatuses have each company's ingenuity in the incident angle, wavelength, and monitor position of scattered light.
[0064]
However, it is a well-known fact that laser light used as incident light does not completely reflect on the surface but also penetrates into silicon, and the depth of the penetration depends on the wavelength.
[0065]
Porous silicon has a structure in which many fine holes are formed by etching from the surface of a silicon wafer, but the side wall of the holes scatters the laser light that has penetrated.
[0066]
That is, if laser light is incident on the porous silicon surface and the scattered light is observed, information reflecting the surface of the porous layer and the porous structure near the surface can be obtained.
[0067]
In the formation of the non-porous single crystal silicon layer on the porous silicon, the inventor has introduced the haze value immediately before the non-porous single crystal silicon layer formation, that is, immediately after the pre-bake process, into the non-porous single crystal silicon layer. It was found to correlate with the crystal defect density.
[0068]
Install porous silicon in the epitaxial growth device, raise the temperature, introduce silicon source gas, perform heat treatment just before forming the non-porous single crystal silicon layer, and keep the haze value of porous silicon taken out from the device constant It was found that the crystal defect density of the non-porous single crystal silicon layer can be suppressed by controlling the range.
[0069]
Porous silicon is HF-C₂ H_Five OH-H₂ Anodization was performed in an O mixed solution, and then heat treatment was performed in an oxygen atmosphere at 400 ° C. for 1 hour (Preoxidation). Thereafter, it was immersed in a 1.25% HF aqueous solution for about 25 seconds, washed with water, dried, and then placed in an epitaxial growth apparatus.
[0070]
FIG. 5 shows the result of measuring the haze value with a foreign substance inspection apparatus after performing only heat treatment at 950 ° C. and 600 Torr and taking out from the epitaxial growth apparatus.
[0071]
The haze value was about 6 after preoxidation, but increased to about 9 by the treatment with the HF solution.
[0072]
The haze value starts to rise as the time for the heat treatment described above increases in the epitaxial growth apparatus. It rose to 11.9 at 2 seconds, 12.7 at 30 seconds, 16.3 at 60 seconds, and 25.7 at 120 seconds. The haze value of the surface of a commercially available silicon wafer was 0.18.
[0073]
FIG. 6 shows the correlation between the haze value obtained by variously changing the temperature and time of the heat treatment performed before the growth of the non-porous single crystal layer and the stacking fault density.
[0074]
It has been found that the stacking fault density is kept low when the increase in haze value is within 3.5 times, more preferably within 2 times. It is considered that the increase in haze value due to heat treatment is accompanied by a change in the porous structure.
[0075]
FIG. 7 shows a high-resolution scanning electron that is taken out from the epitaxial growth apparatus immediately after installation at the epitaxial growth apparatus (a) and after processing at 950 ° C., 2 seconds (b), 1100 ° C., 2 seconds (c). It is the photograph which observed the surface of the porous silicon layer with the microscope. The haze values were 9, 11.9, and 45, respectively. FIG. 8 schematically shows FIGS. 7A, 7B, and 7C, respectively.
[0076]
FIG. 7A is a schematic diagram of an SEM image of the porous silicon surface immediately before being installed in the epitaxial growth apparatus. 10 holes with a diameter of about 10 nm¹¹/ Cm² The density is formed. FIG. 7B shows a schematic diagram of an SEM image of the surface of the porous silicon that has been heat-treated at 950 ° C. and 600 Torr for 2 seconds. The pore density has decreased somewhat, but still 10^Ten/ Cm² It is a stand.
[0077]
On the other hand, when the porous surface treated at 1100 ° C. for 2 seconds is observed, the pore density is remarkably reduced to about 10⁶ / Cm² Had decreased. The remaining holes had a large hole diameter as shown in FIG. 7 (c), and some had a diameter of 40 nm. The increase in the hole diameter is caused by oxidation by residual oxygen / water, etching, enlargement by surface diffusion, coalescence of adjacent holes, and the like. As is apparent from the figure, the heat treatment strength increases, and generally the pore density decreases on the porous surface, and a smooth surface is formed. However, the hole diameter of the residual holes is increasing, indicating that the movement of silicon atoms on and near the surface is intense. When a cross-sectional observation was performed, it was confirmed that the porous structure immediately below the surface had undergone structural changes such as an increase in pore diameter as the heat treatment strength increased. That is, the increase in the haze value in the order of FIG. 7 (a) → (b) → (c) reflects the influence of the structural change on the surface of the porous layer and the structural change in the porous layer. Means that. The stacking fault density is 1 × 10 in the case of FIG.² Piece / cm² In the case of FIG. 7C, 2 × 10^FourPiece / cm² Met.
[0078]
Changes in the haze value of the porous layer due to the heat treatment from the introduction of the substrate having porous silicon to the epitaxial growth apparatus capable of suppressing the etching amount of silicon to 2 nm, more preferably 1 nm or less, until the silicon source gas is introduced. By suppressing it within 4 times, more preferably within 2 times, the conventional crystal defect density of 10^Three -10^Four / Cm² 1x10 from the table² / Cm² It became clear that it can be reduced to the extent. However, as described above, in a system with a large amount of silicon etching, it is difficult to reduce defects at low temperatures because the amount of oxidation is large. This is because a growth system with a large etching amount of single crystal silicon has a large amount of oxidation at the time of temperature rise.
[0079]
It should be noted that if a small amount of silicon atoms or silicon source gas is supplied at the initial stage of growth as disclosed in JP-A-9-100197, the reduction of crystal defects according to the present invention becomes more effective. The process of supplying a small amount of silicon atoms or the like in the initial stage of growth is sometimes referred to as a preinjection process.
[0080]
As an example of the present invention, a porous substrate previously formed on a susceptor coated with carbon CVD-SiC maintained at about 750 ° C. in an atmosphere of hydrogen 43 (1 / min) and a pressure of 600 Torr is passed through a load lock. And then heated to 950 ° C. at a rate of about 100 ° C./min and held for 2 seconds, then SiH_Four After adding a concentration of about 28 ppm for a certain time, the flow rate of the silicon source gas was increased to form a non-porous single crystal silicon film having a desired film thickness. FIG. 9 shows SiH_Four The stacking fault density dependence on the addition treatment time was shown. SiH_Four It is clear that the crystal defect density is reduced by performing a minute addition treatment.
[0081]
FIG. 10 shows the result of taking out the substrate from the epitaxial growth apparatus and measuring the haze value after initial growth by supplying a small amount of silicon. As apparent from the figure, the haze value once rises by the supply process of the trace amount silicon, and then starts to decrease again. As shown in FIG. 10, it is effective to carry out the trace silicon supply step at least until the haze value tends to decrease.
[0082]
Porous silicon is HF-C₂ H_Five OH-H₂ Anodization was performed in an O mixed solution, followed by heat treatment at 400 ° C. in an oxygen atmosphere for 1 hour. Thereafter, it was immersed in a 1.25% HF aqueous solution for about 25 seconds, washed with water, dried, and then placed in an epitaxial growth apparatus.
[0083]
In addition, supply of a minute amount of constituent atoms of the film or source gas has an effect of accelerating the removal of the oxide and suppressing the generation of defects due to the oxide.
[0084]
That is, according to the present invention, the pre-epitaxial heat treatment in which the etching amount of single crystal silicon is extremely small is performed within a range in which the decrease in the haze value on the surface of the porous silicon is suppressed to 4 times, more preferably within 2 times. The stacking fault density of the non-porous single crystal silicon layer formed on the porous layer is 1000 / cm.² Less than 100 / cm² It became clear what can be done. Furthermore, the defect reduction of the present invention can be further improved by reducing the amount of the silicon raw material supplied to the growth surface at the initial growth stage of the non-porous single crystal silicon. In addition, the present invention is a method for managing the haze value derived from the DC level of scattered light in a device for observing the intensity of scattered light by irradiating the surface of the substrate with laser light from a commercially available foreign substance inspection device or the like. The process conditions can be easily controlled with a crystal defect density of 1000 / cm.² Or less, more preferably 100 / cm² It suppresses to the following.
[0085]
Furthermore, in the present invention, the heat treatment temperature, particularly the heat treatment temperature before sealing the pores can be lowered as shown in FIG. Since aggregation / expansion, fragmentation, and the like can be suppressed, the selectivity in selective etching of the porous layer in the subsequent process by the ELTRAN method (registered trademark) is not deteriorated. That is, the crystallinity of the non-porous single crystal silicon layer can be improved without generating a residue in removing the porous layer. Further, in the FIPOS method, the oxidation rate of selective oxidation of the porous layer is not deteriorated.
[0086]
In addition, the present inventor conducted the following experiment in order to investigate the correlation between the stacking fault density and the pressure during pre-baking.
[0087]
As a sample, a non-resistance 0.013-0.017 Ωcm wafer boron-doped on the substrate (100) Si was prepared. The anodizing condition is about 8 mA / cm in a solution of 49% HF and ethanol mixed 1: 1.² Was applied for 11 minutes to form a porous layer. The porosity was approximately 20%.
[0088]
After being immersed in a 1.25% HF solution for 25 seconds, it was washed with water and dried. After that, heat treatment was performed in an oxygen atmosphere at 400 ° C. for 1 hour, and the silicon oxide film was immersed for about 5 nm in a 1.25% HF solution, washed with water, and dried. .
[0089]
Next, regarding epitaxial growth on the porous layer, the epi apparatus was performed in a reaction vessel provided with a load lock chamber. Heat treatment was performed for 120 seconds at 80 Torr and 600 Torr in a hydrogen atmosphere. After that, SiH is added to the hydrogen carrier gas so that the concentration becomes 28 ppm._Four And treated for 120 seconds. Then SiH_Four The addition of was completed, and the pressure was lowered to 80 Torr and the temperature was lowered to 900 ° C. to form a 2 μm epi layer. And the stacking fault temperature in each heat processing temperature was investigated.
[0090]
The result is shown in FIG. As a result, it was found that the pressure has a significant effect on the surface diffusion of the silicon atoms and the alteration of the pore structure on the porous silicon surface, and the lower the pressure, the lower the manifestation of the decrease in stacking fault density. .
[0091]
FIG. 12 shows the dependence of stacking fault density on the heat treatment time before growth in a heat treatment at 600 Torr and 950 ° C. in a hydrogen atmosphere for a sample manufactured in the same manner as FIG. It has been found that the heat treatment increases approximately twice as long as it exceeds 120 seconds, compared with up to 60 seconds.
[0092]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment Example 1
FIG. 13A is an example of a system that determines conditions for appropriately performing the pre-baking treatment of the porous layer.
[0093]
As is clear from Experiment 3, this is based on the fact that the change in haze value before and after pre-baking is correlated with the stacking fault density.
[0094]
After the porous layer is formed, the haze value of the porous layer immediately before the pre-bake treatment is measured (the measured haze value is d₀ And).
[0095]
Then, a pre-bake treatment is performed, and a haze value is further measured (the measured haze value is d₁ And).
[0096]
Thereafter, the change in haze value is evaluated. In particular
[0097]
[Outside 1]

If 1 ≦ r ≦ 3.5, the subsequent steps such as epitaxial growth are performed under the same pre-bake processing conditions.
[0098]
On the other hand, if r> 3.5, the prebake processing conditions are changed. The conditions are determined so as to satisfy 1 ≦ r ≦ 3.5.
[0099]
Specifically, the temperature and time are changed or the moisture and oxygen in the apparatus for performing the pre-bake treatment are reduced.
[0100]
Note that it is not necessary to perform the above-described evaluation for all the silicon wafers that are input, and it is sufficient to evaluate one or several to several to several hundred wafers. In particular, in a new apparatus, it is effective to perform a condition test for determining process conditions or a test after performing modification, repair, cleaning of a reaction vessel, or the like. Even when the quality of the obtained semiconductor substrate is abnormal, if the evaluation method of the present application is performed, the cause can be quickly extracted.
[0101]
In addition, haze value d after pre-baking treatment₁ D if it can be evaluated by itself₀ The measurement of can be omitted. FIG. 13B shows a series of systems for performing a pre-bake process based on the determined conditions and manufacturing a desired semiconductor substrate. Of course, before the epitaxial growth step, it is also preferable to measure whether or not pre-baking has been properly performed by measuring the haze value.
[0102]
Embodiment Example 2
FIG. 14 shows a method for forming a semiconductor substrate according to the present invention.
[0103]
As shown in FIG. 14A, a substrate 1 having a porous silicon layer 90 at least on the surface side is prepared. 2 is a hole and 3 is a hole wall.
[0104]
Next, as shown in FIG. 14B, a thin protective film 4 is formed on the hole wall 3 of the porous single crystal silicon layer as necessary (pre-oxidation step).
[0105]
Since the protective film 5 such as a silicon oxide film is formed on the surface of the porous silicon layer for the pre-oxidation, the protective film 5 on the surface of the porous silicon is removed by immersing it in a low concentration HF aqueous solution (HF). Dip process). FIG. 14 (c) schematically shows this cross section.
[0106]
Next, the substrate on which the porous single crystal silicon is formed is placed in an epitaxial growth apparatus, heat-treated (pre-baked) as shown in FIG. 14 (d), and then non-treated as shown in FIG. 14N (e). A porous single crystal layer 6 is formed.
[0107]
The pre-baking conditions are: the etching amount of the porous silicon layer, that is, the condition that the amount of decrease in the thickness (t) of the porous silicon layer is 2 nm or less, more preferably 1 nm or less (Condition 1), and the porous silicon layer The condition (condition 2) is that the change rate r of the haze value is 3.5 or less, more preferably 2.0 or less.
[0108]
The etching amount te is the thickness of the porous silicon layer before the start of heat treatment t₀ The thickness of the porous silicon layer at the end of the heat treatment is t₁ Te = t₀ -T₁ Can be expressed as The change rate r of the haze value is defined as the haze value of the eye starting heat treatment₀ , Haze value after heat treatment is d₁ When
[0109]
[Outside 2]

It can be expressed as
[0110]
The atmosphere during the heat treatment may be an atmosphere that does not contain a silicon-based gas, more preferably a reducing atmosphere that contains hydrogen. Further, it may be in an inert gas atmosphere or in an ultrahigh vacuum.
[0111]
This heat treatment will be described below.
[0112]
(1) Installation on equipment
A substrate having a porous silicon layer formed on the surface is placed in a reaction vessel in which the amount of residual oxygen and the amount of water are suppressed (not shown). The heat treatment used in the present invention can be functionally divided into two steps, a temperature raising step and a natural oxide film removing step. The natural oxide film here is a silicon oxide film that is unintentionally formed on the surface of the porous silicon layer after the HF dip process and a silicon oxide film that cannot be removed by the HF dip process. is there.
[0113]
The suppression of the etching amount is realized by suppressing the residual oxygen content and water content in the reaction vessel during the temperature raising step and the natural oxide film removal step. Residual oxygen content and water content in the reaction vessel are controlled not only by suppressing oxygen content and water content in the supply gas system, but also by carrying the substrate into and out of the reaction vessel through the load lock chamber. It is effective to prevent the inner surface of the reaction vessel from coming into direct contact with the atmosphere.
[0114]
It is also effective to install a purifier for hydrogen as a carrier gas near the apparatus as necessary. It is also desirable to increase the air tightness of the piping system and the container. By controlling these, as described above, the etching amount of the porous silicon layer in the two steps of the temperature raising step and the natural oxide film removal step can be maintained at least 2 nm or less, more preferably 1 nm or less. However, the method for suppressing the etching amount is not necessarily limited to the method described above.
[0115]
(2) Temperature rising process
After the substrate on which the porous silicon layer is formed is placed in the reaction vessel, the substrate is heated. When the reaction vessel is composed of a light transmissive material such as quartz material, the reaction vessel is heated by infrared lamp irradiation from the outside of the reaction vessel. In addition to lamp heating, there are induction heating by high frequency, resistance heating and the like. Examples of the reaction vessel material include quartz material, SiC, and stainless steel. The faster the temperature raising rate, the less the oxidation / etching due to residual moisture and oxygen content. Preferably, it is 1 ° C./sec or more, more preferably 5 ° C./sec or more.
[0116]
When carrying the substrate into the reaction vessel without passing through the load lock chamber, the substrate is carried in and then sufficiently purged to remove oxygen and moisture mixed in the vessel, and then the substrate is heated to rise. Let warm. In any case, it is desirable to perform in an ultra-high vacuum or non-oxidizing atmosphere.
[0117]
(3) Natural oxide film removal process
A natural oxide film removing step is performed following the temperature raising step. That is, the natural oxide film is removed by heat treatment in hydrogen, a reducing atmosphere containing hydrogen, or in ultra-high vacuum. At this time, the change rate r of the haze value on the surface of the porous silicon layer is 3. It is carried out under conditions that are within 5 and more preferably within 2. R is 1 or more.
[0118]
In order to realize the above conditions, the ultimate temperature during the heat treatment is preferably 850 ° C. or higher and 1000 ° C. or lower, and more preferably 870 ° C. or higher and 970 ° C. or lower.
[0119]
The pressure is not particularly limited, but is preferably atmospheric pressure or lower, preferably 700 Torr or lower, and more preferably 100 Torr or lower.
[0120]
The heat treatment time excluding the temperature raising step should be within 100 seconds, more preferably within 60 seconds, and even more preferably within 10 seconds.
[0121]
Natural oxide film is SiO₂ + Si-> 2SiO ↑
As a result of the reaction, desorption into the gas phase, if the natural oxide film is thick, the surface of the porous silicon layer and the silicon near the surface are etched.
[0122]
The natural oxide film is formed during washing with water after HF dipping, washing with water and drying, in the atmosphere until installation in the epitaxial growth apparatus, during installation in the epitaxial growth apparatus, and during the temperature raising step. In particular, if residual moisture / oxygen content remains during the temperature raising step, the silicon is oxidized to form a silicon oxide film in combination with an increase in temperature. As a result, the formed silicon oxide reacts with the adjacent silicon to etch the silicon.
[0123]
Further, the thicker the silicon oxide film formed during the temperature rise, the longer the heat treatment time required for completely removing the formed silicon oxide film. Such a long heat treatment time is not preferable because the structural change of the porous silicon surface proceeds as described later.
[0124]
In the present invention, the etching amount must be at least 2 nm or less, more preferably 1 nm or less. However, the small amount of silicon etching means that the degree of oxidation of silicon in the apparatus is small.
[0125]
If this heat treatment is continued, migration of surface atoms occurs on the surface of the porous silicon so as to smooth out minute roughness and lower the surface energy, and most of the pores on the surface disappear.
[0126]
In a load-lock type CVD epitaxial growth apparatus, a susceptor in which carbon is coated with CVD-SiC is heated in advance to 750 ° C. in a reaction vessel, and a silicon wafer on which porous silicon is formed is placed through a load lock. Then, under conditions of 600 Torr and hydrogen 43 (1 / min), the temperature was increased to 1100 degrees Celsius at 100 degrees / minute, held at 1100 degrees for 2 seconds, and then decreased to 750 degrees at 100 degrees / minute, When the wafer is taken out via the load lock, the porous surface holes are 10 holes having an average diameter of about 10 nm before the heat treatment.¹¹/ Cm² The hole density was 10⁶ / Cm² And the pore diameter expanded to 20-40 nm. Subsequent to the heat treatment described above under these conditions, if a single crystal silicon layer is epitaxially grown by adding a silicon source gas to hydrogen gas, the stacking fault density is 10^Four / Cm² It became. On the other hand, when the heat treatment at 1100 degrees was changed to 950 degrees and the holding time was equal to 2 seconds, the decrease in the hole density after the heat treatment was at most an order of magnitude. Moreover, the hole diameter hardly increased. After this heat treatment condition, if a single crystal silicon layer is epitaxially grown by adding a silicon source gas to hydrogen gas, the stacking fault density is 10² / Cm² Compared to the case of 1100 degrees, it was drastically reduced to 1/100.
[0127]
The crystal lattice on the surface of the porous silicon is distorted due to the stress acting between the porous silicon and the non-porous single crystal silicon substrate, but when the pore density decreases, this strain concentrates on the peripheral edge of the residual pores. Therefore, it is considered that crystal defects are likely to be introduced into the residual hole portion.
[0128]
In this method, the concentration of strain on the residual pores due to the decrease in pore density is prevented by starting the supply of silicon source gas to the porous silicon surface in the eyes where residual pores are reduced by heat treatment to remove the natural oxide film. This suppresses the introduction of crystal defects. This method can be realized for the first time by removing the heated natural oxide film with a very small etching amount of silicon.
[0129]
In particular, the present invention is a non-destructive method for managing the haze value introduced from the DC level of the scattered light in an apparatus for observing the intensity of the scattered light by injecting laser light into a substrate surface such as a commercially available foreign substance inspection apparatus. Simple process control and crystal defect density of 1000 / cm² Or less, more preferably 100 / cm² It suppresses to the following.
[0130]
For removal of the natural oxide film, other methods such as HF gas may be adopted or used as long as the etching amount of silicon is suppressed within the above-described range.
[0131]
In the present invention, the temperature raising step and the natural oxide film removing step are not particularly limited as long as the silicon etching is suppressed and a film is not formed by heat treatment on the porous surface. Or it is desirable to carry out in a hydrogen atmosphere.
[0132]
(4) Measurement of haze value
The measurement of the haze value is obtained by measuring the intensity of scattered light when parallel light such as laser light is incident on the substrate surface. If a foreign substance inspection apparatus using a commercially available laser beam is used, it can be easily measured. The wavelength of the laser light is preferably a short wavelength such as 488 nm of Ar laser. As the wavelength is shorter, the penetration length of light into the porous layer is shorter, so that the structural change in the vicinity of the surface of the porous layer that directly affects the crystallinity of the epitaxially grown layer can be detected sensitively. In addition, when the incident angle is large, that is, when the incident angle is shallow with respect to the substrate surface, the penetration depth into the porous layer is shortened, and measurement that is sensitive to structural changes in the vicinity of the surface becomes possible. .
[0133]
(5) Epitaxial growth
After passing through the heat treatment step (pre-bake), a source gas is supplied to close the porous holes, and a non-porous single crystal film is formed to a desired film thickness. Thus, a non-porous single crystal layer with a reduced stacking fault density can be formed on the porous silicon.
[0134]
The non-porous single crystal may be silicon epitaxially grown or SiGe, SiC, GaAs, InP, AlGaAs, GaN, etc. grown heteroepitaxially.
[0135]
(Porous silicon layer)
The porous Si used in the present invention is essentially the same as the porous silicon that has been studied up to the present since the discovery of Uhlir et al. In 1964, and is produced by a method such as anodization. However, as long as it is porous Si, the substrate is not limited to impurities, plane orientation, production method, and the like.
[0136]
In the case of forming porous silicon by anodization, the chemical conversion solution is water-soluble with hydrofluoric acid as a main component. During anodization, gas adheres to the electrode and silicon surface, and the porous layer tends to become non-uniform. Generally, an alcohol such as ethanol is added to increase the contact angle, and the attached bubbles. Is accelerated (Enhancement) so that chemical formation occurs uniformly. Of course, the porosity is formed without adding alcohol. When the porous silicon according to the present invention is used for the FIPOS method, the porosity is preferably around 56%, and when used for the bonding method, the low porosity (generally 50% or less, more preferably 30% or less) is suitable. is there. However, it is not limited to this.
[0137]
Since porous silicon is formed by etching as described above, in addition to the holes penetrating to the inside of the porous surface, the surface has shallow irregularities that can be observed from the surface with Field Emission Type Scanning Electron Microscope (FESEM). There are also shallower holes. The lower the porosity (Prosity (%)) of the porous silicon, the lower the stacking fault density on the porous body. Porous silicon having a low porosity can be realized, for example, by methods such as increasing the HF concentration during anodization, decreasing the current density, or increasing the temperature.
[0138]
In addition, the porous single crystal silicon layer may be formed by making only the main surface layer of the Si substrate porous or making the entire Si substrate porous.
[0139]
The porous layer is formed by implanting rare gas ions such as He, Ne, Ar or hydrogen ions into non-porous single-crystal silicon, and performing heat treatment as necessary, thereby forming microbubbles (microbubbles). ) Can be produced to make it porous. This is disclosed in Japanese Patent Laid-Open No. 5-211128.
[0140]
(Pre-oxidation)
In the present invention, a protective film may be formed on the pore wall of the porous silicon layer as necessary.
[0141]
Since the wall thickness between adjacent pores of porous silicon is very thin, several nanometers to several tens of nanometers, depending on the thermal growth after epitaxial growth, epitaxial growth layer, or heat treatment after bonding, Adjacent holes may be agglomerated and coarsened and further divided. This pore aggregation and coarsening phenomenon of the porous layer may lead to a decrease in the selective etching rate and deterioration of the selection ratio of the porous silicon. In FIPOS, the increase in the pore wall thickness and the division of the pores hinder the progress of oxidation of the porous layer, making it difficult to completely oxidize the porous layer. Therefore, after the porous layer is formed, a thin protective film is formed in advance on the pore wall by a method such as thermal oxidation to suppress pore aggregation and coarsening. When forming the protective film, it is essential to leave a region of single crystal silicon inside the hole wall, particularly when oxidation is performed. Therefore, a film thickness of several nm is sufficient.
[0142]
On the other hand, when an SOI substrate is manufactured by a bonding method, this step may be omitted if the subsequent process such as a heat treatment after the bonding is sufficiently performed at a low temperature and the porous structural change is suppressed. Is possible.
[0143]
(HF dip)
The pre-oxidized porous silicon layer can be subjected to HF dip treatment.
[0144]
Regarding HF dip, Sato et al. (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama, and T. Yonehara, Proc. Of the Seventh Int. Symp. On Silicon M. Sci. (Pennington, the Electrochem. Soc. Inc., 1994), p. 443), the stacking fault is reduced by increasing the HF dip time.^Three/ Cm²However, if the HF dip is applied for a long time as described above, the structure of the porous layer becomes coarse depending on the annealing temperature after bonding. Since a portion (etching residue) that is not formed may occur, it is desirable to control the HF dip time within an appropriate range.
[0145]
After HF dip, washing with water and drying can be performed to reduce the residual HF concentration in the porous pores.
[0146]
(Clogging of holes by supplying a small amount of raw material)
In the present invention, in the initial growth process of closing the porous holes, SiH₂Cl₂, SiH_Four, SiHCl_Three, SiCl_FourAnd Si₂H₆Using a silicon-based source gas such as 20 nm. / Min or less, more preferably 10 nm. / Min. Hereinafter, more preferably 2 nm / min. It is preferable to set the flow rate of the source gas so as to achieve the following growth rate. Silane which is a gas at normal temperature and normal pressure is more preferable from the viewpoint of controllability of the supply amount. This further reduces crystal defects. When Si is supplied from a solid source as in the MBE method and the substrate temperature is as low as 800 ° C. or less, the growth rate is desirably 0.1 nm / min or less. The growth rate is not particularly limited after the pores have been closed by a small amount of raw material supply step (sometimes referred to as “pre-injection”).
[0147]
The conditions may be the same as those for growth on normal bulk silicon. Or you may continue growing with the same growth rate as the above-mentioned trace amount raw material supply process, and even if it changes a gas seed | species etc., the requirements of this invention are not inhibited at all. Moreover, even if it is a continuous process with a trace amount raw material supply process, after interrupting supply of a raw material once, a desired raw material may be supplied again and it may be made to grow. Note that N. Sato et. al. Jpn. J. et al. Appl. Phys. 35 (1996) 973. Then, a small amount of SiH in the early stage of growth₂Cl₂It has been reported that the stacking fault density can be reduced by reducing the supply amount of the metal as compared with the conventional method. However, in such a method, the stacking fault density does not change in the tendency to be reduced by increasing the pre-epi pre-bake temperature, and the etching residue accompanying the coarsening of the porous layer as described above may occur. . In the present invention, the pre-growth heat treatment can be performed at about 950 ° C., which is lower than the conventional temperature, so that the porous structure is hardly coarsened.
[0148]
According to the embodiment of the present invention, a high temperature heat treatment is avoided as in the conventional method by installing a substrate having a porous silicon layer in an apparatus with a small amount of silicon etching and controlling the heat treatment time before growth. You can also. In this way, the crystal defect density can be reduced, and the porous structure can be coarsened and the pores can be prevented from being divided.
[0149]
In addition, since the growth temperature, pressure, gas flow rate, etc. can be controlled independently from the initial growth step, the processing temperature is lowered, the structure of the porous silicon is coarsened, or boron, phosphorus, etc. from the porous silicon are used. A thick non-porous single crystal silicon film may be formed in a short time by suppressing the auto-doping of impurities and solid phase diffusion, increasing the growth temperature, and increasing the flow rate of the silicon source gas to increase the growth rate. .
[0150]
The growing non-porous single crystal layer is not limited to silicon as described above, but may be a group IV heteroepitaxy material such as SiGe or SiC, or a compound semiconductor typified by GaAs. Absent. Further, in the trace material supply step, heteroepitaxial growth may be performed using a silicon-based gas and thereafter using another gas.
[0151]
In addition, after the step of sealing the pores on the surface of the porous layer (pre-baking, pre-injection) and before the growth of the desired film, the atmosphere is higher than the pre-baking and pre-injecting and does not contain the source gas of the semiconductor film (for example, It is also preferable to perform heat treatment in a reducing atmosphere containing hydrogen. This heat treatment is referred to as “inter baking”.
[0152]
Embodiment Example 3
An example in which a semiconductor substrate having a low defect density non-porous single crystal silicon layer on a porous single crystal silicon layer is applied will be described.
[0153]
A substrate 10 having a porous silicon layer 11 is produced by making at least one surface side portion of a single crystal Si substrate porous (FIG. 15A).
[0154]
A method similar to that shown in the embodiment example 2, that is, the etching amount of silicon is 2 nm or less (more preferably 1 nm or less), and the change rate r of the haze value of the porous silicon is within 3.5, ( More preferably, heat treatment (pre-bake) is performed (within 2) (FIG. 15B). Thereafter, a non-porous single crystal layer 12 is formed on the porous single crystal silicon layer (FIG. 15C).
[0155]
Prior to the heat treatment, the aforementioned pre-oxidation and HF dip may be performed. Furthermore, it is also preferable to close the holes by supplying a small amount of raw material (pre-injection) after the heat treatment.
[0156]
Next, an SOI substrate is manufactured by a bonding method. First, an insulating layer is formed on at least one of the main surfaces of the non-porous single crystal silicon and the second substrate, and then both the main surfaces are bonded to each other. A structure is formed (FIG. 15D). After performing a heat treatment for increasing the bonding strength as necessary, a step of removing the porous silicon by selective etching or the like (FIG. 15E), the epitaxial growth layer on the porous silicon is formed on the second substrate. If moved up, an SOI structure can be obtained.
[0157]
If the bonding strength is sufficient to withstand the subsequent process, the process proceeds to the subsequent process. The porous layer is exposed by removing the back side of the substrate on which the porous layer has been formed by a mechanical method such as grinding or a chemical method such as etching. Alternatively, the porous layer may be exposed by peeling (separating) 15 non-porous portions of the substrate 10 from the multilayer structure with the porous layer as a boundary. Peeling may be performed mechanically by inserting a wedge or the like from the end face or by spraying a fluid like a water jet, or may utilize ultrasonic waves, thermal stress, or the like. It is preferable that a high porosity layer having a low mechanical strength is partially formed in the porous layer in advance to facilitate separation. For example, the structure of the porous layer 11 is changed from the non-porous single crystal layer 12 side to the first porous layer (porosity of 10% to 30%), and below the second porous layer (30% -70% porosity).
[0158]
(Porous selective etching)
The porous layer remaining on the non-porous single crystal layer 12 is removed by selective etching. Selective etchants are HF and H₂O₂, H₂O₂The mixed solution is preferably used. In order to remove bubbles generated during the reaction, ethyl alcohol, isopropyl alcohol or a surfactant may be added to the mixed solution.
[0159]
In this method, since the structural change / coarseness of the porous layer and the fragmentation of the pores are suppressed, there is little deterioration in selectivity in selective etching.
[0160]
Note that the second substrate on which the non-porous single crystal silicon layer formed on the porous silicon is bonded is not particularly limited. The silicon wafer, the silicon wafer formed with a thermally oxidized silicon film, the transparent substrate such as quartz wafer, the sapphire wafer, etc. If you do. The insulating layer 14 can be omitted when the insulating substrate is bonded.
[0161]
In addition, the non-porous single crystal silicon layer may be formed as it is before the second substrate is bonded even when the second substrate is bonded as it is. The film to be formed may be formed by forming a single crystal film such as SiGe, SiC, III-V compound or II-VI compound in addition to silicon oxide or silicon nitride, or by laminating a plurality of these films. It may be a thing.
[0162]
Before bonding, it is preferable to clean the bonding surface cleanly. For the cleaning, a preceding process used in a normal semiconductor process may be adopted. In addition, the adhesive strength can be increased by irradiating nitrogen plasma or the like before bonding.
[0163]
After the bonding, it is desirable to increase the bonding strength by performing a heat treatment.
[0164]
(Hydrogen annealing)
There are irregularities reflecting the period of the pores and side walls of the surface porous silicon after the removal of the porous silicon. This is because this surface corresponds to the interface between non-porous single crystal silicon and porous silicon, but both are single crystal silicon in the first place, and only the difference is whether or not there is a hole. This surface unevenness can be removed by polishing or the like, but if heat treatment is performed in a hydrogen atmosphere, the unevenness can be removed without substantially reducing the film thickness of the non-porous single crystal silicon. Hydrogen annealing can be performed under atmospheric pressure, high pressure, or slightly reduced pressure.
[0165]
The annealing temperature is from 800 ° C. to the melting point of silicon, more preferably from 900 ° C. to 1350 ° C.
[0166]
(Boron concentration control)
On the other hand, the crystallinity of the epitaxial layer on porous silicon is generally P⁺Si (^-0.01Ω · cm boron doped) is more porous.^-Si (^-Although it is far better than the case of forming 0.01 Ω · cm boron doped), high concentration Boron may diffuse into the epitaxial silicon layer by autodoping or solid phase diffusion during epitaxial growth. Boron diffused in the epitaxial silicon layer remains after the removal of the porous silicon, which may hinder the suppression of the impurity concentration of the active layer in the SOI. In order to solve this problem, by annealing a substrate having an SOI structure completed by Sato et al. (N. Sato, and T. Yonehara, Appl. Phys. Lett. 65 (1994) p. 1924) in hydrogen, The concentration is reduced by removing the natural oxide film on the surface of the SOI layer having a low diffusion rate and diffusing boron in the SOI layer to the outside. However, excessive boron diffusion into the epitaxial silicon layer leads to boron incorporation into the buried oxide film, resulting in prolonged hydrogen annealing, increased process costs, or controllability of the boron concentration in the buried oxide film. There were cases where problems such as deterioration occurred. In order to solve this problem, it is effective to suppress the diffusion of boron, for example, by lowering the conditions for forming the epitaxial silicon layer. According to the present invention, the conditions for forming the epitaxial silicon layer can be set independently of the blockage of the holes, so that appropriate conditions can be set.
[0167]
(FIPOS method)
The SOI structure may be formed by selectively oxidizing the porous silicon by an oxidation process after partially removing the epitaxial growth layer by the FIPOS method without performing the Mataha bonding process. In this method, since the structural change / coarseness of the porous layer and the fragmentation of the pores are suppressed, there is little deterioration in selectivity even in the selective oxidation.
[0168]
(Heteroepitaxy)
Alternatively, a compound semiconductor such as GaAs, or a group IV hetero-epi such as SiC or SiGe may be performed. In heteroepitaxy, porous silicon acts as a stress buffering material, which can relieve stress due to lattice mismatch and reduce the crystal defect density of the non-porous single crystal silicon layer. The defect density of the epitaxial growth layer is also reduced. In this method, since the structural change / coarseness of the porous layer and the fragmentation of the pores are suppressed, the deterioration of the stress buffering effect is small.
[0169]
(Other applications)
Since porous silicon has a gettering action, a process can be performed by directly forming a MOS transistor, a bipolar transistor, or the like on a non-porous single-crystal silicon layer manufactured according to the present invention without forming an SOI structure as described above. The substrate is highly resistant to impurity contamination such as metal contamination.
[0170]
Compared with the conventional method, this method can lower the heat treatment temperature, particularly the heat treatment temperature before sealing the pores, so that the aggregation / expansion of the pores in the porous layer, the division, etc. can be suppressed. The selectivity in the selective etching of the porous layer in the subsequent process is not deteriorated. That is, the crystallinity of the non-porous single crystal silicon layer can be improved without generating a residue in removing the porous layer. Further, in the FIPOS method, the oxidation rate of selective oxidation of the porous layer is not deteriorated.
[0171]
Hereinafter, specific examples of the present invention will be described.
[0172]
(Example 1-950 ° C., 600 Torr Prebake (2 s, 120 s), Preinjection, Epi-2 μm)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-CZ 6 inch (100) p made 0.005Ω · cm⁺A silicon wafer was prepared.
[0173]
2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is connected to another p through the same solution.⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to energize. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, a current was passed for 12 minutes to anodize the silicon wafer, and 12 μm thick porous silicon was formed on the surface.
[0174]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere. Since this oxidation treatment forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and the single crystal silicon region remains inside.
[0175]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to remove the ultrathin silicon oxide film formed on the surface of the porous layer as an overflow rinse. did.
[0176]
5) Then, as a pre-baking step, heat treatment was performed at 1100 ° C. for 120 seconds.
[0177]
The haze value immediately before pre-baking was 9.1 ppm, and the haze value after pre-baking was 34.5 ppm. That is, r = 3.8 (> 3.5).
[0178]
Therefore, when the heat treatment conditions were varied so that the change rate r of the haze value satisfies 1 ≦ r ≦ 3.5, when the heat treatment was performed at 950 ° C. for 120 seconds, the change rate r of the haze value was It was found to be 2.8 (<3.5).
[0179]
After pre-baking under the condition of r = 2.8, SiH was added to hydrogen carrier gas so as to have a concentration of 28 ppm at a pressure of 600 Torr in the same reaction vessel._FourFor 200 seconds and SiH_FourAfter that, the pressure was lowered to 80 Torr, the temperature was lowered to 900 ° C., and this time, SiH₂Cl₂Was added to a concentration of 0.5 mol% to form a non-porous single crystal silicon film having a thickness of 2 μm. The wafer was then subjected to defect revealing etching to reveal crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 99% or more of stacking faults. The density of stacking faults is 160 / cm²Met.
[0180]
On the other hand, when the rate of change haze value r = 3.8, epitaxial growth under the same conditions results in a stacking fault density of 1.5 × 10 5.^Four/ Cm²I found out that From the above, it was confirmed that a single-crystal Si layer having a very low stacking fault density can be formed by performing pre-baking under conditions where the haze value is within a certain range.
[0181]
Note that the stacking fault was observed with a microscope after performing defect revealing etching. Specifically, as an etchant, K in the Secco etching method is used.₂Cr₂O₇In order to reduce the etching rate, a mixed aqueous solution of (0.15M) and 49% -HF (2: 1) was diluted with pure water and introduced into the non-porous single crystal silicon layer on the wafer surface. After revealing the crystal defects, the stacking fault density was determined by observation with a Nomarski differential interference microscope.
[0182]
(Example 2-950 ° C., 600 Torr Prebake (2 s, 120 s), Preinjection, Epi-2 μm)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-CZ 6 inch (100) p made 0.005Ω · cm⁺A silicon wafer was prepared.
[0183]
2) In a solution in which a 49% HF aqueous solution and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is connected to another p through the same solution.⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to conduct. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, the silicon wafer was anodized by supplying a current for 12 minutes to form 12 μm thick porous silicon on the surface.
[0184]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere.
[0185]
Since this oxidation process forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side wall of the hole, and the region of single crystal silicon is left inside. .
[0186]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to remove the ultrathin silicon oxide film formed on the surface of the porous layer as an overflow rinse. did.
[0187]
5) The wafer is placed in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed and set, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected to each other. Installed.
[0188]
After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂Gas was flowed to 80 Torr. Transfer chamber is N in advance.₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0189]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0190]
6) After setting the pressure in the process chamber to 600 Torr, the wafer transferred on the susceptor was heated with an IR lamp to increase the temperature at a rate of 100 ° C. per minute, held at 950 ° C. for 2 seconds, The temperature was lowered to 750 ° C., and the wafer was again taken out to the load lock chamber via the transfer chamber by the transfer robot. The other wafer was held at 950 ° C. for 120 seconds, and the other processes were performed in the same manner as the wafer described above and returned to the load lock chamber.
[0191]
7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and when the haze on the surface of the porous layer was observed with a foreign substance inspection apparatus, the average haze value of the porous material on the wafer treated for 2 seconds was 11.9 ppm. The haze value of the porous material treated for 120 seconds was 25.7, which was about 1.3 and 2.8 times the haze value of 9.1 ppm of the sample before being installed in the epitaxial growth apparatus, respectively. That is, r = 1.3, 2.8.
[0192]
8) In addition, after preparing the SOI substrate prepared in advance by HF dipping, washing with water and drying, the film thickness of the SOI layer is measured with an optical interference film thickness meter, and the processing of 5) and 6) is performed. , Removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm.
[0193]
9) The wafer having undergone the process of 4) was transferred to the process chamber of the epitaxial growth apparatus by the method described in 5).
[0194]
10) After setting the pressure in the process chamber to 600 Torr, the wafer transferred on the susceptor is heated with an IR lamp to raise the temperature at a rate of 100 ° C. per minute, and as a heat treatment (pre-bake treatment) at 950 ° C. for 2 seconds. After being held, SiH is added to the hydrogen carrier gas so that the concentration becomes 28 ppm._FourAnd treated for 200 seconds, SiH_FourAfter that, the pressure was lowered to 80 Torr, the temperature was lowered to 900 ° C., and this time, SiH₂Cl₂Is added to a concentration of 0.5 mol% to form a non-porous single crystal silicon film of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is transferred to the transfer chamber again by the transfer robot. It was taken out to the load lock room via. The other wafer was pre-baked in a hydrogen atmosphere at 950 ° C. for 120 seconds, and the other processes were the same and returned to the load lock chamber. In addition, the concentration of 28 ppm SiH_FourWhen gas is added, the growth rate is 3.3 nm / min.
[0195]
11) The wafer after the processing of 10) was subjected to defect revealing etching to reveal crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 99% or more of stacking faults. The density of stacking faults is 84 / cm in the case of pre-baking for 2 seconds.²In the case of 60 seconds of pre-baking, 160 pieces / cm²In the case of pre-baking at 1100 ° C. for 120 seconds, 1.5 × 10^Four/ Cm²Compared to, it decreased sharply. Especially when prebaked at 950 ° C for 2 seconds, 100 pieces / cm²A stacking fault density of less than 5 was obtained.
[0196]
(Example 3-950 ° C., 600 Torr Prebake (2e), Preinjection, Epi-0.32 μm ELTRAN)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-CΩ 8 inches (100) p with 0.01 Ω · cm⁺A silicon wafer was prepared.
[0197]
2) In a solution in which a 49% HF aqueous solution and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is passed through the same solution with another p⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to conduct. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, the silicon wafer was anodized by flowing an electric current for 12 minutes to form a plurality of 12 μm thick porous silicon on the surface.
[0198]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in an oxygen atmosphere at 400 degrees. Since this oxidation treatment forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side wall of the hole, and the single crystal silicon region remains inside.
[0199]
4) The ultrathin silicon oxide film formed on the surface of the porous layer by exposing the wafer to an aqueous HF solution diluted to 1.25% for about 30 seconds, then immersing in pure water for 10 minutes, overflow rinsing, and Was removed.
[0200]
5) Place the wafer in the wafer carrier in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed in the wafer carrier, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected. Installed. After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr. Transfer chamber is N in advance₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0201]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0202]
6) The wafer transferred on the susceptor was heated with an IR lamp and heated at a rate of 100 ° C. per minute, and kept at 950 ° C. for 2 seconds as a pre-bake process. The haze change rate r was 1.3.
[0203]
Next, SiH is used as a hydrogen carrier gas so that the concentration becomes 28 ppm._FourCl₂For 200 seconds, and SiH_FourIs completed, and then the temperature is lowered to 900 ° C., this time SiH_FourCl₂Is added to a concentration of 0.5 mol% to form a non-porous single crystal silicon film of 0.32 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is again transferred by the transfer robot. It was taken out into the load lock chamber via the chamber. The film thickness of the formed non-porous single crystal silicon layer was 0.32 μm on average and the maximum value−minimum value = 8 nm.
[0204]
7) A wafer obtained by epitaxially growing nonporous single crystal silicon is placed in a vertical furnace, and the nonporous single crystal is heat-treated at 1000 ° C. in a mixture of water vapor and residual oxygen formed by burning oxygen and hydrogen. The silicon surface was oxidized to form a 208 nm silicon oxide film.
[0205]
8) After the above wafer and the second silicon wafer are cleaned cleanly by a silicon semiconductor process cleaning line, the first main surfaces of both wafers are gently overlapped and the center is pressed. did.
[0206]
9) Subsequently, the integrated wafer set was placed in a vertical furnace and heat-treated at 1100 ° C. for 1 hour in an oxygen atmosphere.
[0207]
10) The back side of the wafer on which the porous silicon was formed was ground with a grinder: the porous silicon was exposed over the entire surface of the wafer.
[0208]
11) When the exposed porous silicon layer is dipped in a mixed solution of HF and hydrogen peroxide solution, all the porous silicon is removed in about 2 hours, and the non-porous single crystal silicon layer and the thermally oxidized silicon are formed on the entire surface of the wafer. Interference color due to the film was observed.
[0209]
12) After the processing in 11) is completed, the wafer is cleaned in a cleaning line generally used in a silicon semiconductor device process, and then placed in a vertical hydrogen annealing furnace to perform heat treatment at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere. It was. Hydrogen gas is purified by a commercially available hydrogen refining device using a palladium alloy connected to the device by an internally polished stainless steel pipe of about 7 m.
[0210]
13) Thus, an SOI structure wafer was fabricated in which a 200 nm silicon oxide layer and a 200 nm single crystal silicon layer were stacked on the second silicon wafer.
[0211]
The average thickness of the single crystal silicon layer was 201 nm, and the maximum value−minimum value = 8 nm.
[0212]
14) After removing the single crystal silicon layer by 130 nm by defect revealing etching, the wafer was immersed in 49% HF for 3 minutes. As a result, the buried oxide film is etched by HF from the portion of the crystal defect remaining in the single crystal silicon layer etched by the defect revealing etching, and the defect density can be easily measured with a Nomarski differential interference microscope. The observed defect density is 64 / cm.²Met. Due to the hydrogen annealing treatment, stacking faults introduced into the non-porous single crystal silicon layer were reduced. Defect density 100 / cm²And a thin film SOI layer having a uniform film thickness was obtained.
[0213]
(Example 4-950 ° C., 600 Torr Prebake (2s, 120s), No Preinjection, Epi-2 μm)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-0.005 Ω · cm, 6 inches (100) p⁺A silicon wafer (CZ wafer) was prepared.
[0214]
2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is connected to another p through the same solution.⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to conduct. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, the silicon wafer was anodized by applying an electric current for 12 minutes to form 12 μm thick porous silicon on the surface.
[0215]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere. Since this oxidation treatment forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and the single crystal silicon region remains inside.
[0216]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and an ultrathin silicon oxide film formed on the surface of the porous layer is formed. Removed.
[0217]
5) Place the wafer in the wafer carrier in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed in the wafer carrier, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected. Installed.
[0218]
After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr.
[0219]
Transfer chamber is N in advance₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0220]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0221]
6) After setting the pressure of the process chamber to 600 Torr, the wafer transferred on the susceptor is heated with an IR lamp to raise the temperature at a rate of 100 ° C. per minute, and kept at 950 ° C. for 2 seconds. The temperature was lowered to 750 ° C., and the wafer was again taken out to the load lock chamber via the transfer chamber by the transfer robot. The other wafer was held at 950 ° C. for 60 seconds, and the other processes were performed in the same manner and returned to the load lock chamber.
[0222]
7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze value of the porous layer surface was measured with a foreign substance inspection device. The average haze value of the porous surface on the wafer treated for 2 seconds was 11.9. Yes, the haze value of the porous material treated for 60 seconds was 16.3, which was about 1.3 and 1.8 times the haze value 9.1 of the sample before being installed in the epitaxial growth apparatus, respectively.
[0223]
8) In addition, dip the SOI substrate prepared in advance, wash it with water, dry it, measure the film thickness of the SOI layer with an optical interference film thickness meter, and perform the processing 5) and 6). , Removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm.
[0224]
9) The wafer having undergone the process of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).
[0225]
10) After setting the pressure in the process chamber to 600 Torr, the wafer transferred on the susceptor was heated with an IR lamp to raise the temperature at a rate of 100 ° C. per minute, and maintained at 950 ° C. for 2 seconds as a pre-bake treatment. The temperature is lowered to 900 ° C., the pressure is 80 Torr, SiH₂Cl₂Is added to a concentration of 0.5 mol% to form a non-porous single crystal silicon film of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is transferred to the transfer chamber again by the transfer robot. It was taken out to the load lock room via. The other wafer was subjected to a pre-bake treatment time in a hydrogen atmosphere at 950 ° C. for 60 seconds, and the other treatments were the same and returned to the load lock chamber.
[0226]
11) The wafer after the processing of 10) was subjected to defect revealing etching to reveal crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 99% or more of stacking faults. The density of stacking faults is 170 / cm in the case of pre-baking for 2 seconds.²270 pieces / cm for 60 seconds of pre-baking²In the case of pre-baking at 1100 ° C. for 120 seconds, 1.5 × 10^Four/ Cm²Compared to, it decreased sharply.
[0227]
(Example 5-900 ° C., 450 Torr Prebake (2 s, 120 s), Preinjection, Epi-2 μm)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-6 inches (100) p with 0.005 Ω · cm⁺A silicon wafer (CZ wafer) was prepared.
[0228]
2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is connected to another p through the same solution.⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to conduct. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, the silicon wafer was anodized by applying an electric current for 12 minutes to form 12 μm thick porous silicon on the surface.
[0229]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere. Since this oxidation treatment forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side walls of the holes, and the single crystal silicon region remains inside.
[0230]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and an ultrathin silicon oxide film formed on the surface of the porous layer is formed. Removed.
[0231]
5) Place the wafer in the wafer carrier in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed in the wafer carrier, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected. Installed. After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr. Transfer chamber is N in advance₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0232]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0233]
6) After setting the pressure in the process chamber to 450 Torr, the wafer transferred on the susceptor is heated with an IR lamp to raise the temperature at a rate of 100 ° C. per minute, and held at 900 ° C. for 2 seconds. The temperature was lowered to 750 ° C., and the wafer was again taken out to the load lock chamber via the transfer chamber by the transfer robot. The other wafer was held at 900 ° C. for 120 seconds, and the other processes were the same and returned to the load lock chamber.
[0234]
7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze value on the surface of the porous layer was measured with a foreign substance inspection device. The average haze value of the porous material on the 2-second treated wafer was 12.1. The average haze value of the porous material treated for 60 seconds was 14.3, which was about 1.3 and 1.6 times the average haze value 9.2 of the sample before being installed in the epitaxial growth apparatus, respectively.
[0235]
8) In addition, dip the SOI substrate prepared in advance, wash it with water, dry it, measure the film thickness of the SOI layer with an optical interference film thickness meter, and perform the processing 5) and 6). , Removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm.
[0236]
9) The wafer having undergone the process of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).
[0237]
10) After setting the pressure in the process chamber to 450 Torr, the wafer transferred on the susceptor was heated with an IR lamp to raise the temperature at a rate of 100 ° C. per minute, and maintained at 900 ° C. for 2 seconds as a pre-bake treatment. SiH into the hydrogen carrier gas to a concentration of 28 ppm_FourFor 200 seconds, and SiH_FourAfter that, the pressure was lowered to 80 Torr, the temperature was lowered to 900 ° C., and this time, SiH₂Cl₂Is added to a concentration of 0.7 mol% to form a non-porous single crystal silicon film having a thickness of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is transferred again to the transfer chamber by a transfer robot. It was taken out to the load lock room. The pre-baking process time in another wafer at 900 ° C. in a hydrogen atmosphere was set to 60 seconds, and the other processes were the same and returned to the load lock chamber.
[0238]
11) The wafer after the processing of 10) was subjected to defect revealing etching to reveal crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 99% or more of stacking faults. The density of stacking faults is 350 / cm in the case of pre-baking for 2 seconds.²In the case of 60 seconds of pre-baking, 400 pieces / cm²In the case of pre-baking at 1100 ° C. for 120 seconds, 1.5 × 10^Four/ Cm²1000 pieces / cm²Less than defect density was realized.
[0239]
(Example 6-870 ° C., 80 Torr Prebake (5 s, 60 s), Preinjection, Epi-2 μm)
1) Addition of boron as a p-type impurity and a specific resistance of 0.015 Ω · cm⁺/^-6 inches (100) p with 0.005 Ω · cm⁺A silicon wafer (CZ wafer) was prepared.
[0240]
2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was placed as an anode and a 6-inch diameter platinum plate was placed as a cathode so as to face the silicon wafer. The back side of the silicon wafer is connected to another p through the same solution.⁺The front surface of the Si wafer was opposed, and the 6-inch diameter platinum plate was opposed to the outermost wafer. The solution between the wafers was separated by the wafer and was placed so as not to conduct. A current density of 10 mA / cm between the silicon wafer and platinum.²Then, the silicon wafer was anodized by applying an electric current for 12 minutes to form 12 μm thick porous silicon on the surface.
[0241]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere. Since this oxidation treatment generally forms only an oxide film of 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side wall of the hole, and the single crystal silicon region remains inside.
[0242]
4) The wafer is exposed to an aqueous HF solution diluted to 1.3% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and an ultrathin silicon oxide film formed on the surface of the porous layer is formed. Removed.
[0243]
5) Place the wafer in the wafer carrier in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed in the wafer carrier, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected. Installed. After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr. Transfer chamber is N in advance₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0244]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0245]
6) The pressure of the process chamber is 80 Torr, the wafer transferred on the susceptor is heated with an IR lamp, heated at a rate of 100 ° C. per minute, held at 870 ° C. for 5 seconds, and then the temperature is increased to 750 ° C. The temperature was lowered, and the wafer was taken out again by the transfer robot into the load lock chamber via the transfer chamber. The other wafer was held at 860 ° C. for 60 seconds, and the other processes were the same and returned to the load lock chamber.
[0246]
7) The load lock chamber was opened to the atmosphere, the wafer was taken out, and the haze value on the surface of the porous layer was measured with a surf scan 6420 obliquely incident with an argon laser having a wavelength of 488 nm as a commercially available foreign matter inspection apparatus. The average haze value of the porous material on the wafer is 10.2, the average haze value of the porous material after 30 seconds treatment is 19.5, and the average haze value of the sample before installation in the epitaxial growth apparatus is about 8.5. 1.2 and 2.3 times.
[0247]
8) In addition, after preparing the SOI substrate prepared in advance by HF dipping, washing with water and drying, the film thickness of the SOI layer is measured with an optical interference film thickness meter, and the processing of 5) and 6) is performed. , Removed from the load lock. When the thickness of the SOI layer was measured again, the amount of decrease in the thickness of the SOI layer was less than 1 nm.
[0248]
9) The wafer having undergone the process of 4) was transferred to the process chamber of the epitaxial growth apparatus according to 5).
[0249]
10) After setting the pressure in the process chamber to 80 Torr, the wafer transferred on the susceptor was heated with an IR lamp and heated at a rate of 100 ° C. per minute, and held at 860 ° C. for 2 seconds as a pre-bake treatment. SiH into the hydrogen carrier gas to a concentration of 35 ppm_FourAnd treated for 150 seconds, SiH_FourIs finished, and then SiH₂Cl₂Is added to a concentration of 1 mol% to form a non-porous single crystal silicon film having a thickness of 2 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is again transferred by the transfer robot via the transfer chamber. Removed to load lock chamber. The other wafer was subjected to a pre-baking process time of 60 seconds, and the other processes were the same and returned to the load lock chamber.
[0250]
11) The wafer after the processing of 10) was subjected to defect revealing etching to reveal crystal defects introduced into the non-porous single crystal silicon layer, and then observed with a Nomarski differential interference microscope. The observed defects were 99% or more of stacking faults. The density of stacking faults is 120 / cm in the case of pre-baking for 5 seconds.²In the case of 30 seconds pre-baking, 430 pieces / cm²In the case of pre-baking at 1100 ° C. for 120 seconds, 1.5 × 10^Four/ Cm²1000 pieces / cm²Less than defect density was realized.
[0251]
(Example 7-950 ° C., Prebake (2 s), Preinjection, Epi-0.32 μm)
1) Boron is added as a p-type impurity, and the specific resistance value is 0.015 Ω · cm.⁺/^-8-inch plane orientation (100) p of 0.01 Ω · cm⁺A silicon wafer (CZ wafer) was prepared.
[0252]
2) The surface layer of the first single crystal Si substrate was anodized in an HF solution.
[0253]
The anodizing conditions were as follows.
[0254]
Current density: 7 (min)
Anodizing solution: HF: H₂O: C₂H_FiveOH = 1: 1: 1
Time: 5 (mA · cm^-2)
Thickness of porous Si: 5 (μm)
further,
Current density: 50 (mA · cm^-2)
Anodizing solution: HF: H₂O: C₂H_FiveOH = 1: 1: 1
Time: 10 (sec)
Porous Si thickness: ~ 0.2 (μm)
50 (mA · cm^-2), The porosity of the porous Si layer was increased, and a structurally fragile high-porosity thin layer was formed. That is, a low-porosity porous layer and a high-porosity porous layer were formed in this order from the surface side of the silicon wafer.
[0255]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to oxidation treatment (pre-oxidation) for 1 hour in a 400 ° oxygen atmosphere. Since this oxidation treatment forms only an oxide film of approximately 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side wall of the hole, and the single crystal silicon region remains inside.
[0256]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, and then immersed in pure water for 10 minutes to remove the ultrathin silicon oxide film formed on the surface of the porous layer as an overflow rinse. did.
[0257]
5) The wafer is placed in a load lock chamber of an epitaxial CVD growth apparatus in which a load lock chamber for setting a wafer in a wafer carrier, a transfer chamber in which a wafer transfer robot is set, and a process chamber are connected. Placed in a wafer carrier.
[0258]
After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr.
[0259]
Transfer chamber is N in advance.₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0260]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0261]
6) The wafer transferred on the susceptor is heated with an IR lamp and heated at a rate of 100 ° C. per minute, held at 950 ° C. for 2 seconds as a heat treatment (prebake treatment), and then hydrogenated to a concentration of 28 ppm. SiH as carrier gas_FourFor 200 seconds, and SiH_FourIs completed, and then the temperature is lowered to 900 ° C., this time SiH₂Cl₂Is added to a concentration of 0.5 mol%, a non-porous single crystal silicon film is formed to 0.32 μm, the temperature is lowered to 750 ° C. in a hydrogen atmosphere, and the wafer is again transferred to the transfer chamber by the transfer robot. To the load lock chamber. The film thickness of the formed non-porous single crystal silicon layer was 0.32 μm on average and maximum value−minimum value = 8 nm. In addition, it was 11.4 after heat processing with respect to haze value 9.5 before heat processing. That is, r = 1.2.
[0262]
In addition, the prepared SOI substrate is dipped in HF, washed with water and dried, and then the thickness of the SOI layer is measured with an optical interference type film thickness meter and subjected to the processing of 5) and 6), and loaded. Removed from the lock. When the film thickness of the SOI layer was measured again, the amount of decrease in the film thickness of the SOI layer was less than 1 nm.
[0263]
7) A wafer obtained by epitaxially growing nonporous single crystal silicon is placed in a vertical furnace, and the nonporous single crystal is heat-treated at 1000 ° C. in a mixture of water vapor and residual oxygen formed by burning oxygen and hydrogen. The silicon surface was oxidized to form a 208 nm silicon oxide film.
[0264]
8) After the above wafer and the second silicon wafer are cleaned cleanly by a silicon semiconductor process cleaning line, the first main surfaces of both wafers are gently overlapped and the center is pressed. did.
[0265]
9) Subsequently, the integrated wafer set was placed in a vertical furnace and processed at 1100 ° C. for 1 hour in an oxygen atmosphere.
[0266]
10) When a water jet was sprayed on the side surface of the bonded wafer, the high porosity layer was cracked and divided. In addition to the water jet, the dividing method is a method of applying external pressure such as pressurization, tension, shear, wedge, etc., a method of applying ultrasonic waves, a method of applying heat, and the porous Si is expanded from the periphery by oxidation to be in the porous Si. There are a method of applying an internal pressure to the material, a method of heating in pulses, applying a thermal stress, or a method of softening. It is possible to separate by any method.
[0267]
11) When a second silicon wafer having an exposed porous silicon layer on the surface is dipped in a mixed solution of HF and hydrogen peroxide solution, all the porous silicon is removed in about 2 hours. Interference colors due to the porous single crystal silicon layer and the thermally oxidized silicon film were observed.
[0268]
12) After the processing in 11) is completed, the wafer is cleaned in a cleaning line generally used in a silicon semiconductor device process, and then placed in a vertical hydrogen annealing furnace to perform heat treatment at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere. It was. Hydrogen gas is purified by a commercially available hydrogen refining device using a palladium alloy connected to the device by an internally polished stainless steel pipe of about 7 m.
[0269]
13) Thus, an SOI structure wafer was fabricated in which a 200 nm silicon oxide layer and a 200 nm single crystal silicon layer were stacked on the second silicon wafer.
[0270]
The average thickness of the single crystal silicon layer was 201 nm, and the difference between the maximum value and the minimum value was 8 nm.
[0271]
14) After removing the single crystal silicon layer by 130 nm by the defect revealing etching of the wafer of 13), the wafer was immersed in 49% HF for 3 minutes. As a result, the buried oxide film is etched by HF from the portion of the crystal defect remaining in the single crystal silicon layer etched by the defect revealing etching, and the defect density can be easily measured with a Nomarski differential interference microscope. The observed defect density is 64 / cm.²Met. Due to the hydrogen annealing treatment, stacking faults introduced into the non-porous single crystal silicon layer were reduced. Defect density 100 / cm²And a thin film SOI layer having a uniform film thickness was obtained.
[0272]
(Example 8-950 ° C., 80 Torr Prebake (2 s), Preinjection, Epi-0.01 μm Hetero-epitaxy)
1) Anodizing four p-type or n-type (100) single crystal Si substrates having a specific resistance of 0.01 Ω · cm having a thickness of 615 μm in a solution diluted with HF alcohol, A porous Si layer was formed on one main surface which is the mirror surface.
[0273]
2) The anodizing conditions were as follows.
[0274]
Current density: 7 mA / cm²
Anodizing solution: HF: H₂O: C₂H_FiveOH = 1: 1: 1
Time: 12 minutes
The thickness of the porous Si layer: 10 μm
Porosity: 20%
[0275]
3) Subsequently, the wafer on which the porous silicon layer was formed was subjected to an oxidation treatment for 1 hour in a 400 degree oxygen atmosphere. Since this oxidation treatment generally forms only an oxide film of 50 mm or less, the silicon oxide film is formed only on the surface of the porous silicon and the side wall of the hole, and the single crystal silicon region remains inside.
[0276]
4) The wafer is exposed to an aqueous HF solution diluted to 1.25% for about 30 seconds, then immersed in pure water for 10 minutes, overflow rinsed, and an ultrathin silicon oxide film formed on the surface of the porous layer is formed. Removed.
[0277]
5) Place the wafer in the wafer carrier in the load lock chamber of the epitaxial CVD growth apparatus in which the load lock chamber in which the wafer is placed in the wafer carrier, the transfer chamber in which the wafer transfer robot is set, and the process chamber are connected. Installed. After depressurizing the load lock chamber from atmospheric pressure to 1 Torr or less with a dry pump, N₂To 80 Torr. Transfer chamber is N in advance₂And is held at 80 Torr. In the process chamber, a susceptor in which carbon is coated with CVD-SiC is installed to hold a wafer. The susceptor is heated to about 750 ° C. by an IR lamp in advance. In the process chamber, purified hydrogen gas is supplied to the process chamber by a stainless steel pipe whose inner surface is polished about 10 m from the refiner by a hydrogen purifier using a heated palladium alloy.
[0278]
The wafer was transferred from the load lock chamber to the process chamber via the transfer chamber by the transfer robot and placed on the susceptor.
[0279]
6) The wafer transferred on the susceptor is heated with an IR lamp and heated at a rate of 100 ° C. per minute, held at 950 ° C. for 2 seconds as a heat treatment (prebake treatment), and then hydrogenated to a concentration of 28 ppm. SiH as carrier gas_FourFor 200 seconds, and SiH_FourThen, the temperature was lowered to 750 ° C. in a hydrogen atmosphere, and the wafer was again taken out to the load lock chamber via the transfer chamber by the transfer robot. The film thickness of the formed non-porous single crystal silicon layer was 0.03 μm on average. In addition, it was 11.2 after heat processing with respect to the haze value 8.5 before heat processing.
[0280]
Single crystal GaAs was epitaxially grown on the porous Si to a thickness of 1 μm by MOCVD (Metal Organic Chemical Vapor Deposition). The growth conditions were as follows.
[0281]
Source gas: TMG / AsH_Three/ H₂
Gas pressure: 80 Torr
Temperature: 700 ° C
[0282]
As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no crystal defects were introduced into the GaAs layer and a GaAs layer having good crystallinity was formed. At the same time, it was confirmed that an extremely steep interface was formed between the porous Si layer whose surface was sealed with Si.
[0283]
Further, the defect density was obtained by counting the number of crystal defects revealed by an optical microscope by defect revealing etching.^Four/ Cm²Met.
[0284]
【The invention's effect】
As described above, according to the present invention, the heat treatment (pre-baking) conditions performed prior to the growth of the non-porous single crystal layer on the porous silicon layer are set to the change rate r of the haze value that is easy to measure. It can be determined using.
[0285]
Further, as described above, according to the present invention, the heat treatment (pre-bake) is performed so that the change rate r of the haze value of the surface of the porous silicon before and after the heat treatment is within 3.5, more preferably within 2, and The stacking fault density of the non-porous single crystal silicon layer formed on the porous layer is set to 1000 / cm by performing the conditions under which the silicon etching amount in the heat treatment is suppressed to 2 nm or less, more preferably 1 nm or less.²Less than 100 / cm²I was able to. Furthermore, the defect reduction of the present invention can be further improved by reducing the amount of silicon raw material supplied to the growth surface at the initial growth stage of non-porous single crystal silicon.
[0286]
As a result, when the present invention is applied to the bonding method, an SOI layer having a uniform film thickness and extremely few crystal defects can be obtained.
[0287]
In other words, the present invention reduces the heat treatment time and temperature for removing the natural oxide film in a short time by suppressing the amount of the natural oxide film on the porous surface that is formed in the epitaxial growth apparatus. At the same time, the structural change in the surface of the porous layer and in the vicinity of the surface is suppressed, and the formation of the non-porous single crystal silicon film is started before the change in the surface structure of the porous layer becomes obvious. Density 1000cm²Less epitaxial silicon layer is obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a method for forming a non-porous single crystal layer on a porous silicon layer.
FIG. 2 is a diagram showing an example of an apparatus with a load lock chamber.
FIG. 3 is a diagram for explaining a silicon etching amount in an epitaxial growth apparatus;
FIG. 4 is a diagram for explaining a relationship between a heat treatment temperature and a defect density according to a difference in an epitaxial growth apparatus.
FIG. 5 is a diagram illustrating a change in haze value due to heat treatment of porous silicon.
FIG. 6 is a diagram for explaining a relationship between a change rate of a haze value and a defect density.
FIG. 7 is an SEM image for explaining the change of the surface pores of the porous layer due to heat treatment.
FIG. 8 is a schematic diagram for explaining changes due to heat treatment of the surface pores of the porous layer.
FIG. 9 is a diagram for explaining the relationship between the time of a trace silicon raw material supply step and the defect density.
FIG. 10 is a diagram illustrating a change in haze value due to supply of a small amount of silicon.
FIG. 11 is a diagram for explaining the difference in the relationship between the heat treatment temperature and the defect density due to the difference in pressure during the heat treatment.
FIG. 12 is a diagram illustrating the relationship between heat treatment time and defect density.
FIG. 13 is an example of a system for determining conditions for appropriately performing pre-baking processing.
FIG. 14 is a schematic diagram illustrating a process of the present invention.
FIG. 15 is a schematic view illustrating a manufacturing process of an SOI substrate according to the present invention.
FIG. 16 is a conceptual diagram of an observation method of the foreign matter inspection apparatus.
[Explanation of symbols]
1. Substrate having a porous silicon layer
2 holes
3 hole wall
4 Protective film
5 Protective coating
6 Non-porous single crystal layer
10 Substrate
11 Porous silicon layer
13 Incident light
14 Reflected light
15 Scattered light
16 Silicon wafer
17 Observation area

Claims (10)

In a method for manufacturing a semiconductor substrate having a non-porous single crystal layer on a porous silicon layer, the porous silicon layer is non-coated prior to the step of forming the non-porous single crystal layer on the porous silicon layer. A rate of change of the haze value of the surface of the porous silicon layer before and after the heat treatment r (r = (porous after the heat treatment) A method for producing a semiconductor substrate, wherein the haze value on the surface of the silicon layer) / (the haze value on the surface of the porous silicon layer before the heat treatment)) satisfies 1 ≦ r ≦ 3.5 .   In a method for manufacturing a semiconductor substrate, comprising a step of preparing a substrate having a porous silicon layer, a heat treatment step of heat-treating the porous silicon layer, and a growth step of growing a non-porous single crystal layer on the porous silicon layer The heat treatment is performed in an atmosphere that does not include the source gas of the non-porous single crystal layer, the silicon etching amount by the heat treatment is 2 nm or less, and the change rate r (r of the haze value on the surface of the porous silicon layer) = Haze value after heat treatment / Haze value before heat treatment) is performed so as to satisfy 1 ≦ r ≦ 3.5.   Providing a first substrate having a porous silicon layer, a heat treatment step for heat-treating the porous silicon layer, a growth step for growing a non-porous single crystal layer on the porous silicon layer, and the first step In the method for manufacturing a semiconductor substrate, including the step of transferring the non-porous single crystal layer on the substrate onto the second substrate, the heat treatment is performed in an atmosphere that does not include the source gas of the non-porous single crystal layer and The etching amount of silicon by the heat treatment is 2 nm or less, and the change rate r (r = the haze value after the heat treatment / the haze value before the heat treatment) of the haze value on the surface of the porous silicon layer is 1 ≦ r ≦ 3. 5. A method for manufacturing a semiconductor substrate, which is performed so as to satisfy 5. It said non-porous single crystal, non-porous method for manufacturing a semiconductor substrate according to claim 1 wherein the single crystal silicon layer. The heat treatment step includes a Atsushi Nobori step and the native oxide film removal step, the native oxide film removal step is 850 ° C. or higher, a method for manufacturing a semiconductor substrate according to claim 1, which is carried out at 1000 ° C. or lower. Prior to the heat treatment step, a method for manufacturing a semiconductor substrate according to claim 1, further comprising a step of removing the oxide film formed on the surface of the porous monocrystalline silicon layer. The thermal treatment process, the growth step, the method for manufacturing a semiconductor substrate according to claim 1, wherein a carried out in a reaction vessel load lock chamber is attached. The pressure during the heat treatment step, a method for manufacturing a semiconductor substrate of high claim 1 than the pressure of the growing step. The heat treatment process, a reducing atmosphere containing hydrogen gas, a nitrogen gas atmosphere or a method for manufacturing a semiconductor substrate according to claim 1, which is carried out in an inert gas atmosphere. The heat treatment process, a method for manufacturing a semiconductor substrate according to claim 1, which is carried out at 870 ° C. or higher 970 ° C. or less.

Images