JP3216078B2 - Semiconductor substrate and method of manufacturing semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of forming a semiconductor substrate, and more particularly, to a semiconductor substrate and an SOI substrate.
The present invention relates to a semiconductor substrate used as a substrate of an integrated circuit using a MOSFET, a bipolar transistor, and the like, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a silicon-based semiconductor device and an integrated circuit technology, a silicon-on-insulator (SOI) structure has a higher transistor speed by reducing parasitic capacitance and facilitating element isolation. Numerous studies have been made on technologies for reducing power consumption, increasing integration, and reducing total cost.

[0003] In the 1970's, Imai introduced FIPO, which formed an SOI structure by utilizing the porous silicon accelerated oxidation phenomenon.
Proposed S (Fully isolation by porous silicon) method (K. Imai, Solid State Electronics 24 (1981) p.15)
9). In this method, first, an n-type island is formed on a p-type substrate. Thereafter, the p-type region is selectively made porous including the lower portion of the n-type island by anodization. On the other hand, the n-type region remains without being made porous. Porous silicon was introduced in 1964 by Uhlir et al. (A. Uhlir, Bell Syst. Tech. J., 35 (1956), p. 33).
As found in 3), pores with a diameter of several nanometers to several tens of nanometers are formed inside the silicon crystal like a sponge, and the surface area per unit volume is several hundred m ² / cm ³
Above and very big. Therefore, when thermal oxidation is performed in an atmosphere containing oxygen (Thermal Oxidation), not only the surface but also the inside of the porous silicon is simultaneously oxidized by oxygen reaching the inside of the porous silicon, so that the porous layer is selectively oxidized. can do. Since the oxide film thickness is controlled by the thickness of the porous layer rather than the oxidation time, it is possible to form a silicon oxide film tens to hundreds of times thicker than when bulk silicon is oxidized. It is possible. That is, it is possible to completely oxidize the formed porous region and leave the island region of silicon without completely oxidizing the n-type silicon island. According to this method, an island of silicon was formed on the oxidized porous silicon by FI.
POS. Since silicon expands in volume when oxidized, porous silicon also has a porosity in FIPOS in order to prevent volume expansion due to oxidation and the accompanying introduction of wafer warpage and defects.
y (porosity): pore volume / (residual silicon volume + pore volume) was preferably around 56%.

Then, as an improvement of this method, after porous silicon is formed on the entire surface, non-porous single-crystal silicon is epitaxially grown on the porous silicon, and a part of this epitaxial silicon layer is removed to remove the porous silicon. After exposing porous silicon, a method of realizing an SOI structure by selectively oxidizing porous silicon by thermal oxidation has been proposed (H. Takai, and T. Itoh, J. Electronic Materials 12 (198)
3) p.973).

[0005] With the development of the field of application of porous silicon called FIPOS, the growth of a non-porous single crystal silicon layer on the porous silicon layer has also been developed with the application to FIPOS in mind.

[0006] T. Unagami et al. (T. Unagami, and M. Seki, J. El.
ectrochem. Soc., 125 (1978), p. 1340), probably the first epitaxial growth on porous silicon, reported prior to the publication of the FIPOS method, had a p-value of 0.004-0.15 Ωcm.
After forming porosity on the surface of the mold (111) Si wafer,
Growth rate 0.4 .mu.m / min of SiCl ₄ as a source gas in a hydrogen atmosphere at 1170 ° C.. Grows an epitaxial silicon layer. Sirtle Etchin
According to the observation after g, almost no stacking faults are observed. However, such a high-temperature heat treatment markedly increased the size of the porous structure, and was not suitable for forming a FIPOS structure. For this reason, research reports on the formation of epitaxial layers since the advent of FIPOS focused on how to suppress the structural change of porous silicon and achieve an epitaxial layer with a low crystal defect density.

[0007] Takai et al. (H.Takai, and T.Itoh, J.Electroni
c Materials 12 (1983) p. 973, H. Takai, and T. Itoh, J. App
Phys. 60 (1986) p. 223) has a growth rate of 102-132 nm / min. by a plasma CVD method using SiH ₄ at 750 ° C. in order to suppress the structural change of porous silicon.
Formed a single-crystal silicon layer. Takai et al., Plasma C
It is reported that when an epitaxial silicon layer is formed on porous silicon by the VD method, the porous pores are closed as the thickness of the epitaxial silicon layer increases. The transition layer with holes remaining is estimated to be about 150 nm.

[0008] Vescan et al. (L. Vescan, G. Bomchil, A. Halimao
ui, A.Perio, and R.Herino, Material Letters7 (1988) p.9
4)) is LPVPE (Low Pressure Vapor Phase Epita
xy) was used. Prepare porous silicon with a porosity of 56% formed on a p-type Si substrate of 0.01 Ωcm.
The side wall of the hole was thinly oxidized by dry oxidation at 0 ° C. for 1 hour (Pr
eoxidation; This oxidation treatment is for suppressing the structure of the porous layer from being coarsened by subsequent epitaxial growth or high-temperature heat treatment such as oxidation treatment. Then, after removing only the oxide film on the porous surface by HF Dip, the substrate was placed in a growth vessel and 5 × 1
0 ^-6 After baking in ultrahigh vacuum mbar, SiH ₂
By introducing Cl ₂ , a non-porous single-crystal silicon layer was epitaxially grown by a process at 900 ° C. or lower. According to the cross-sectional observation using a transmission electron microscope, 10 ⁵
A transition network of about / cm ² has been found. Some defects crossing the epitaxial layer have also been observed.

C.Oules et al. (C.Oules, A.Halimaoui, JLReg
olini, R.Herino, A.Perio, D.Benshahel, and G.Bomchil, M
ater.Sci.Eng., B4 (1989) p.435., or C.Oules, A.Ha
limaoui, JLRegolini, A.Perio, and G.Bomchil, J.Elect
rochem.Soc.139 (1992) p.3595.) is similar to Vescan et al.
After preoxidation, in the same LPVPE method, S
It reports that iH ₄ was used as a source gas. They 830 is SiH ₄ and H ₂ as a carrier gas as a raw material gas
Epitaxial growth was performed at 2 Torr at a temperature of 2 Torr. The growth rate was 0.5 μm / min. Met. 0.01Ωcm
Crystal defect density in an epitaxial silicon layer on porous silicon formed on a p-type Si substrate
At a porosity of 50% or less, the defect density observed by planar TEM is almost the same as that of the epitaxially grown layer under the same conditions on a bulk silicon wafer (non-porous) under the same conditions. Although it is shown, its absolute value is not mentioned. Since the measurement area of one sample in a normal planar TEM observation is about 100 μm square, the measurement limit of the defect density is approximately 10 ⁴ / cm ² , and even if a fairly detailed observation is performed, it is 10 ³ / cm ² .
/ Cm ² . In addition, it is assumed that the remaining defects are due to particles or the like caused by a problem on the apparatus, and a detailed evaluation of the defect density requires further experiments in a clean environment.

[0010] There are 1 research reports on these FIPOS methods.
Although it was prosperous from the 970s to the early 1980s, in recent years, the FIPOS method can form a surface silicon layer only in the form of islands and lacks versatility, and the new SOI
With the development of the method of forming the structure, it has fallen.

As described above, in the epitaxial growth on porous silicon for the FIPOS method, the process temperature is set to 900 ° C. or less in order to suppress the coarsening of the porous structure which hinders the subsequent porous selective oxidation process. Had to be cold. For this reason, epitaxial growth has also been limited to techniques such as MBE and LPVPE, which are not widely used as semiconductor silicon production apparatuses.
Therefore, 10 Torr widely used as a production device
Growth in a CVD apparatus that performs growth by supplying a source gas in a hydrogen atmosphere at a pressure of about 760 Torr has hardly been studied.

As an SOI formation technique that has recently attracted attention, an oxygen implantation method (SIMOX: Separation by Impl) has been proposed.
anted Oxygen) and wafer bonding method (wafer
bonding technology). SIMOX is NT
The method proposed by T. Izumi in 1978 (K. Izumi, M. Doke
n, and H.Ariyoshi, Electron.Lett.14 (1978) p.593)
This is a method in which oxygen is ion-implanted into a silicon substrate and then heat treatment is performed at a high temperature exceeding 1300 ° C. to form a buried silicon oxide film. The surface silicon film thickness and the buried silicon oxide film thickness are restricted because they are related to the control of the defect density and the quality of the oxide film. Limited to a specific thickness. The uniformity of the film thickness is also affected by variations in implantation energy during ion implantation. In order to obtain a desired film thickness, a device maker must take measures such as sacrificial oxidation and epitaxial growth, and the thickness uniformity tends to deteriorate especially when the device is thinned. In addition, since the buried oxide film is formed by the aggregation of the implanted oxygen ions, a portion which becomes a pinhole of the buried oxide film is generated in a portion where the aggregation is insufficient. This pinhole leaks from the buried oxide film,
This was the cause of the breakdown voltage failure.

On the other hand, by applying a wafer bonding technique,
Various methods for realizing the OI structure have been proposed in view of the arbitrary thickness of the surface silicon layer and the buried silicon oxide layer of the SOI structure and the good crystallinity of the surface silicon layer. The bonding method of bonding wafers without an intermediate layer such as an adhesive is described by Nakamura et al.
No. 7869, which has been proposed, but its research has been actively conducted by JBLasky et al. (JBLasky, SRStiffler, FRWhit
e, and JRAbernathey, technical Digest of theIntern
ational Electron Devices Meeting (IEEE, New York, 198
5), p.684) describes a method of thinning one of the bonded wafers and the operation of a MOS transistor formed thereon.
It was after reporting in 1985. The method of Lasky et al. Prepares a first wafer in which a low-concentration or n-type epitaxial silicon layer is formed on a single-crystal silicon wafer to which high-concentration boron is added. After cleaning the first wafer and the second wafer having an oxide film formed on its surface as necessary, when the two wafers are brought into close contact, the two wafers are bonded by van der Waals force. When heat treatment is further applied, a covalent bond is formed between the two wafers, and the bonding strength is increased to a level that does not hinder device fabrication. Thereafter, the first wafer is etched from the back surface with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid to selectively remove the p ⁺ silicon wafer and leave only the epitaxial silicon layer on the second wafer. This is the method of Lasky et al. However, p ⁺ silicon and epitaxial silicon (p ⁻
Alternatively, since the etching rate ratio in n) is as low as several tens, it has been difficult to leave an epitaxial silicon layer having a uniform thickness on the entire surface of the wafer.

A method for solving this problem is to perform selective etching.
Some of them are implemented twice. That is, the first group
The surface of a low impurity concentration silicon wafer substrate
To p ⁺⁺Prepare a stack of Si layer and low impurity concentration layer
You. This substrate is bonded to a second substrate similar to the above method.
Let After that, the first substrate is ground, polished, etc. from the back side.
The thickness is reduced by the mechanical method described above. Then embedded in the first substrate
P⁺⁺Selective etching until Si layer is fully exposed
I do. At this time, ethylene diamine was used as the etchant.
Use an alkaline solution such as mpirocatechol or KOH
Selective etching is performed depending on the impurity concentration of the substrate.
Is Thereafter, the same method as that of Lasky et al.
Selective etching with a mixture of hydrofluoric acid, nitric acid and acetic acid
P⁺⁺If the Si layer is selectively removed, the second
Only the low-impurity-concentration single-crystal Si layer is formed on the substrate.
Will be relocated. In such a method, selective etching is performed.
Multiple selections for comprehensive etching
The surface Si layer in SOI
Was improved in film thickness uniformity.

However, in the above-described thinning of the substrate by selective etching utilizing the impurity concentration of the substrate or the difference in composition, the etching selectivity and impurity concentration are greatly affected by the profile in the depth direction. Is easily predictable. That is, when the heat treatment after bonding is performed at a high temperature in order to increase the bonding strength of the wafer, the impurity distribution of the buried layer is expanded, so that the etching selectivity is deteriorated, and as a result, the film thickness uniformity is deteriorated. Was. Therefore, the heat treatment after bonding needs to be 800 ° C. or less. In addition, since the plurality of etchings have a low etching selectivity, controllability during mass production has been questioned.

In the above-described method, the selectivity of etching is determined based on the impurity concentration or the difference in the composition. No.) proposed a new method. The method disclosed in this publication forms a member in which a non-porous single-crystal semiconductor region is disposed on a porous single-crystal semiconductor region, and the surface of the non-porous single-crystal semiconductor region has an insulating material. A method for manufacturing a semiconductor member (A process for pr
eparing a semiconductor member comprising the step
s of: forming a member having a non-porous monocrys
talline semiconductor region on a porous monocryst
alline semiconductor region, bonding the surface of
a member of which the surface is composed ofan
insulating substance onto the surface of said non
-porous monocrystalline semiconductor region, and
then removing said porous monocrystallinesemicondu
ctor region by etching.).

According to the method, an SOI substrate having a uniform thickness of a silicon active layer can be obtained by utilizing the selectivity of etching between a porous single crystal semiconductor region and a non-porous single crystal semiconductor region. It is a method. With this method,
Due to the difference in structure between porous silicon and non-porous silicon having a surface area per unit volume of 200 m ² / cm ³ , selective etching as high as 100,000 times can be realized.

In this method, a high selectivity of 100,000 times can be obtained, so that the resulting film thickness uniformity of the SOI layer is hardly impaired by etching. Is reflected as it is. That is, a commercially available CV
If a D epitaxial growth apparatus is used, the uniformity within a wafer realized by this apparatus is, for example, ± 2-4% or less of SO.
It can also be realized with an I-Si layer. In this method, F
Porous silicon, which was a material for selective oxidation in IPOS, was used as a material for selective etching. Therefore, Poros
ity is not limited to around 56%, but rather 2
A low value of about 0% is preferable. In addition, since porous silicon does not become a structural material of the final product, the influence of warpage and distortion is reduced, so that the structural change of porous silicon,
The coarsening is allowed as long as the etching selectivity is not impaired. That is, the epitaxial growth temperature is not limited to 900 ° C. or lower. The method of fabricating the SOI structure disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-21338 is disclosed by Yonehara et al. (T. Yonehara, K. Sakaguchi, N. Sato, Appl. Phys. Lett. 64).
(1994) p.2108) and was named ELTRAN. In this method, the epitaxial growth of non-porous single crystal silicon on porous silicon is one of the very important steps, and the stacking fault density in the epitaxial silicon layer on porous silicon depends on the growth conditions. It was reported that it may be 10 ³ -10 ⁴ / cm ² . In a SOI wafer formed by the ELTRAN method, the stacking fault is a main defect.

The present inventor Sato et al. (N. Sato, K. Sakaguchi, KY
amagata, Y.Fujiyama, and T.Yonehara, Proc.of the Seve
nth Int.Symp.on Silicon Mater.Sci.and Tech., Semico
nductor Silicon, (Pennington, The Electrochem.Soc.In
c., 1994), p. 443) is a CVD (Chemical vapor Deposit) process using SiH ₂ Cl ₂ as a source gas in an H ₂ atmosphere as an epitaxial growth on a porous material for the ELTRAN method.
ion) method was performed. The process temperature is 1 for pre-bake.
040 degrees and crystal growth of 900-950 degrees, which are higher than those reported in the conventional FIPOS.
(400 ° C., 1 hin O ₂ ) almost suppresses the structural coarsening of the porous silicon layer. It is assumed that stacking faults are dominant in the defects introduced into the epitaxial layer. To reduce stacking faults, pores on the surface of the porous silicon are formed by four digits or more (10 ¹¹ 10 ⁷ / cm ² or less) and that the reduction of oxygen concentration near the surface of the porous layer by HF dip immediately before the substrate is placed in the epitaxial growth furnace is effective (to reduce stacking faults). ing. The stacking density in the epitaxial silicon layer on the porous silicon can be increased by increasing the HF dip to 10 ³ −
Although it decreased to 10 ⁴ / cm ² , the decrease in defect density was saturating. On the other hand, it is suggested that the pores remaining on the porous silicon surface after hydrogen pre-bake are the origins of stacking faults. Growth rate is approximately 100 nm / mi
n. Was over. It is generally pointed out that stacking faults may cause deterioration of the dielectric strength of an oxide film. Also, dislocations surrounding stacking faults increase the leakage current of the pn junction and degrade the minority carrier lifetime, but the idea that this occurs only when dislocations are accompanied by metal impurities is currently dominant. is there. Even in the other reports on epitaxial growth on porous materials mentioned above, after etching for revealing defects with lower detection limits,
Even with the method of observing with an optical microscope, a crystal defect of 10 ³ /
There were no reports that it was below cm ² . 10 ³ -10 ⁴
Although the probability that a stacking fault of / cm ² is included in a 1 μm ² gate region is as low as about 0.0001 to 0.00001, the defect density is still higher than that of a bulk silicon wafer, and the influence is generally higher than that of a bulk silicon wafer. It is expected that the circuit may be surfaced as the yield of the circuit. When the SOI wafer obtained by the above method is put to practical use, it is desirable to further reduce the stacking fault density.

The crystal growth method employed is as follows.
The thickness uniformity of the epitaxial silicon layer is at least ±
There is a demand for an epitaxial growth method by a CVD method using a raw material gas diluted with H _2, which can realize within 4% and better equipment within ± 2%. This is because a widely available commercially available CVD epitaxial growth apparatus can be used, so that equipment investment and equipment development cost can be reduced.

A CVD epitaxial growth apparatus usually used in such a semiconductor process is convenient because it can easily cope with an increase in wafer size (6 → 8 → 12 inches).

On the other hand, it has been shown that prolonging the HF dip immediately before introduction into the growth furnace contributes to a reduction in the crystal defect density. However, in the HF dip, the HF liquid sometimes locally penetrates deeply into the porous silicon and removes the ultra-thin oxide film on the side wall of the hole formed by preoxidation. Then, as a result, local structural coarsening of the porous silicon is caused, and even if the porous silicon is selectively etched, the porous silicon cannot be completely removed and remains in an island shape. For this reason, it is desired to establish a method for further reducing crystal defects in an epitaxial silicon layer on porous silicon in a CVD method for supplying a source gas diluted with H ₂ for achieving a good film thickness distribution. Was.

In the above-described method in which an epitaxial silicon layer on porous silicon is bonded and then the porous layer is removed by etching. If there is, the etchant may enter the bonding interface from here. Then, there is a possibility that a void called a void is generated by etching the buried silicon oxide film. When such voids are formed, the buried oxide film does not exist. Therefore, when a device such as a MOS transistor is manufactured, an operation failure may be caused due to instability of a base interface. (Object of the Invention) A first object of the present invention is to provide a method of manufacturing a semiconductor substrate in which an epitaxial silicon layer with reduced crystal defects is arranged on a porous silicon layer.

A second object of the present invention is to provide a method of manufacturing a semiconductor substrate in which crystal defects in an epitaxial silicon layer formed on a porous silicon layer are reduced and a growth rate is secured. .

Another object of the present invention is to provide a method of manufacturing a semiconductor substrate in which crystal defects in an epitaxial silicon layer formed on a porous silicon layer are reduced and the layer thickness is made uniform. .

Still another object of the present invention is to provide a semiconductor substrate applicable to an SOI substrate having excellent film thickness uniformity, defect density, and buried oxide film characteristics.

[0027]

The above-mentioned object is achieved by the present invention having the following configuration.

The first aspect of the manufacturing method of the semiconductor substrate of the present invention is the manufacturing method of <br/> semiconductor substrate in the porous silicon layer having a monocrystalline silicon layer, at least a silicon source
Charges in an atmosphere containing gas and a hydrogen gas, and the growth rate of the single crystal silicon layer, the single crystal silicon layer is porous sheet
The residual hole density on the crystal growth surface when growing to a layer thickness corresponding to the hole diameter of the recon layer becomes less than 1000 / cm ²
Controlled to is characterized in that the growing said single crystal silicon layer. Manufacturing method of semiconductor substrate of the present invention
The second aspect of the invention is that a single-crystal silicon
In the method for manufacturing a semiconductor substrate having a layer, the single-crystal silicon
The growth rate of the silicon layer is controlled by the
The result when grown to a layer thickness corresponding to the diameter of the hole in the silicon layer
The residual pore density on the crystal growth surface is less than 1000 / cm ²
Growing the single crystal silicon layer at a first growth rate
At a second growth rate higher than the first growth rate.
Growing a crystalline silicon layer.
You. A third aspect of the method for producing a semiconductor substrate of the present invention is a
First part having single-crystal silicon layer on porous silicon layer
Preparing a material, combining the first member and the second member with each other;
Laminate so that the crystalline silicon layer is located inside
Forming a bonded structure, and the porous silicon
Removing the layer.
And an atmosphere containing at least a silicon source gas and hydrogen gas.
In an atmosphere and at a rate of
The crystalline silicon layer corresponds to the pore diameter of the porous silicon layer.
The residual pore density on the crystal growth surface when growing to a layer thickness of
And controlled to be less than 00 / cm ²
It is characterized by growing a recon layer. Book
A fourth aspect of the method for manufacturing a semiconductor substrate according to the present invention is a method for manufacturing a porous substrate.
Using a first member having a single crystal silicon layer on a silicon layer
A step of separating the first member and the second member from each other
Lamination and lamination so that the recon layer is located inside
Forming a porous structure, and removing the porous silicon layer.
The method of manufacturing a semiconductor substrate having a step of to, the
The growth rate of the single crystal silicon layer is controlled by the single crystal silicon layer.
Grown to a thickness corresponding to the pore diameter of the porous silicon layer
The residual pore density on the crystal growth surface is less than 1000 / cm ²
The single crystal silicon layer is grown at a first growth rate that disappears.
After that, a second growth rate higher than the first growth rate.
Growing the single crystal silicon layer at a temperature
Things. Fifth aspect of the method for producing a semiconductor substrate of the present invention
Has a single crystal silicon layer on a porous silicon layer
A method of manufacturing a semiconductor substrate, comprising a porous silicon layer.
Preparing a substrate to be processed, and at least
Porous silicon in an atmosphere containing a source gas and hydrogen gas.
20 nm / min. At the following growth rate,
It has a step of growing a recon layer.

In a sixth aspect of the method for producing a semiconductor substrate according to the present invention , a single crystal silicon layer is provided on a porous silicon layer.
A method of manufacturing a semiconductor substrate, comprising a porous silicon layer.
Preparing a substrate to be coated, 20 μm on the porous silicon layer
nm / min. The single crystal silicon has a first growth rate of
Growing the growth layer, and a speed higher than the first growth rate.
Growing the single crystal silicon layer at a second growth rate.
Have a process

According to a seventh aspect of the method for producing a semiconductor substrate of the present invention, a first substrate having a porous silicon layer is prepared.
Process, atmosphere containing at least silicon source gas and hydrogen gas
In an atmosphere, 20 nm / min.
A step of growing a single-crystal silicon layer at a growth rate of
The single crystal silicon layer includes the first substrate and the second substrate.
Laminated so that it is located on the side, and form the bonded structure
Forming, and removing the porous silicon layer
Have

According to an eighth aspect of the method for producing a semiconductor substrate of the present invention, a first substrate having a porous silicon layer is prepared.
Step, 20 nm / min. On the porous silicon layer. Less than
For growing a single-crystal silicon layer at a first growth rate
At a second growth rate higher than the first growth rate.
Growing a monocrystalline silicon layer, the first substrate and the second
A substrate is bonded so that the single crystal silicon layer is located inside.
Forming a bonded structure and a bonded structure;
And a step of removing the porous silicon layer.

The present invention includes a semiconductor substrate. The semiconductor substrate of the present invention is obtained by the method for producing a semiconductor substrate of the present invention. Further, the semiconductor substrate of the present invention includes the following aspects.

[0033]

[0034]

According to the present invention having the above-described structure, the above-described object is achieved.

According to the present invention, by controlling the growth rate when forming a non-porous single-crystal silicon layer on porous silicon to a range where nucleation does not occur, defects in the non-porous single-crystal silicon layer can be reduced. The density can be reduced to less than approximately 1000 / cm ² .

Further, according to the present invention, the growth at such a growth rate that does not cause nucleation is limited to the initial stage of the growth on the porous material, and thereafter, a conventional growth method can be adopted. It is possible to reduce the crystal defect density while maintaining the growth rate as before. In addition, after growth at a growth rate that does not cause nucleation, growth for increasing the film thickness is performed in a low temperature region to reduce the crystal defect density, reduce the Boron concentration, and enlarge the porous structure. Both suppression can be achieved.

Further, according to the present invention, the surface roughness of the epitaxial silicon layer on the porous silicon is improved, so that when bonding is performed, an increase in bonding strength or the generation of a bonding failure area occurs. It is significantly suppressed. Further, since growth at a growth rate that suppresses nucleation is a growth mode in which the surface diffusion of incident atoms is dominant, the generation of pinholes due to minute foreign matter and the like is also suppressed.

In addition, when the method for manufacturing a semiconductor base material of the present invention is applied to a method for manufacturing an SOI substrate, the density of crystal defects in the single crystal silicon layer is less than 1000 / cm ^2.
An OI structure can be realized. In addition, the gap at the bonding interface due to the pinhole can be almost eliminated.
Also, no pinholes exist in the buried oxide film.

The SOI substrate obtained by this method has a low defect density and a uniform film thickness, and is superior to SIMOX without pinholes in the buried oxide layer. This is because the thermal oxide film formed on the second member to be bonded can be used as a buried insulating layer having an SOI structure.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the method for manufacturing a semiconductor substrate according to the present invention is as described above. The most characteristic feature of the manufacturing method of the present invention is that when a non-porous single-crystal silicon layer is grown on a porous single-crystal silicon layer, it is initially grown at a very low growth rate. The method for manufacturing a semiconductor substrate according to the present invention is applicable to a method for manufacturing an SOI substrate, and the demand for a high-quality SOI substrate is great. The present invention will be described below based on the method. The method of manufacturing an SOI substrate studied by the present inventors can be roughly classified into a step of making a single crystal silicon substrate porous, a step of epitaxially growing single crystal silicon on a porous silicon layer, and a step of forming an epitaxial silicon film. And a step of bonding to another substrate and a step of removing the porous silicon layer.

An example of a method for manufacturing such an SOI substrate will be described with reference to FIGS.

The single-crystal silicon substrate 100 is anodized to form porous silicon 101 (FIG. 7A). At this time, the thickness to be made porous may be several μm to several tens μm on one surface layer of the substrate. Alternatively, the entire silicon substrate 100 may be anodized.

A method for forming porous silicon will be described with reference to FIG. First, a P-type single crystal silicon substrate 600 is prepared as a substrate. Although it is not impossible even with an N-type, in that case, the substrate must be limited to a low-resistance substrate, or the substrate surface must be irradiated with light to promote the generation of holes. The substrate 600 is set in an apparatus as shown in FIG. That is, one side of the substrate is in contact with the hydrofluoric acid solution 604, and the negative electrode 6 is connected to the solution side.
06, and the opposite side is in contact with the positive metal electrode 605. Alternatively, as shown in FIG. 10 (B), the positive electrode side 605 'may also take a potential via the solution 604'. In any case, porosity occurs from the negative electrode side in contact with the hydrofluoric acid-based solution. As the hydrofluoric acid solution 604, generally, concentrated hydrofluoric acid (49% HF) is used. When diluted with pure water (H ₂ O), it depends on the value of the flowing current.
It is not preferable because etching occurs from a certain concentration. In addition, bubbles are generated from the surface of the substrate 600 during the anodization, and for the purpose of efficiently removing the bubbles,
Alcohol can also be added as a surfactant. As the alcohol, methanol, ethanol, propanol, isopropanol and the like are used. Alternatively, anodizing may be performed while stirring the solution using a stirrer instead of the surfactant. Regarding the negative electrode 606, a material that is not eroded by the hydrofluoric acid solution, for example, gold (A
u), platinum (Pt) or the like is used. Positive electrode 605
May be a commonly used metal material, but the hydrofluoric acid-based solution 604 reaches the positive electrode 605 when the anodization is performed on all the substrates 600.
It is preferable that a metal film having a hydrofluoric acid solution resistance is coated on the surface of the substrate. The current value for anodizing is up to several hundred mA / c.
m ² and the minimum value need not be zero. This value is determined within a range where good quality epitaxial growth can be performed on the surface of the porous silicon. Usually, when the current value is large, the rate of anodization increases, and at the same time, the density of the porous silicon layer decreases. That is, the volume occupied by the holes increases. This changes the conditions for epitaxial growth.

The porous layer 101 formed as described above
A non-porous single-crystal silicon layer 102 is epitaxially grown thereon (FIG. 7B). Here, how to form a single-crystal silicon layer is an important point of the present invention, which will be described in detail later.

Next, the surface of the epitaxial layer 102 is oxidized to form a SiO ₂ layer 103 (including thermal oxidation) (FIG. 7C). This is because when the epitaxial layer is directly bonded to the supporting substrate in the next step, impurities tend to segregate at the bonding interface, and the number of dangling bonds at the interface increases, resulting in the characteristics of a thin film device. This is a cause of instability. However, this step is not necessarily essential, and may be omitted if a device configuration that does not cause the above phenomenon to be considered is considered.
Here, the SiO ₂ layer 103 functions as an insulating layer of the SOI substrate, but the insulating layer needs to be formed on at least one surface of the substrate to be bonded. There is.

In the case of oxidation, the thickness of the oxide film only needs to be thick enough not to be affected by contamination from the air introduced into the bonding interface.

The substrate 100 having an oxidized epitaxial surface and the SiO ₂ layer 104 serving as a support substrate
Is prepared. Support substrate 110
Is the silicon substrate surface oxidized (including thermal oxidation),
Examples include quartz glass, crystallized glass, and glass obtained by depositing SiO ₂ on an arbitrary substrate. Here, the SiO ₂ layer 104
It is also possible to use a silicon substrate provided with no.

After cleaning the two prepared substrates, they are bonded together (FIG. 7D). The cleaning method is performed in accordance with a general step of cleaning a semiconductor substrate (for example, before oxidation).

Pressing the entire surface of the substrate after bonding has the effect of increasing the bonding strength.

Then, the bonded substrates are heat-treated.
The heat treatment temperature is preferably higher. However, if the heat treatment temperature is too high, the porous layer 101 may cause a structural change or impurities contained in the substrate may diffuse into the epitaxial layer. You need to choose a time. Specifically, about 600 to 1100 ° C. is preferable. Some substrates cannot be heat-treated at high temperatures. For example, when the support substrate 110 is made of quartz glass, a temperature difference of 200 ° C.
The heat treatment can be performed only at a temperature lower than about. If the temperature is exceeded, the bonded substrates are peeled off or broken by stress. However, the heat treatment only needs to be able to withstand the stress at the time of grinding or etching the bulk silicon 100 performed in the next step. Therefore, even at a temperature of 200 ° C. or less, the process can be performed by optimizing the surface treatment conditions for activation.

Next, the silicon substrate portion 100 and the porous portion 101 are selectively removed while leaving the epitaxial growth layer 102 (FIG. 7E). Thus, an SOI substrate is obtained.

Further, the following steps may be added to the steps described above. (1) Oxidation (Preoxidation) of Inner Wall of Pores of Porous Layer The thickness of the wall between adjacent holes of the porous silicon layer is several n.
It is very thin, from m to several tens nm. For this reason, when a porous layer is subjected to high-temperature treatment, such as during the formation of an epitaxial silicon layer or during heat treatment after bonding, the pore walls are aggregated. There are cases. Therefore, after the formation of the porous layer, a thin oxide film is formed on the hole wall, so that the hole can be prevented from becoming coarse. However, since it is necessary to epitaxially grow a non-porous single-crystal silicon layer on the porous layer, only the surface of the inner wall of the hole is oxidized inside the hole wall of the porous layer so that the single-crystal property remains. There is a need to. It is desirable that the oxide film formed here has a thickness of several to several tens of mm. An oxide film having such a thickness is formed at a temperature of 200 ° C. to 70 ° C. in an oxygen atmosphere.
It is formed by heat treatment at a temperature of 0 ° C, more preferably at a temperature of 250 ° C to 500 ° C. (2) Hydrogen baking treatment The present inventors have previously shown in EP 553 852 A2 that heat treatment in a hydrogen atmosphere removes minute roughness (roughness) on a silicon surface and obtains a very smooth silicon surface. Was. In the present invention,
Baking under a hydrogen atmosphere can be applied.
Hydrogen baking, for example, after forming a porous silicon layer,
Can be performed before forming the epitaxial silicon layer,
Alternatively, it can be performed on an SOI substrate obtained after the porous silicon layer is removed by etching. Depending on the hydrogen baking treatment performed before the formation of the epitaxial silicon layer, a phenomenon occurs in which the outermost surface of the hole is closed due to migration of silicon atoms constituting the porous silicon surface. When the epitaxial silicon layer is formed with the outermost surface of the hole closed,
An epitaxial silicon layer with less crystal defects can be obtained. On the other hand, depending on the hydrogen baking performed after the etching of the porous silicon layer, the action of smoothing the somewhat roughened epitaxial silicon surface by the etching and the skipping of boron in the clean room that is inevitably taken into the bonding interface during bonding are called. There is action.

The cause of the introduction of crystal defects in the epitaxial silicon layer on the porous silicon grown by the CVD method or the like has not been elucidated at present. However, from the fact that no crystal defects are introduced into the epitaxially grown layer on the bulk wafer under the same conditions, growth on porous material is the first factor for introducing stacking faults. Next, in the hydrogen pre-bake before epitaxial growth, pores were observed to be blocked, but it was reported that pores still remained. is expected.

On the other hand, silicon homoepitaxial growth on bulk silicon by the CVD method of diluting with H ₂ and supplying a source gas is widely spread as an essential technique in the silicon semiconductor process, and the uniformity of film thickness is ± 2 It can be within 4%. Conventionally, in the epitaxial growth by the CVD method, research and development have been focused on forming an epitaxial layer having a thickness of several μm. Here, the main focus has been on lowering the growth temperature or increasing the growth rate in order to suppress autodoping of impurities. Therefore, a growth rate of 50 nm / min. As seen in reports on epitaxial growth on porous silicon. Less is reported on the growth below.

The present inventors have conducted detailed experiments to reduce the stacking fault density, and have found that the growth rate and temperature at the initial stage of epitaxial growth are important factors for reducing defects. FIG. 1 shows the experimental results of silicon epitaxial growth on porous silicon in a commercial CVD epitaxial growth furnace in which SiH ₂ Cl ₂ is diluted with H ₂ . The relationship between the growth rate in the initial stage of epitaxial growth and the stacking fault density is shown. The growth temperature is 1150 degrees and the pressure is atmospheric pressure. The stacking fault density is such that the growth rate is 20 nm / min. , The stacking faults can be rapidly reduced, and the stacking faults can be reduced by at least 1/3, or two orders of magnitude depending on the condition, as compared with the conventional high growth rate system. This is because when the growth rate falls below a certain value, the surface diffusion of Si atoms adsorbed on the porous silicon surface becomes more apparent rather than an increase in the film thickness, resulting in an increase in the number of atoms incorporated into the lattice at the portion of the residual pores. Conceivable. On the porous surface due to hydrogen pre-bake before epitaxial silicon growth, the pores are blocked by the surface diffusion of atoms constituting the surface, resulting in a diameter of several nm to several tens of nm observed in a planar observation with a high-resolution scanning electron microscope. n
Holes with a density of 10 ¹¹ / cm ² at m are hardly observable. The lower limit of measurement at this time was about 10 ⁷ / cm ² . At the same time, flattening by hydrogen baking advances in the portions where the holes have disappeared, and atomic steps peculiar to the (2 × 1) surface structure are observed. In order to confirm the existence of residual holes, the substrate taken out of the furnace after hydrogen prebaking alone was placed in a load lock type vacuum chamber compatible with ultra-high vacuum, and the pressure drop in the vacuum chamber was reduced by the porous layer. Was clearly slower than the bulk silicon wafer where no was formed. Similarly, porous silicon without hydrogen pre-bake, an epitaxial layer of 2 μm on the porous
A similar experiment was conducted on a bulk silicon wafer using the substrate formed with m. When the time required to reach the pressure reached when the bulk silicon wafer was introduced was compared, the order was as follows.

Porous silicon (with pre-bake)> porous silicon (without pre-bake) >> porous silicon to bulk silicon with epitaxial layer (2 μm) That is, residual pores still exist on the surface of porous silicon immediately after hydrogen baking it seems to do. FIG.
(A)-(c) are cross-sectional schematic views of a process in which pores on the surface are closed by hydrogen prebaking. In the portions where the holes have disappeared, the flattening by hydrogen baking proceeds, and atomic steps peculiar to the (2 × 1) surface structure are observed. Fig. 2 shows the density distribution of adsorption sites such as steps and kinks on the surface.
Shown in The site density is very high only around the residual holes. This is because many surfaces are continuously exposed at the portion of the residual hole based on the curvature of the exposed silicon surface.

Now, it is assumed that the growth is started and the supply of the atoms constituting the grown film on the surface is started. When the amount of the incident atoms is large, the incident atoms collide with each other on the terrace before reaching the step and become a dimer. The mobility of the dimer on the surface is much lower than that of the monomer. That is, it becomes a nucleus and becomes an adsorption site for further incident atoms. That is, as a result of the increase in the effective step (adsorption site) density, the incident atoms are incorporated into the lattice with almost no surface diffusion. In other words, the in-plane distribution of the probability that the crystal lattice of the incident atoms is incorporated is small, and as a result, the thickness of the residual hole increases before the hole disappears. Become
It is considered that a defect is finally introduced. FIG.
(A) to (e) show schematic cross-sectional views. In FIG. 1, the portion where the stacking fault density does not depend on the growth rate is the growth by this mechanism. When nucleation occurs, the stacking fault density is determined by the residual pore density immediately before growth.

On the other hand, when the incident atomic weight is small, the growth is considered to be two-dimensional growth with only the step as the growth starting point. Assuming that the surface diffusion distance of the incident Si atom is sufficiently longer than the average distance of the terrace between the steps in the portion other than the vicinity of the residual hole, the incident Si atom reaches the terrace and is incorporated into the step. As shown in FIG. 2, when Si atoms are incident on a surface having a distribution of adsorption site densities, the probability that the incident Si atoms diffuse on the surface and are taken into a large number of adsorption sites (steps) around the residual holes is extremely high. To increase. That is, the portion of the residual hole functions as a sink for surface diffusing atoms, that is, most of the incident atoms are used to block the residual hole, and the opening portion of the residual hole narrows with almost no increase in film thickness, and finally The holes disappear without introducing defects. As described above, in the early stage of the epitaxial growth process, by supplying a small amount of the constituent atoms of the film or the source gas that does not cause nucleation on the porous Si surface, the residual holes can be closed without introducing defects. it can. After that, it is not limited by the amount of raw material supplied to the surface,
Crystal growth can be performed in the same manner as on normal bulk silicon. FIGS. 4A to 4E show schematic sectional views. In FIG. 1, the stacking fault density decreases rapidly with the growth rate phenomenon when the residual holes are closed by this mechanism. In addition, hydrogen pre-bake before growth is not necessarily required, and it is sufficient if a natural oxide film or the like does not remain on the porous silicon surface. Baking in an ultra-high vacuum, etching with HCl or the like,
The natural oxide film may be removed. That is, it is sufficient that the oxide film on the surface is removed even if the residual pore density is not reduced in advance by hydrogen pre-baking.

On the other hand, after the supply of the atoms of the grown film is started, the H ₂ gas is effective for preventing the surface from being reoxidized. The point of attachment of oxygen atoms to the growth surface becomes the nucleus of the film growth, which reduces the surface diffusion distance. To prevent such reoxidation and increase the surface diffusion distance, it was effective to increase the temperature during growth. When the raw material is supplied by dilution with H ₂ , it depends on the pressure, but is generally 800 ° C. or higher, more preferably 900 ° C.
A temperature of at least ℃ is desirable. At temperatures below this,
The effect was not significant.

Further, as shown in FIG. 5, the present inventor clarified the relationship between the growth rate and the reduction of the residual hole density by forming a single-crystal silicon layer on the porous silicon at several growth rates. After epitaxial growth of a film thickness equivalent to the maximum pore diameter of
The time required to reach a given pressure was compared. Here, the maximum pore diameter is a value obtained by adding three times the standard deviation of the pore diameter distribution to the average pore diameter measured by the gas adsorption method, but may be obtained from actual measurement. The measurement of pore size distribution by gas adsorption method is detailed in the report of R. Herino et al. (R. Herino, G. Bomchil,
K.Barla, C.Bertrand, and JLGinoux, J.Electrochem.So
c.134 (1987) p.1994). When the growth rate is 20 nm / min.
It can be seen that when the pressure is turned off, the time for the pressure to decrease rapidly is shortened. When FIG. 5 corresponds to FIG. 4, it can be seen that lowering the growth rate does not increase the film thickness, but the hole remaining during hydrogen pre-baking is closed and the density of crystal defects introduced into the epitaxial silicon layer is good. It is clear that there is. That is, it has been clarified that the residual hole density at the time of forming the ultra-thin epitaxial layer greatly changes depending on the growth rate.

The pore density of porous silicon can be measured by ultra-high resolution scanning electron microscope observation or gas adsorption method. However, if the pore diameter is small and the pore density is low, a problem may occur in the measurement accuracy. . Here, the residual pore density of the sample after the formation of the low-density ultra-thin epitaxial layer, which is difficult to find by ultra-high resolution scanning electron microscope observation, was measured by the method described below.

1) A sample was mixed with a mixed solution of ammonia and hydrogen peroxide solution or a mixed solution of hydrogen chloride and hydrogen peroxide solution
It is immersed in an aqueous solution heated to a temperature of about 0 to 100 degrees to form a hydrophilic surface. The type of the chemical is not limited as long as the surface can be made hydrophilic.

2) Immerse the sample in pure water. Pure water is transferred from the pores remaining on the surface to the inner porous layer using Capillary F.
Infiltrated by orce. The pores of the porous silicon extend not only vertically from the surface but also in the lateral direction in a complicated manner, and the intruded water spreads not only immediately below the residual pores but also in the lateral direction. Water at room temperature is sufficient, but heating is better. The time is not particularly limited, but is 1 minute or more, more preferably 5 minutes or more.

3) The sample is oxidized by thermal oxidation after being withdrawn from pure water. The oxidation temperature is at least 400 degrees or more, more preferably 800 degrees or more, and an oxide film thickness of 10 nm is sufficient. If the thickness is more than necessary than the thickness of the epitaxial layer, the sample may be warped, which may hinder subsequent observation.

During this oxidation treatment, the water permeated from the residual pores evaporates due to an increase in temperature and becomes a competitive process between the process of desorbing from the residual pores and the porous oxidation process. By setting the above range,
The latter can be dominant. As a result, the porous silicon is preferentially oxidized in the water-soaked portion, so that this portion can be easily observed using an optical microscope or the like from the surface morphology or contrast due to light interference. all right.

That is, this method makes it possible to measure the residual pore density of porous silicon when the pore density is low. FIG. 6 shows the relationship between the growth rate and the residual pore density when the ultra-thin epitaxial silicon layer is deposited to a thickness corresponding to the maximum pore diameter of porous silicon. When the growth rate is about 20 nm / min. It can be seen that the residual pore density decreases rapidly when the ratio is less than. 6 and FIG. 1, the residual hole density and the stacking fault in the ultra-thin film region correspond to each other, and the stacking fault density is set to 1000 / cm ² by making the residual hole density less than 1000 / cm ^2. It is clear that less than ² can be done. According to other experiments, the conditions of the growth rate are different when the growth temperature, growth gas, etc. are different, but in any case, when the ultra-thin epitaxial silicon layer is formed to have a film thickness corresponding to the maximum pore diameter of porous silicon. If the residual pore density is less than 1000 / cm ^2, that the crystal defects in the epitaxial layer on the resulting porous by the subsequent epitaxial growth is less than 1000 / cm ² was revealed. Here, the maximum pore size is the average pore size measured by the gas adsorption method, which is 3 times the standard deviation of the pore size distribution.
Doubled value was added. That is, the growth rate is 20 nm / m
in. Below which the residual pore density rapidly decreases to 1000
/ Cm ² became clear.

In other words, the present invention is to obtain an epitaxial layer on porous silicon having a crystal defect density of less than 1000 / cm ² by controlling the thickness of the transition layer between the epitaxial layer and the porous layer. As the growth method, if the epitaxial growth by the CVD method in which the source gas is diluted with H ₂ is used, it is sufficiently possible to make the thickness uniformity of the epitaxial silicon layer within ± 4%.

When residual pores are present in the porous silicon, the ultrathin oxide film remaining inside the pores is vaporized by etching with hydrogen, the oxygen concentration near the surface is locally increased, and the porous silicon surface is regenerated. Supply of a small amount of constituent atoms of the film or atomic gas that does not cause formation of a small amount of nuclei, which may adhere, has an effect of removing oxides and suppressing generation of defects due to oxides.

Further, according to the present invention, nucleation due to collision of incident atoms and the like is suppressed and surface diffusion becomes dominant, so that the so-called coverage is improved. However, no pinhole is formed in that portion, and foreign matter can be covered.

The surface roughness is also improved as compared with the case of the conventional high growth rate. As a result, when the substrate is bonded to another substrate by the ELTRAN method, the bonding strength is improved, and the weakly bonded region and the non-bonded region are improved. Can be suppressed.

The example in which the semiconductor base material of the present invention is applied to the manufacture of an SOI substrate has been described with reference to FIG. 7; explain. (Aspect 2) The aspect shown in FIG. 8 will be described. 8 that are the same as those in FIG. 7 represent the same parts in FIG. In the example shown in FIG. 7, the surfaces of the _two substrates to be bonded are the SiO ₂ layer 103 and the SiO ₂ layer.
_{Although the two} layers 104 are used, both surfaces need not necessarily be SiO ₂ layers, and it is sufficient that at least one surface is made of SiO ₂ . In the embodiment shown here, the epitaxial silicon layer 1102 (B
1) The surface is bonded to the surface of the oxide film 1104 formed on the silicon substrate 1110 (C1), and the surface of the oxide film 1103 formed by thermally oxidizing the surface of the epitaxial silicon layer 1102 (B2) is oxidized. (C2) to be bonded to the surface of the silicon substrate 1110 that has not been formed. In the embodiment shown here, the other steps are the same as those shown in FIG.
Can be performed similarly to the example shown in FIG. (Aspect 3) The aspect shown in FIG. 9 will be described. 9 that are the same as those in FIG. 7 indicate the same parts as in FIG. The embodiment shown here is characterized in that a glass material 1210 (C1, C2) such as quartz glass, blue plate glass, or the like is used for a substrate to be bonded to the substrate (B1, B2) on which the epitaxial silicon film is formed. In this embodiment, the epitaxial silicon layer 11
02 (B1) and a glass substrate 1210 (C
There are shown a 1) mode and a mode (C2) in which an oxide film 1103 (B2) formed by thermally oxidizing the surface of the epitaxial silicon layer 1102 is bonded to a glass substrate 1210. In the embodiment shown here, other steps can be performed similarly to the example shown in FIG.

In the present invention, it is important how a single crystal silicon layer is epitaxially grown on the porous silicon layer.

Since the discovery of porous silicon by Uhlir et al. In 1964, research was carried out in the 1970s with an eye on the application to the FIPOS method. Since its discovery by the group of U. Gosele et al., There has been research aimed at application to this light emitting device. In the study of the light-emitting device based n ^-, p ^-
Silicon substrates are preferred. On the other hand, when fabricating an SOI structure, n ⁺ and p ⁺ substrates are preferred over n ⁻ and p ⁻ because of the stability of the structure and the good crystallinity of the epitaxial silicon layer. The porous Si targeted in the present invention is essentially the same as these conventionally studied porous silicon, and is produced by a method such as anodization, but as long as the porous Si is used. However, the present invention is not limited to substrate impurities, plane orientation, preparation method and the like.

In the case of forming porous silicon by anodization, the chemical conversion solution is an aqueous solution containing HF as a main component.
In general, the addition of alcohol such as ethanol increases the contact angle on the silicon surface, thereby accelerating the desorption of the attached bubbles, so that the chemical formation occurs uniformly. Of course, the porosity is formed without adding alcohol. When the porous silicon according to the present invention is used for FIPOS, the porosity is 56
% Is low porosity when used for ELTRAN
(Approximately 50% or less, more preferably 30% or less) is suitable, but is not limited thereto.

Since the porous silicon is formed by etching as described above, the surface thereof has a small roughness even in a portion other than the hole.
Observed by an icroscope (FESEM).

In the present invention, it has been shown that the inner wall of the hole can be oxidized (preoxidation). However, in the present invention, the silicon oxide film formed by the preoxidation is immersed in a low-concentration HF aqueous solution. (HF
By dip), a step of removing the silicon oxide film near the porous surface can be added. FIG. 4A shows a schematic sectional view of this. Report by Sato et al. (N. Sato, K. Sakaguc
hi, K.Yamagata, Y.Fujiyama, and T.Yonehara, Proc.of th
e Seventh Int.Symp.on Silicon Mater.Sci.andTech., S
emiconductor Silicon, (Pennington, The Electrochem.S
According to oc. Inc., 1994), p. 443), stacking faults can be reduced to about 10 ³ / cm ² by increasing the HF dip time. According to the HF dip for a long time, the structure of the porous layer becomes coarse depending on the annealing temperature after bonding,
During the etching of the porous silicon, an unetched portion (etching residue) was sometimes generated. According to the present invention, the crystal defect density can be reduced by supplying a small amount of Si atoms to the surface of the porous silicon to the extent that nucleation does not occur, as described above. Therefore, the HF dip is not necessarily required. When the HF dip was omitted, no etching residue was generated.

In the present invention, a substrate on which porous silicon is formed is placed in an epitaxial growth apparatus, and a single crystal silicon layer can be epitaxially grown by, for example, the following steps. 1) Removal of native oxide film The native oxide film is removed by a heat treatment in hydrogen (in a non-oxidizing atmosphere) or a heat treatment at about 800 ° C. in an ultra-high vacuum. The processing temperature is at least 600 degrees, more preferably at least 1000 degrees. The pressure is not particularly limited, but is preferably equal to or lower than the atmospheric pressure.

The natural oxide film is desorbed into the gas phase by the reaction of SiO ₂ + Si → 2SiO ↑. HF gas may be used to remove the natural oxide film. Alternatively, if the substrate is placed in a growth furnace without being exposed to an atmosphere containing oxygen from the load lock chamber in a nitrogen atmosphere after the HF dip, the step of removing the natural oxide film by heat treatment may be omitted. Absent. 2) Clogging of pores After the removal of the natural oxide film as described in 1) above, if the heat treatment in hydrogen is continued, the micro-roughness of the surface of the porous silicon is reduced to smooth the minute roughness and reduce the surface energy.
Although n occurs and most of the pores disappear, it is difficult to block all the pores because porous silicon lacks Si atoms per unit area according to its porosity. FIG. 4B shows a schematic sectional view of this. In general, in the case of a high-temperature heat treatment exceeding 1000 degrees in hydrogen, silicon is etched by hydrogen, so the deficiency of Si atoms is further increased. Therefore,
The pores may not necessarily be sufficiently closed, and the process may proceed to the next step.However, by taking sufficient time, the pore density on the porous silicon surface is reduced, and at the same time, the step structure is exposed on the surface. It is more preferable to reduce the density of the adsorption sites. In (100) Si, the steps and terraces have a (2 × 1) structure.

This step is carried out in an inert gas such as argon or helium, not necessarily in a reducing atmosphere such as hydrogen or nitrogen, as long as the oxidizing atmosphere such as residual moisture and oxygen is sufficiently removed. No problem.

The removal of the natural oxide film and the closing of the holes do not necessarily proceed in order, but proceed simultaneously or with an in-plane distribution on the substrate surface. There is. 3) Supply of a very small amount of raw material A small amount of atoms or a raw material gas is supplied while being diluted with H ₂ so that nucleation does not occur on the surface of the porous silicon.
The supplied atoms or the raw material gas diffuses on the surface of the porous surface, is taken into an adsorption site such as a step of a residual hole, and the residual hole is closed without introducing a defect. FIG. 4C shows a schematic sectional view of this.

More specifically, the pore size distribution of porous silicon formed in advance under the same conditions was measured, and the residual pore density when forming a film having the maximum pore size obtained from this pore size distribution was 10%.
The supply rate of atoms or source gas is reduced so as to be less than 00 / cm ² , and the growth rate is reduced. The maximum pore size may be directly obtained from the pore size distribution obtained by a gas adsorption method or the like,
It may be a value obtained by adding three times the standard deviation to the average pore diameter.

SiH ₂ Cl ₂ (dichlorosilane), Si
H ₄ (silane), SiHCl ₃ (trichlorosilane),
In CVD growth using a silicon source gas such as SiCl ₄ (tetrachlorosilane) or Si ₂ H ₆ (disilane), 20 nm / min. The following, more preferably 10
nm / min. Hereinafter, more preferably, 2 nm / mi
n. The flow rate of the source gas is set so that the growth rate is as follows.

It is desirable that the substrate temperature be high in order to increase the surface mobility of atoms incident on the surface. Specifically, 800 degrees or more, more desirably 900 degrees or more,
More desirably, it is not less than 1000 degrees, but is not necessarily limited to this. It is sufficient that the surface mobility is sufficient for the supplied atomic weight. The upper limit of the substrate temperature is determined by the degree of structural coarsening of the porous silicon.

As a result of promoting the surface diffusion of atoms on the growth surface, the surface roughness is also improved.

The material to be supplied is not limited to silicon or silicon-based gas, but may be a group IV heteroepitaxy material such as SiGe or SiC, or GaAs.
Compound semiconductor represented by s may be used. 4) Growth After the closing of the hole is completed by a small amount of raw material supply process,
The growth rate is not particularly limited. The conditions may be the same as those for normal growth on bulk silicon. Alternatively, the growth may be continued at the same growth rate as that of the above-mentioned minute amount of raw material supply step, and changing the gas type or the like does not impair the requirements of the present invention at all. Further, even if the process of supplying the trace amount of raw material is a continuous process, the supply of the raw material may be temporarily interrupted, and then the desired raw material may be supplied again for growth. In any case, a single crystal layer is formed to a desired thickness. FIG. 4D shows a schematic sectional view of this.

That is, since the growth temperature can be controlled independently of the step 3), the structure temperature of the porous silicon can be increased by lowering the processing temperature, or impurities such as boron and phosphorus can be removed from the porous silicon. Auto doping and solid phase diffusion can be suppressed.

The single crystal layer to be grown is not limited to silicon or silicon-based gas, but may be SiGe, Si-based gas.
Group IV heteroepitaxy material such as C, or G
It may be a compound semiconductor typified by aAs, or may be a material different from the trace material supply step.

Further, according to the method of the present invention, after partially removing the epitaxially grown layer by the FIPOS method, the porous silicon is selectively oxidized by an oxidation treatment to obtain SOI.
It can also be applied to form structures. Further, GaAs is formed on the epitaxial silicon layer formed on the porous silicon layer.
Heteroepitaxial growth of a compound semiconductor such as SiC, or a group IV-based material such as SiC or SiGe.

[0090]

Embodiments of the present invention will be described below. [Embodiment 1] In this embodiment, the present invention is intended to reduce crystal defects in an epitaxial silicon layer on porous silicon. 1) Boron is added as a p-type impurity and the specific resistance is 0.01
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) Subsequently, the five wafers on which the porous silicon layers were formed were subjected to an oxidation treatment in an oxygen atmosphere at 400 degrees for 1 hour. Since this oxidation treatment forms only an oxide film of about 50 ° or less, only a silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the pores as disclosed in Japanese Patent Application Laid-Open No. H5-217827. A single crystal silicon region is left inside. 4) After exposing the five wafers to an HF aqueous solution diluted to 1.25% for about 30 seconds, the wafer was washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer. 5) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the conditions of the step b) for each wafer.

A) Temperature: 1150 ° C. Pressure: 760 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1150 ° C. Pressure: 760 Torr Gas: H ₂ ; 230 (l / min. ) SiH ₂ Cl ₂ ; variable (l / min.) Time: 5 minutes The flow rate of SiH ₂ Cl ₂ was 0.005, 0.01, 0.05, 0.1, 0. 25
(L / min.). The growth rate was 2.8, respectively.
5.6, 28, 56, 140 nm / min. Met.

By adjusting the growth time, about 1 μm
A thick single crystal silicon layer was formed. 6) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single crystal silicon layers was measured by a Nomarski differential interference microscope. As a result, the crystal defects were occupied by the stacking faults. SiH
_When the flow rate of ₂ Cl ₂ is 0.005 (l / min.), It is 2 × 10 ² / cm ² , and when it is 0.01 (l / min.), It is 3.5 × 10 ² / cm ² . 05 (l / min.)
1.1 × 10 ³ / cm ² , 0.1 (l / mi
n. ) Is 1.3 × 10 ³ / cm ² , 0.5 (l /
min. )) Was 1.2 × 10 ³ / cm ² . That is, the step b) is introduced, and when the flow rate of the SiH ₂ Cl ₂ gas becomes 0.05 to 0.01 (l / min.), The stacking fault density rapidly decreases, and the stacking fault density becomes about 1/3. Reduced to 〜.

Further, when an area of 50 μm square was scanned with an atomic force microscope and the mean square roughness was measured, the growth rate was 2.8, 5.6, 28, 56, 140 nm / min.
Respectively corresponding to 0.21, 0.22, 0.51,
0.52, 0.51 nm, and a flow rate of 28 nm / min. It was found that lowering the value lowers the surface roughness. Similarly, when the surface roughness of a commercially available Si wafer was measured, it was 0.23 nm. That is, the surface roughness was as flat as the Si wafer. [Embodiment 2] This embodiment aims at both reducing the crystal defects in the epitaxial silicon layer on the porous silicon and securing the growth rate. 1) Boron is added as a p-type impurity and the specific resistance is 0.01
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) Subsequently, the five wafers on which the porous silicon layers were formed were subjected to an oxidation treatment in an oxygen atmosphere at 400 degrees for 1 hour. Since this oxidation process forms only an oxide film of approximately 50 ° or less, a single crystal silicon region remains inside. 4) After exposing the five wafers to an HF aqueous solution diluted to 1.25% for about 30 seconds, the wafer was washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer. 5) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the conditions of the step b) for each wafer.

A) Temperature: 1150 ° C. Pressure: 760 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1150 ° C. Pressure: 760 Torr Gas: H ₂ ; 230 (l / min. ) SiH ₂ Cl ₂ ; variable (l / min.) Time: 5 minutes The flow rate of SiH ₂ Cl ₂ was 0.005, 0.01, 0.05, 0.1, 0. 25
(L / min.). The growth rate was 2.8, respectively.
5.6, 28, 56, 140 nm / min. Met.

C) Temperature: 1150 ° C. Pressure: 760 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.25 (l /
min. ) Time: 13 minutes By this heat treatment, a single-crystal silicon layer having a thickness of about 2 µm was formed. 6) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single crystal silicon layers was measured by a Nomarski differential interference microscope. As a result, the crystal defects were occupied by the stacking faults. SiH
2.1 × 10 ² / cm ² when the flow rate of ₂ Cl ₂ is 0.005 (l / min.), 3.4 × 10 ² / cm ² when the flow rate is 0.01 (l / min.), 0.05 (l / mi
n. ) Is 1.1 × 10 ³ / cm ² , 0.1 (l /
min. )) Is 1.2 × 10 ³ / cm ² , 0.5
(L / min.), It was 1.2 × 10 ³ / cm ² . That is, the step b) is introduced and SiH ₂ Cl
₂ The flow rate of the gas is 0.05 to 0.01 (l / min.)
, The stacking fault density rapidly decreased, and the stacking fault density decreased to about 1/3 to 1/5. In addition, since the stacking fault density was almost the same as that of Example 1, it was found that the step c) did not contribute to the introduction of the defect. That is,
By combining the step (b) having a low growth rate with the step (c) having a high growth rate, the growth time can be reduced from about 1/25 to 1 in terms of the growth rate without increasing crystal defects.
/ 50 was able to be shortened. Example 3 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was performed by changing the conditions of the step b) for each wafer.

A) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) ) SiH ₄ ; Variable (l / min.) Time: 5 minutes The flow rate of SiH ₄ is 0.0 for each of five wafers.
05, 0.01, 0.05, 0.1, 0.5 (l / mi
n. ). The growth rates were 2.8, 5.6,
28, 56, 140 nm / min. Met.

C) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ / SiH ₄ ; 230 / 0.25 (l / mi)
n. ) Time: 13 minutes By this heat treatment, a single-crystal silicon layer having a thickness of about 2 µm was formed. 4) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single crystal silicon layers was measured by a Nomarski differential interference microscope. SiH
_When the flow rate of ₄ is 0.005 (l / min.), 2.1
× 10 ² / cm ² , in the case of 0.01 (l / min.), 3.4 × 10 ² / cm ² , and in the case of 0.05 (l / min.), 1.1 × 10 ³ / cm ^2. , 0.1 (l / mi
n. ) Is 1.2 × 10 ³ / cm ² , 0.5 (l /
min. )) Was 1.2 × 10 ³ / cm ² . That is, the step b) is introduced, and when the flow rate of the SiH ₄ gas falls from 0.05 to 0.01 (l / min.), The stacking fault density rapidly decreases, and the stacking fault density becomes about 1 /.
It decreased to 3 to 1/5. Example 4 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) Subsequently, the five wafers on which the porous silicon layers were formed were subjected to an oxidation treatment in an oxygen atmosphere at 400 degrees for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, only a silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside. 4) After exposing the five wafers to an HF aqueous solution diluted to 1.25% for about 30 seconds, the wafer was washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer. 5) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the conditions of the step b) for each wafer.

A) Temperature: 1100 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1100 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min. ) SiH ₄ ; Variable (l / min.) Time: 5 minutes The flow rate of SiH ₄ was adjusted and the growth rates were 2, 5,
10, 50, 140 nm / min. And

C) Temperature: 900 ° C. Pressure: 80 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.25 (l /
min. By this heat treatment, a single crystal silicon layer having a thickness of about 2 μm was formed. 6) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single-crystal silicon layers was measured by a Nomarski differential interference microscope. When the growth rate is 2 nm / min. 1 × 10 ² / cm ² for 5
nm / min. 3 × 10 ² / cm ² , 10 nm
/ Min. 5 × 10 ² / cm ² , 50 nm / m
in. 1.7 × 10 ³ / cm ² , 140 nm /
min. Was 1.6 × 10 ³ / cm ² .
That is, the step b) is introduced, and the growth rate is 50 to 1
0 nm / min. , The stacking fault density rapidly decreased, and the stacking fault density decreased to about 1/3 to 1/15. Further, when the cross sections of the substrates obtained in this example and example 2 were observed with a high-resolution scanning electron microscope, it was confirmed that the coarsening of the structure of the porous layer was suppressed.

Similarly, each of the present embodiment and the embodiment 2
B) when the growth rate is 5 nm / min. 5.6n
m / min. SIMS (Secondary Ion Mass Spectrometry)
Analysis of boron in the depth direction
In the case of the method described above, almost the entire area of the epitaxial silicon layer is
To 10¹⁸/ Cm^ThreeContained boron at concentrations exceeding
On the other hand, in the case of this embodiment, boron is porous silicon.
Diffuses only up to about 100 nm from the interface with
However, on the surface side, the boron concentration is 10 ^Fifteen/ Cm
^ThreeLow crystal defect density and Boron's porosity
At the same time, the suppression of their diffusion was realized. Example 5 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
-0.02Ωcm 5 inch (100) silicon wafer
Two pieces of c were prepared. 2) Mix 49% HF and ethyl alcohol at a ratio of 2: 1
5 inches in diameter with the silicon wafer as the anode in the solution
Facing the silicon wafer with the platinum plate as the cathode
It was installed in. The back surface of the silicon wafer is coated with platinum and solution.
To prevent conduction through
All surfaces of the recon wafer communicate with platinum through the solution
As described above, the coating was performed up to the end face of the wafer. The silicon wafer
Current density 10mA / cm between Eha and platinum^TwoFor 12 minutes
An electric current is applied to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This
Was performed one by one. One sheet with a porous layer
Take out the wafer and measure the porosity
Was about 20%. 3) Subsequently, the two wafers on which the porous silicon layer was formed
C is oxidized for 1 hour in a 400 ° C. oxygen atmosphere.
Was. This oxidation process forms only an oxide film of approximately 50 ° or less.
Oxidized only on the porous silicon surface and the side walls of the pores
Only a silicon film is formed, and a single-crystal silicon
Area is left. 4) The two wafers were placed in an aqueous HF solution diluted to 1.25%.
After exposing C for about 30 seconds, wash with water and form on the surface of the porous layer.
The formed ultra-thin silicon oxide film was removed. 5) Place the wafer in a CVD growth furnace and perform the following heat treatment
Was performed continuously.

A) Temperature: 1120 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1120 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) ) SiH ₂ Cl ₂ ; 0.005 (l / min.) Time: 5 minutes c) Temperature: 900 ° C. Pressure: 80 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.4 (l / m)
in. By this heat treatment, a single-crystal silicon layer having a thickness of about 0.25 μm was formed. The thickness of the formed single-crystal Si layer is measured by the Spectroreflectance method on the surface of the wafer.
When the entire area of the wafer was measured at approximately 100 lattice points at m intervals, the film thickness distribution was 252.2 nm ± 8.1 nm.
(3.2%).

The growth was carried out by omitting the step b) for one of the two wafers. 6) Subsequently, the two wafers are oxidized at 900 ° C. in a mixed atmosphere of oxygen and hydrogen to form a silicon oxide film 5 times.
It was formed to a thickness of 0 nm. 7) After the wafer was subjected to chemical cleaning used in a normal semiconductor process together with the second wafer having an oxide film formed on the surface, and the surfaces were gently brought into close contact with each other, the two adhered and integrated. Subsequently, a heat treatment at 800 ° C. for 2 hours was applied. Observation of these two sets of bonded wafers with an infrared camera showed that, when the step b) was omitted, several defective bonding locations were found at the wafer periphery. No spot was seen. 8) Next, the back side of the wafer having the porous silicon was ground to expose the porous silicon on the entire surface of the substrate.
Thereafter, when the wafer is immersed in a mixed solution of HF, H ₂ O ₂ and alcohol for about 2 hours, the porous silicon is etched away and the epitaxial silicon layer is transferred to the second substrate via a silicon oxide film. Was done. 9) This substrate was subjected to a heat treatment at 1000 ° C. for 6 hours in a 100% hydrogen atmosphere. 10) When the surface of the epitaxial silicon layer was thoroughly observed with a Nomarski differential interference optical microscope, 5) per wafer was omitted on the substrate where the step b) was omitted.
Approximately 0 pinholes and the voids were assumed to be formed by etching the silicon oxide film due to the penetration of the etchant into the bonding interface from here, but when the step b) was performed, Only two voids were observed.

When the film thickness was measured, it was 229.5 nm ± 8.0 nm (3.5%) over the entire surface of the wafer. In addition, when an electrode having ohmic contact was attached to each of the surface Si layer of the substrate and the supporting substrate, and current-voltage characteristics between the two electrodes were evaluated, no continuity was observed. Was confirmed. That is, no pinhole was present in the buried oxide film. Example 6 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) Subsequently, the five wafers on which the porous silicon layers were formed were subjected to an oxidation treatment in an oxygen atmosphere at 400 degrees for 1 hour. Since this oxidation process only forms an oxide film of approximately 50 ° or less, only a silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside. 4) After exposing the five wafers to an HF aqueous solution diluted to 1.25% for about 30 seconds, the wafer was washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer. 5) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the condition of the step b) for each wafer.

A) Temperature: 1100 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1100 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) ) SiH ₄ ; Variable (l / min.) Time: 5 minutes The flow rate of SiH ₄ was adjusted, and the growth rate was 2.5, respectively.
10, 50, 140 nm / min. And

C) Temperature: 900 ° C. Pressure: 80 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.25 (l /
min. By this heat treatment, a single crystal silicon layer having a thickness of about 2 μm was formed. 6) After forming an oxide film on the surface of the wafer, the wafer is subjected to chemical cleaning used in a normal semiconductor process together with a quartz glass substrate, and then the surface is exposed to oxygen plasma, washed with water, and then gently washed with each other. When they were brought into close contact with each other, they were adhered and integrated. Subsequently, a heat treatment at 300 ° C. for 2 hours was applied. 7) Next, the back side of the wafer having the porous silicon was ground to expose the porous silicon on the entire surface of the substrate.
Thereafter, when the wafer is immersed in a mixed solution of HF, H ₂ O ₂ and alcohol for about 2 hours, the porous silicon is etched away and the epitaxial silicon layer is transferred to the second substrate via a silicon oxide film. Was done. 8) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single-crystal silicon layers was measured by a Nomarski differential interference microscope. As a result, the crystal defects were occupied by stacking faults. When the growth rate is 2 nm / min. 1 × 10 ² / cm ² for 5
nm / min. 3 × 10 ² / cm ² , 10 nm
/ Min. 5 × 10 ² / cm ² , 50 nm / m
in. 1.7 × 10 ³ / cm ² , 140 nm /
min. Was 1.6 × 10 ³ / cm ² .
That is, the step b) is introduced, and the growth rate is 50 to 1
5 nm / min. , The stacking fault density rapidly decreased, and the stacking fault density decreased to about 1/3 to 1/15. Example 7 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Five 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the conditions of the step b) for each wafer.

A) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: Variable Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) SiH ₄ ; 0.005 (l / min.) Time: 5 minutes The temperature was 700, 750, 770,
800,900 ° C. The growth rate was 2.
8, 5.6, 28, 56, 140 nm / min. Met.

C) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ / SiH ₄ ; 230 / 0.25 (l / mi)
n. ) Time: 13 minutes By this heat treatment, a single-crystal silicon layer having a thickness of about 2 µm was formed. 4) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single crystal silicon layers was measured by a Nomarski differential interference microscope. When the temperature is 900 ° C., it is 2.1 × 10 ² / cm ² , when it is 800 ° C., it is 3.4 × 10 ³ / cm ² , and when it is 770 ° C., it is 1.
2 × 10 ⁵ / cm ² , 5 × 10 ⁵ / c at 750 ° C.
In the case of m ² and 700 ° C., it was 1.2 × 10 ⁶ / cm ² . That is, the step b) is introduced and the temperature is 770 ° C.
From 800 ° C., the stacking fault density rapidly decreased, and the stacking fault density decreased to about 1/3 to 1/1000. Example 8 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Six 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. An electric current was passed between the silicon wafer and platinum at a current density of 7 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 16%. 3) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

The growth was carried out by changing the conditions of the step a) for each wafer.

A) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) SiH ₄ ; Variable (l / min.) Time: 5 minutes Flow rate of SiH ₄ for five wafers Was varied to set the growth rate as follows. SiH ₄ flow rate 0.005, 0.01, 0.05, 0.1, 0.5
(L / min.), The growth rate was 2.8, respectively.
5.6, 28, 56, 140 nm / min. Met.

B) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ / SiH ₄ ; 230 / 0.25 (l / mi)
n. ) Time: 13 minutes By this heat treatment, a single-crystal silicon layer having a thickness of about 2 µm was formed. 4) The crystal defects were revealed by Secco etching, and the density of the crystal defects contained in these single crystal silicon layers was measured by a Nomarski differential interference microscope. S for heat treatment
iH ₄ flow rate is 0.005 l / min. 4 × 1
0 ² / cm ² , 0.01 l / min. 5 × 10
² / cm ² , 0.05 l / min. 1.5 × 1
0 ³ / cm ² , 0.1 l / min. 1.7 × 1
0 ³ / cm ² , 0.5 l / min. 1.7 × 1
0 ³ / cm ² . That is, the step a) is introduced, and the flow rate of the SiH ₄ gas is 0.05 to 0.01 l / m 2.
in. , The stacking fault density rapidly decreased, and the stacking fault density decreased to about 1/3 to 1/5. Example 9 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Three 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. A current was passed between the silicon wafer and platinum at a current density of 10 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 20%. 3) Subsequently, the two wafers on which the porous silicon layer was formed were oxidized for one hour in an oxygen atmosphere at 400 degrees. Since this oxidation process only forms an oxide film of approximately 50 ° or less, only a silicon oxide film is formed only on the surface of the porous silicon and on the side walls of the holes, and a single crystal silicon region remains inside. 4) The three wafers were exposed to an HF aqueous solution diluted to 1.25% for about 30 seconds, and then washed with water to remove the ultrathin silicon oxide film formed on the surface of the porous layer. 5) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

A) Temperature: 1120 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min.) Time: 7.5 minutes b) Temperature: 1120 ° C. Pressure: 80 Torr Gas: H ₂ ; 230 (l / min. ) SiH ₂ Cl ₂ ; 0.005 (l / min.) Time: 5 minutes c) Temperature: 900 ° C. Pressure: 80 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.4 (l / m)
in. By this heat treatment, a single-crystal silicon layer having a thickness of about 0.29 μm was formed.

The growth was performed by omitting the step b) for one of the two wafers. 6) Subsequently, these two wafers were exposed to a mixed atmosphere of oxygen and hydrogen at 900 ° C., and the single crystal silicon layer was oxidized to form a silicon oxide film having a thickness of 200 nm. 7) This wafer and the second Si wafer are subjected to chemical cleaning used in a normal semiconductor process, dipped in a dilute HF solution as a final chemical cleaning, rinsed with pure water, dried, and then gently washed with two wafers. When the surfaces of the wafers were brought into close contact with each other, they were adhered and integrated. Subsequently, heat treatment was performed at 1180 ° C. for 5 minutes. 8) Next, the back side of the wafer having the porous silicon was ground to expose the porous silicon on the entire surface of the substrate.
After accordingly, the wafer in a mixed solution of HF and H ₂ O ₂ 2
After a while, the porous silicon was etched and disappeared, and an epitaxial silicon layer having a thickness of about 0.2 μm was transferred to the second substrate via a silicon oxide film. 9) This substrate was subjected to a heat treatment at 100 ° C. for 4 hours in a 100% hydrogen atmosphere. 10) When the surface of the epitaxial silicon layer was thoroughly observed with a Nomarski differential interference optical microscope, 5) per wafer was omitted on the substrate where the step b) was omitted.
Approximately 0 pinholes and the voids were assumed to be formed by etching the silicon oxide film due to the penetration of the etchant into the bonding interface from here, but when the step b) was performed, Only two voids were observed. Example 10 1) Boron was added as a p-type impurity, and the specific resistance was 0.01.
Three 5-inch (100) silicon wafers of −0.02 Ω · cm were prepared. 2) In a solution in which 49% HF and ethyl alcohol were mixed at a ratio of 2: 1, the silicon wafer was set as an anode and a platinum plate having a diameter of 5 inches was set as a cathode so as to face the silicon wafer. The back surface of the silicon wafer was coated so as not to conduct with the platinum through the solution, while the surface of the silicon wafer was coated up to the end surface of the wafer so that the entire surface was conductive with the platinum through the solution. An electric current was passed between the silicon wafer and platinum at a current density of 7 mA / cm ² for 12 minutes to anodize the silicon wafer (Anodiz
e), the surface layer was 12 μm thick porous silicon. This anodization was performed one by one. One wafer on which the porous layer was formed was taken out, and the porosity was measured to be about 16%. 3) The wafer was placed in a CVD growth furnace, and the following heat treatment was continuously performed.

A) Temperature: 900 ° C. Pressure: 20 Torr Gas: H ₂ ; 230 (l / min.) SiH ₄ ; 0.005 (l / min.) Time: 5 minutes b) Temperature: 900 ° C. Pressure: 80 Torr gas : H ₂ / SiH ₂ Cl ₂ ; 230 / 0.4 (l / m
in. By this heat treatment, a single crystal silicon layer having a thickness of about 0.30 μm was formed.

The growth was carried out by omitting the step a) for one of the two wafers. 4) Subsequently, these two wafers were exposed to a mixed atmosphere of oxygen and hydrogen at 900 ° C., and the single crystal silicon layer was oxidized to form a silicon oxide film having a thickness of 200 nm. 5) This wafer is subjected to chemical cleaning used in a normal semiconductor process together with the second Si wafer, dipped in a dilute HF solution as a final chemical cleaning, rinsed with pure water, dried, and then gently washed with two wafers. When the surfaces of the wafers were brought into close contact with each other, they were adhered and integrated. Subsequently, a heat treatment at 800 ° C. for 2 hours was applied. 6) Next, the back side of the wafer having the porous silicon was ground to expose the porous silicon on the entire surface of the substrate.
After accordingly, the wafer in a mixed solution of HF and H ₂ O ₂ 2
After a while, the porous silicon was etched and disappeared, and an epitaxial silicon layer having a thickness of about 0.2 μm was transferred to the second substrate via a silicon oxide film. 7) This substrate was subjected to a heat treatment at 1100 ° C. for 4 hours in a 100% hydrogen atmosphere. 8) The entire surface of the epitaxial silicon layer was observed with a Nomarski differential interference optical microscope. 3) On the substrate where the step a) was omitted, 1 wafer per wafer was used.
Approximately 00 pinholes and voids were assumed to have been formed by etching the silicon oxide film by infiltration of the etchant into the bonding interface from here, but when step a) was performed, Only two voids were observed.

Pressure: 20 Torr Gas: H ₂ / SiH ₂ Cl ₂ ; 230 / 0.25 (l /
min. Time: 5 minutes By this heat treatment, a single-crystal silicon layer having a thickness of about 2 μm was formed. 9) The crystal defects were made obvious by Secco etching, and the density of the crystal defects contained in these single-crystal silicon layers was measured by a Nomarski differential interference microscope. Is 9
In the case of 00 ° C., 2.1 × 10 ² / cm ² , in the case of 800 ° C., 3.4 × 10 ² / cm ² , in the case of 770 ° C., 1.2
× 10 ⁵ / cm ^2, 750 cases ℃, ⁵ × 10 5 / cm
^{2. At} 700 ° C., it was 1.2 × 10 ⁶ / cm ² . That is, the step b) was introduced, and when the temperature was changed from 770 ° C. to 800 ° C., the stacking fault density was rapidly reduced, and the stacking fault density was reduced to about 1/3 to 1/1000.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between a crystal defect density and a growth rate.

FIG. 2 is a schematic cross-sectional view of porous silicon heat-treated in hydrogen and a distribution diagram of the adsorption site density on the surface.

FIG. 3 is a view showing a step of forming an epitaxial silicon layer on porous silicon by a conventional method.

FIG. 4 is a diagram showing a process of forming an epitaxial silicon layer on porous silicon according to the present invention.

FIG. 5 is a diagram showing a relationship between a growth rate of a single crystal silicon layer and a time required to reach a predetermined pressure when a film thickness corresponding to a maximum pore diameter is grown.

FIG. 6 is a diagram showing a relationship between a growth rate and a residual hole density.

FIG. 7 is a schematic view showing one example of a method for producing a semiconductor substrate according to the present invention.

FIG. 8 is a schematic view showing one example of a method for producing a semiconductor substrate according to the present invention.

FIG. 9 is a schematic view showing one example of a method for producing a semiconductor substrate according to the present invention.

FIG. 10 is a schematic view showing an example of an anodization apparatus.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 single crystal silicon substrate 101 porous silicon 102 non-porous single crystal silicon layer 103 SiO ₂ layer 104 SiO ₂ layer 110 support substrate 1102 epitaxial silicon layer 1110 silicon substrate 1104 oxide film 1103 oxide film 1210 glass material

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-21338 (JP, A) JP-A-5-41354 (JP, A) JP-A-7-235651 (JP, A) JP-A-5-23551 217826 (JP, A) JP-A-5-217992 (JP, A) US Pat. No. 5,198,071 (US, A) YONEHARA T. et al. , "Epitaxial layer transfer by bond and etch back of porous Si," Applied Physics Letters, Vol. 64, no. 16, 1994, pp. 2108-2110 VESCAN L. et al. , "Low-pressure vapor-phase epitaxy of silicon on porous silicon," Materials Letters, Vol. 7, No.3, 1988, pp. 94-98 (58) Field surveyed (Int. Cl. ⁷ , DB name) C30B 1/00-35/00 CA (STN) JICST file (JOIS) WPI (DIALOG)

Claims (67)

(57) [Claims] In a method for manufacturing a semiconductor substrate having a single-crystal silicon layer on a porous silicon layer, the growth rate of the single-crystal silicon layer is controlled in an atmosphere containing at least a silicon source gas and a hydrogen gas. The single crystal silicon layer is controlled by controlling the residual pore density on the crystal growth surface to be less than 1000 / cm ² when the single crystal silicon layer has grown to a thickness corresponding to the diameter of the pores of the porous silicon layer. A method for producing a semiconductor substrate, which comprises growing. 2. A method for manufacturing a semiconductor substrate having a single-crystal silicon layer on a porous silicon layer, wherein the growth rate of the single-crystal silicon layer is determined by determining whether the single-crystal silicon layer has a pore diameter of the porous silicon layer. The single crystal silicon layer is grown at a first growth rate at which the residual hole density on the crystal growth surface when growing to a layer thickness corresponding to the following is less than 1000 / cm ² , and then higher than the first growth rate A method for manufacturing a semiconductor substrate, comprising growing the single crystal silicon layer at a second growth rate. 3. A step of preparing a first member having a single-crystal silicon layer on a porous silicon layer, wherein the first member and the second member are arranged such that the single-crystal silicon layer is located inside. A method for manufacturing a semiconductor substrate, comprising: a step of bonding, a step of forming a bonded structure, and a step of removing the porous silicon layer, wherein the single crystal is formed in an atmosphere containing at least a silicon source gas and a hydrogen gas. The growth rate of the silicon layer is set such that the residual pore density of the crystal growth surface when the single crystal silicon layer is grown to a layer thickness corresponding to the diameter of the pores of the porous silicon layer is 1000 /.
A method for producing a semiconductor substrate, comprising growing the single crystal silicon layer while controlling the thickness to be less than cm ² . 4. A step of preparing a first member having a single crystal silicon layer on a porous silicon layer, wherein the first member and the second member are arranged such that the single crystal silicon layer is located inside. A method of manufacturing a semiconductor substrate, comprising: a step of bonding, a step of forming a bonded structure, and a step of removing the porous silicon layer, wherein the growth rate of the single crystal silicon layer Growing the single crystal silicon layer at a first growth rate at which the residual hole density on the crystal growth surface when growing to a layer thickness corresponding to the diameter of the hole in the silicon layer is less than 1000 / cm ² ; A method for manufacturing a semiconductor substrate, comprising: growing the single crystal silicon layer at a second growth rate higher than the first growth rate. The 5. single-crystal silicon layer, nonporous method for manufacturing a semiconductor substrate according to any one of claims 1 to 4 is a single crystal silicon layer. 6. The semiconductor according to claim 1, wherein said single crystal silicon layer is grown by supplying a source gas into a crystal growth furnace provided with said porous silicon layer. A method for manufacturing a substrate. 7. The raw material gas is silane, dichlorosilane,
7. The method according to claim 6, wherein the method is selected from trichlorosilane, tetrachlorosilane, and disilane. 8. The method for manufacturing a semiconductor substrate according to claim 1, wherein the porous silicon layer is heated in a non-oxidizing atmosphere before growing the single crystal silicon layer. 9. The method according to claim 8, wherein the non-oxidizing atmosphere is a hydrogen atmosphere. 10. The method according to claim 1, wherein prior to growing said single crystal silicon layer,
The method for manufacturing a semiconductor substrate according to claim 1, further comprising a step of removing a natural oxide film. 11. The method according to claim 1, wherein prior to growing the single crystal silicon layer,
The semiconductor substrate according to any one of claims 1 to 4, further comprising a step of forming an ultrathin oxide film on the side wall of the hole of the porous silicon layer and a step of removing the oxide film on the surface of the porous silicon layer. The method of manufacturing the material. 12. The method according to claim 1, wherein prior to growing said single crystal silicon layer,
Forming an oxide film on the side walls of the pores of the porous silicon layer,
The method of manufacturing a semiconductor substrate according to claim 1, further comprising a heat treatment step in an atmosphere containing hydrogen. 13. The growth rate is 20 nm / min. The method for producing a semiconductor substrate according to any one of claims 1 to 12, wherein: 14. The method according to claim 1, wherein the step of growing the single crystal silicon layer includes heating the porous silicon layer to 900 ° C. or higher.
The method for producing a semiconductor substrate according to claim 4. 15. The method according to claim 1, wherein the diameter of the pore is a maximum pore diameter of the porous silicon layer. 16. The method of manufacturing a semiconductor substrate according to claim 3, wherein the bonded structure is formed by bonding the first member and the second member via an insulating layer. 17. The method according to claim 16, wherein the insulating layer is a silicon oxide layer formed on the first member. 18. The method according to claim 16, wherein the insulating layer is formed on a surface of the second member. 19. The method according to claim 16, wherein the insulating layer is formed by oxidizing a surface of the single crystal silicon layer on the first member.
3. The method for producing a semiconductor substrate according to item 1. 20. The insulating layer according to claim 16, wherein the surface of the single crystal silicon substrate as the second member is thermally oxidized.
3. The method for producing a semiconductor substrate according to item 1. 21. The method according to claim 3, wherein the second member is a single crystal silicon substrate. 22. The method according to claim 3, wherein the second member is made of glass. 23. Removal of the porous silicon layer, a method of manufacturing a semiconductor substrate according to claim 3 or claim 4 is performed using an etchant containing hydrofluoric acid. 24. Removal of the porous silicon layer, manufacturing side of the semiconductor substrate according to claim 3 or claim 4 is performed using an etchant containing hydrofluoric acid and hydrogen peroxide
Law . 25. The method for manufacturing a semiconductor substrate according to claim 1, wherein the residual pore density is measured by a gas adsorption method or observation with an ultra-high resolution scanning electron microscope. 26. When growing the single crystal silicon layer at the first growth rate, silane (SiH ₄ ) is used as a silicon source gas, and when growing at the second growth rate, chlorosilane (SiH ₂ Cl ₂₎ the method of manufacturing a semiconductor substrate according to claim 2 or claim 4 is used as the silicon source gas. 27. When growing the single crystal silicon layer at the first growth rate, dichlorosilane (SiH ₂ Cl
₂ ) is used as a silicon source gas, and when growing at the second growth rate, dichlorosilane (SiH ₂ C
5. The method according to claim _{2, wherein} l ₂ ) is used as a silicon source gas. 28. When growing the single crystal silicon layer at the first growth rate, silane (SiH ₄ ) is used as a silicon source gas, and when growing at the second growth rate, silane (SiH ₄ ) is used. 5. The method according to claim 2, wherein (SiH ₄ ) is used as a silicon source gas. 29. The method according to claim 29, wherein the growth rate is 10 nm / min. The method for producing a semiconductor substrate according to claim 1 or 3, which is: 30. The method according to claim 30, wherein the first growth rate is 10 nm / mi.
n. The method for producing a semiconductor substrate according to claim 2 or 4, which is as follows. 31. The growth of the single-crystal silicon layer is performed by 10 T
The method is performed under a pressure of orr to 760 Torr.
The method for producing a semiconductor substrate according to claim 4. 32. The method according to claim 1, wherein the growth of the single-crystal silicon layer is performed at a temperature of 800 ° C. or more. 33. Prior to growing the single crystal silicon layer, the porous silicon layer is heat-treated in an atmosphere containing hydrogen, and the growth of the single crystal silicon layer and the heat treatment in an atmosphere containing hydrogen are performed. The method of manufacturing a semiconductor substrate according to claim 1, wherein the method is performed continuously using the same CVD growth furnace. 34. A method for manufacturing a semiconductor substrate having a single-crystal silicon layer on a porous silicon layer, comprising the steps of preparing a substrate having a porous silicon layer, and including at least a silicon source gas and a hydrogen gas 20 nm / min. On the porous silicon layer in an atmosphere. A method for manufacturing a semiconductor substrate, comprising a step of growing the single-crystal silicon layer at the following growth rate. 35. A method of manufacturing a semiconductor substrate having a single-crystal silicon layer on a porous silicon layer, comprising the steps of: preparing a substrate having a porous silicon layer; Manufacturing a semiconductor substrate having the following steps of growing the single-crystal silicon layer at a first growth rate and growing the single-crystal silicon layer at a second growth rate higher than the first growth rate: Method. 36. A step of preparing a first substrate having a porous silicon layer, the method comprising: forming a first substrate on a porous silicon layer in an atmosphere containing at least a silicon source gas and hydrogen gas;
/ Min. Growing a single crystal silicon layer at the following growth rate, bonding the first substrate and the second substrate such that the single crystal silicon layer is located inside, and forming a bonded structure; And a method for producing a semiconductor substrate, comprising a step of removing the porous silicon layer. 37. A step of preparing a first substrate having a porous silicon layer, the method comprising: forming a first substrate having a thickness of 20 nm / m on the porous silicon layer.
in. Growing a single-crystal silicon layer at a first growth rate below, growing a single-crystal silicon layer at a second growth rate faster than the first growth rate, Bonding a substrate and the single-crystal silicon layer so that the single-crystal silicon layer is located inside, forming a bonded structure,
And a method for producing a semiconductor substrate, comprising a step of removing the porous silicon layer. 38. The semiconductor substrate according to claim 34, further comprising a step of forming an oxide film on a hole wall of the porous silicon layer before growing the single crystal silicon layer. Production method. 39. The semiconductor substrate according to claim 34, further comprising a step of removing an oxide film on an outer surface of the porous silicon layer before growing the single crystal silicon layer. Production method. 40. The semiconductor substrate according to claim 34, further comprising a step of heat-treating the porous silicon layer in an atmosphere containing hydrogen before growing the single-crystal silicon layer. Production method. 41. The method according to claim 34, further comprising the step of forming an oxide film on the pore walls of the porous silicon layer and removing the oxide film on the outer surface of the porous silicon layer before growing the single crystal silicon layer. The method for producing a semiconductor substrate according to any one of claims 37 to 37. 42. The method according to claim 34, further comprising a step of forming an oxide film on the hole walls of the porous silicon layer and subjecting the porous silicon layer to a heat treatment in an atmosphere containing hydrogen before growing the single crystal silicon layer. The method for producing a semiconductor substrate according to any one of claims 37 to 37. 43. The method according to claim 34, wherein the single crystal silicon layer is a non-porous single crystal silicon layer . 44. The semiconductor according to claim 34, wherein said single crystal silicon layer is grown by supplying a source gas into a crystal growth furnace provided with said porous silicon layer. A method for manufacturing a substrate. 45. The method according to claim 44, wherein the source gas is selected from silane, dichlorosilane, trichlorosilane, tetrachlorosilane, and disilane. 46. The method according to claim 46, further comprising:
The method for manufacturing a semiconductor substrate according to any one of claims 34 to 37, wherein the porous silicon layer is heated in a non-oxidizing atmosphere. 47. The method according to claim 46, wherein the non-oxidizing atmosphere is a hydrogen atmosphere. 48. The first growth rate is 10 nm / mi.
n. The method for producing a semiconductor substrate according to any one of claims 34 to 37, which is as follows. 49. The first growth rate is 2 nm / min.
The method for producing a semiconductor substrate according to any one of claims 34 to 37, which is as follows. 50. The method according to claim 3, wherein the step of growing the single crystal silicon layer includes heating the porous silicon layer to 900 ° C. or more.
The method for producing a semiconductor substrate according to any one of claims 4 to 37. 51. The semiconductor substrate according to claim 36, wherein the bonded structure is formed by bonding the first substrate and the second substrate via an insulating layer. Production method. 52. The method according to claim 51, wherein the insulating layer is a silicon oxide layer formed on the first substrate . 53. The method according to claim 51, wherein the insulating layer is formed on the surface of the second substrate . 54. The insulating layer is formed by oxidizing a surface of the single crystal silicon layer on the first substrate .
3. The method for producing a semiconductor substrate according to item 1. 55. The insulating layer is formed by thermally oxidizing a surface of a single crystal silicon substrate as the second substrate .
3. The method for producing a semiconductor substrate according to item 1. 56. The method according to claim 36, wherein the second substrate is a single crystal silicon substrate. 57. The method according to claim 36, wherein the second substrate is made of glass. 58. Removal of the porous silicon layer, a method of manufacturing a semiconductor substrate according to claim 36 or claim 37 carried out using an etchant containing hydrofluoric acid. 59. The method according to claim 36, wherein the removal of the porous silicon layer is performed using an etching solution containing hydrofluoric acid and hydrogen peroxide .
Construction method . 60. The method according to claim 35, wherein a source gas used for growing the single crystal silicon layer at the first growth rate and the second growth rate is different. 61. When the single crystal silicon layer is grown at the first growth rate, silane (SiH ₄ ) is used as a silicon source gas, and when the single crystal silicon layer is grown at the second growth rate, disilane is used. chlorosilane (SiH ₂ Cl ₂₎ the method of manufacturing a semiconductor substrate according to claim 35 or claim 37 used as the silicon source gas. 62. When growing the single crystal silicon layer at the first growth rate, dichlorosilane (SiH ₂ Cl
₂ ) is used as a silicon source gas, and when growing at the second growth rate, dichlorosilane (SiH ₂ C
38. The method according to claim 35, wherein l ₂ ) is used as a silicon source gas. 63. When growing the single crystal silicon layer at the first growth rate, silane (SiH ₄ ) is used as a silicon source gas, and when growing at the second growth rate, silane (SiH ₄ ) is used. the method of manufacturing a semiconductor substrate according to claim 35 or claim 37 using (SiH ₄₎ as the silicon source gas. 64. The growth of the single-crystal silicon layer is performed by 10 T
35. The process is performed under a pressure of from about rr to about 760 Torr.
The method for producing a semiconductor substrate according to any one of claims 37 to 37. 65. The method according to claim 34, wherein the growth of the single-crystal silicon layer is performed at a temperature of 800 ° C. or higher. 66. Prior to the growth of the single crystal silicon layer, the porous silicon layer is heat-treated in an atmosphere containing hydrogen, and the growth of the single crystal silicon layer and the heat treatment in an atmosphere containing hydrogen are performed. The method for producing a semiconductor substrate according to any one of claims 34 to 37, wherein the method is performed continuously using the same CVD growth furnace. 67. A semiconductor substrate manufactured by using the method according to any one of claims 1 to 66.