CN115206811A

CN115206811A - Heterojunction structure and preparation method

Info

Publication number: CN115206811A
Application number: CN202110379342.9A
Authority: CN
Inventors: 欧欣; 瞿振宇; 游天桂; 徐文慧
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2022-10-18

Abstract

The invention provides a heterogeneous bonding structure and a preparation method thereof, wherein a structure loose layer is formed in a heterogeneous substrate by carrying out ion implantation and annealing on the heterogeneous substrate so as to accommodate water vapor generated at an interface in a hydrophilic bonding process and ions and gas molecules at a bonding interface in an ion beam stripping and transferring process, so that the foaming problem caused by water vapor aggregation at the bonding interface in the hydrophilic bonding process and the electric field clustering and foaming problems caused by ion implantation aggregation at the bonding interface when semiconductor material heterogeneous integration is carried out by utilizing the ion beam stripping and transferring technology are solved, the heterogeneous bonding process is optimized, the interface quality of the heterogeneous substrate and the bonding material is improved, the reliability of a device manufactured by utilizing the heterogeneous bonding structure is improved, and the development significance of the device manufactured by the heterogeneous bonding structure is great.

Description

Heterojunction structure and preparation method

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a heterojunction structure and a preparation method thereof.

Background

With the rapid development of the electronic information industry, the demand for semiconductors is no longer limited to the conventional semiconductor material technology, and silicon (Si) -based semiconductor materials have been developed to substitute for gallium arsenide (GaAs) and indium phosphide (InP)Second generation semiconductor materials of the table, and gradually toward silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga) ₂ O ₃ ) And the development of the third generation wide bandgap semiconductor material. Although silicon material is still one of the most important semiconductor materials in the electronic information industry today, indirect band gap, narrow forbidden band width, low breakdown electric field and other factors limit the application of silicon in high frequency, high power devices, optoelectronic fields and the like. In addition, silicon has approached the limits of device performance and device size over half a century of development, but at the same time, achieving reliable compound semiconductor-based transistors at the device level still faces difficulties such as finding high quality gate insulators, forming low resistance contacts, and fabricating p-type transistors that efficiently conduct holes. It is therefore important to realize heterogeneous integration of compound semiconductors with other semiconductor materials.

The main ways of achieving heterogeneous integration of compound semiconductors with other semiconductor materials can now be divided into epitaxy-based methods and bonding-based methods. For the epitaxy-based approach, the quality of the compound semiconductor material that is epitaxial is limited due to the large lattice mismatch and thermal mismatch of the compound semiconductor and silicon itself. The heterogeneous integration of the compound semiconductor and other semiconductor materials can be realized based on wafer bonding and thin layer transfer processes, but in the hydrophilic bonding process, water vapor is gathered at a bonding interface, so that the bonding strength is influenced by the bubbling phenomenon; in an ion beam stripping and transferring process, namely an intelligent cutting process, the method is a technology which can be used for realizing heterogeneous integration of a compound semiconductor and other semiconductor materials, and has the following advantages:

(a) Almost has no requirement on the lattice matching degree, and the selection of the film material and the substrate material is more flexible;

(b) The ion beam stripped and transferred film is part of a single crystal bulk material being stripped, having the single crystal mass of the bulk material;

(c) The stripped single crystal bulk can be recycled, and materials are fully utilized;

(d) Different high-quality single crystal films can be simultaneously integrated on the same substrate, the performance of each film material is not influenced by the preparation process, and the integration level and the design flexibility of the device are greatly improved.

However, no matter hydrophilic bonding, surface activation bonding, metal bonding or anodic bonding is used, the aggregation of implanted ions can occur at the bonding interface, and the aggregated implanted ions can generate an electric field crowding phenomenon at the interface on one hand, so that the whole device is easier to break down; on the other hand, the concentrated implanted ions form H at the interface ₂ Or He gas molecules, affect the bonding strength and even blister formation may occur in severe cases, resulting in peeling of the bonded film from the substrate.

Therefore, the heterogeneous bonding structure and the preparation method are necessary.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a hetero-bonding structure and a method for manufacturing the same, which are used to solve the above-mentioned problems related to the bonding quality at the bonding interface in the hetero-bonding process in the prior art.

To achieve the above and other related objects, the present invention provides a method for fabricating a heterojunction structure, comprising the steps of:

providing a bonding material wafer, wherein one surface of the bonding material wafer is a polishing surface;

providing a heterogeneous substrate, wherein one surface of the heterogeneous substrate is a polished surface;

performing ion injection from the polished surface of the heterogeneous substrate to form a doped layer in the heterogeneous substrate;

bonding the polished surface of the bonding material wafer with the polished surface of the heterogeneous substrate to prepare a composite structure;

and annealing the composite structure, wherein the doped ions in the doped layer react with the heterogeneous substrate to be converted into a structure loose layer to obtain a heterogeneous bonding structure, and the heterogeneous bonding structure comprises the heterogeneous substrate, the structure loose layer and a bonding material wafer which are sequentially stacked.

Optionally, forming a doped layer in said foreign substrateThe ion implantation comprises one or a combination of O ion implantation and N ion implantation; the energy of the ion implantation is 15 keV-190 keV, and the dosage is 1 x 10 ¹⁶ ions/cm ² ～7×10 ¹⁷ ions/cm ² The temperature is 20-200 ℃.

Optionally, the doped layer is formed to have a thickness of 2nm to 100nm.

Optionally, the structure loosening layer comprises one or a combination of a silicon oxide layer and a silicon nitride layer.

Optionally, the annealing treatment of the composite structure is performed under a vacuum environment or a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, the annealing temperature is 400-1100 ℃, and the annealing time is 1 min-240 h.

Optionally, the bonded material wafer comprises one of a gallium oxide wafer, a gallium nitride wafer, a silicon carbide wafer, an indium phosphide wafer, a gallium arsenide wafer, a gallium antimonide wafer; the foreign substrate includes one of a silicon substrate and a silicon carbide substrate.

Optionally, the bonding method includes one of surface activation bonding, metal bonding, hydrophilic bonding, and anodic bonding.

Optionally, the bonding is performed in a vacuum of 1 × 10 ^-7 Pa～5×10 ^-7 Pa, pressure of 10-20 MPa, and temperature of 25 deg.C.

Optionally, the bonded material wafer comprises a defect bonded material wafer having a defect layer formed using ion implantation; the defect bonding material wafer is peeled from the defect layer while the annealing treatment is performed.

The invention also provides a heterojunction structure prepared by the preparation method of the heterojunction structure as claimed in any one of claims 1 to 9.

As described above, according to the hetero-bonding structure and the manufacturing method of the present invention, the ion implantation and annealing are performed on the hetero-substrate to form the structure loose layer in the hetero-substrate to accommodate the water vapor generated at the interface during the hydrophilic bonding process and the ions and gas molecules at the bonding interface during the ion beam stripping and transferring process, thereby solving the bubbling problem caused by the water vapor accumulation at the bonding interface during the hydrophilic bonding process and the electric field crowding and bubbling problem caused by the ion implantation accumulation at the bonding interface during the hetero-integration of the semiconductor material by the ion beam stripping and transferring process, optimizing the hetero-bonding process, improving the interface quality between the hetero-substrate and the bonding material, and the reliability of the device manufactured by using the hetero-bonding structure, which is significant for the development of the device manufactured by the hetero-bonding structure.

Drawings

Fig. 1 is a flow chart illustrating a process for fabricating a heterojunction structure according to a first embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a bonding material wafer according to a first embodiment of the invention.

Fig. 3 is a schematic structural diagram of a foreign substrate provided in the first embodiment of the invention.

Fig. 4 is a schematic structural diagram illustrating a doped layer formed by ion implantation on a foreign substrate according to a first embodiment of the invention.

Fig. 5 is a schematic structural diagram of a composite structure according to a first embodiment of the present invention.

Fig. 6 is a schematic structural diagram illustrating a heterojunction structure formed after an annealing process is performed according to a first embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a defect bonded material wafer according to a second embodiment of the present invention.

Fig. 8 is a schematic structural diagram illustrating the formation of a doped layer by ion implantation on a foreign substrate according to a second embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a composite structure prepared in the second embodiment of the present invention.

Fig. 10 is a schematic structural diagram illustrating a heterojunction structure formed after annealing treatment according to a second embodiment of the present invention.

Description of the element reference

100. Wafer of bonding material

Polished surface of 100a bonding material wafer

200. 210 foreign substrate

200a, 210a heterogeneous substrate polishing surface

300. 310 doped layer

400. 410 loose layer

110. Wafer of defect bonding material

110a polished surface of a wafer of defect bonding material

120. Defective layer

130. Film of bonding material

Detailed Description

The inventors have discovered that heterointegration of compound semiconductor materials with other semiconductor materials can provide additional degrees of freedom in fabrication and design, improve device performance, and reduce manufacturing costs. However, when hydrophilic bonding is used, water vapor is collected at the bonding interface to cause foaming phenomenon, which affects the bonding quality. When ion beam stripping and transferring technology is used for heterogeneous integration, no matter what bonding mode is used, the concentration of implanted ions occurs at the bonding interface, and further the phenomena of electric field cluster and film bubbling and falling are caused.

Therefore, the inventors propose a hetero-bonding structure and a manufacturing method for solving the problem of bubbling caused by water vapor accumulation at the bonding interface during bonding using hydrophilicity and the problem of electric field crowding and bubbling caused by ion implantation accumulation at the bonding interface when hetero-integration is performed using ion beam lift-off and transfer techniques.

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, this embodiment provides a method for preparing a heterojunction structure, including the following steps:

performing ion implantation from the polished surface of the heterogeneous substrate to form a doped layer in the heterogeneous substrate;

bonding the polished surface of the bonding material wafer with the polished surface of the foreign substrate to prepare a composite structure;

First, referring to fig. 2, a bonding material wafer 100 is provided, and one surface of the bonding material wafer 100 is a polishing surface 100a.

As an example, the bonding material wafer 100 may include one of a gallium oxide wafer, a gallium nitride wafer, a silicon carbide wafer, an indium phosphide wafer, a gallium arsenide wafer, and a gallium antimonide wafer.

Specifically, the size of the bonding material wafer 100 may be selected as desired, and may include, for example, 2 inches to 12 inches. The surface roughness of the polished surface 100a of the bonding material wafer 100 should be less than 1nm, such as 0.5nm, 0.2nm, etc., and the doping type of the bonding material wafer 100 may include n-type doping, p-type doping, or intrinsic undoped, which may be specifically selected as required.

Next, referring to fig. 3, a foreign substrate 200 is provided, one surface of the foreign substrate 200 being a polished surface 200a.

As an example, the foreign substrate 200 may include one of a silicon substrate and a silicon carbide substrate.

Specifically, the size of the foreign substrate 200 may be selected according to a requirement, and may include 2 inches to 12 inches, the surface roughness of the polished surface 200a of the foreign substrate 200 should be less than 1nm, such as 0.5nm, 0.2nm, and the like, and the foreign substrate 200 may include an n-type doped foreign substrate, a p-type doped foreign substrate, or an intrinsic foreign substrate, and may be selected according to a requirement. The heterogeneous substrate 200 is not limited to the silicon substrate and the silicon carbide substrate, and may be a material of a bulk layer of an amorphous structure formed by ion implantation.

Next, referring to fig. 4, ion implantation is performed from the polished surface 200a of the foreign substrate 200 to form a doped layer 300 in the foreign substrate 200.

As an example, the ion implantation includes one or a combination of O ion implantation and N ion implantation.

As an example, the ion implantation energy is 15keV to 190keV and the dose is 1 × 10 ¹⁶ ions/cm ² ～7×10 ¹⁷ ions/cm ² The temperature is 20-200 ℃.

Illustratively, the doped layer 300 is formed to have a thickness of 2nm to 100nm.

Specifically, the arrows in fig. 4 indicate the direction of ion implantation. In one example, a single type of ion implantation, i.e., either O ion implantation or N ion implantation, may be performed from the polished side 200a of the foreign substrate 200. When the implanted ions are O ions, the O ions may enter the foreign substrate 200 to form the doped layer 300 and cause lattice distortion, so that a silicon oxide structure relaxed layer is generated in the subsequent annealing process, wherein the depth of forming the doped layer 300 is determined by the energy of ion implantation, and the O ion concentration in the doped layer 300 is determined by the dose of ion implantation. When the implanted ions are N ions, the N ions can enterAnd forming the doped layer 300 into the foreign substrate 200, and causing lattice distortion so as to facilitate the formation of a silicon nitride structure relaxed layer in a subsequent annealing process, wherein the depth of forming the doped layer 300 is determined by the energy of ion implantation, and the N ion concentration of the doped layer 300 is determined by the dose of ion implantation. In another example, co-implantation of two types of ions may also be performed from the polished surface 200a of the foreign substrate 200, that is, the implanted ions are O ions and N ions, wherein the O ions and the N ions form corresponding doped layers respectively and are coupled with each other to cause larger lattice distortion, so that a looser silicon oxide structure loose layer/silicon nitride structure loose layer may be formed in the subsequent annealing process, and moisture generated at the interface during hydrophilic bonding and ions and gas molecules at the bonding interface during ion beam stripping and transferring processes may be better accommodated, thereby solving the problem of bubbling caused by moisture aggregation at the bonding interface during hydrophilic bonding and the problem of electric field crowding and bubbling caused by ion aggregation at the bonding interface during heterogeneous integration of semiconductor materials by ion beam stripping and transferring processes, and improving the quality of the bonding interface. Wherein the energy of the ion implantation can be 15keV, 50keV, 100keV, 150keV, 190keV, etc., and the dosage can be 1 × 10 ¹⁶ ions/cm ² 、5×10 ¹⁶ ions/cm ² 、1×10 ¹⁷ ions/cm ² 、5×10 ¹⁷ ions/cm ² 、7×10 ¹⁷ ions/cm ² Etc., the temperature can be 20 ℃, 50 ℃, 100 ℃, 200 ℃ and the like; the doped layer 300 may be formed to have a thickness of 2nm, 10nm, 50nm, 100nm, etc. The type, energy, dose, temperature of the implanted ions, and the thickness of the doped layer 300 formed may be selected according to the needs, and are not limited herein.

Next, referring to fig. 5, the polished surface 100a of the bonding material wafer 100 is bonded to the polished surface 200a of the foreign substrate 200 to prepare a composite structure.

As an example, the bonding method includes one of surface activation bonding, metal bonding, hydrophilic bonding, and anodic bonding.

By way of example, said bondingVacuum degree of 1X 10 ^-7 Pa～5×10 ^-7 Pa, pressure of 10-20 MPa, and temperature of 25 deg.C.

Specifically, the bonding may have a degree of vacuum of 1 × 10 ^-7 Pa、2×10 ^-7 Pa、5×10 ^-7 Pa, etc. the pressure can be 10MPa, 15MPa, 20MPa, etc., and can be specifically selected according to the needs, and through the bonding, the bonding material wafer 100 and the heterogeneous substrate 200 can be bonded well, so as to realize heterogeneous integration.

Next, referring to fig. 6, the composite structure is subjected to an annealing process, wherein the doped ions in the doped layer 300 react with the foreign substrate 200 to be converted into a structure-loosening layer 400, so as to obtain a hetero-bonded structure, which includes the foreign substrate 200, the structure-loosening layer 400, and the bonding material wafer 100 stacked in this order.

As an example, the process conditions for annealing the composite structure include performing the annealing in a vacuum environment or in a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, wherein the annealing temperature is 400 ℃ to 1100 ℃, and the annealing time is 1min to 240h.

As an example, the structure loosening layer 400 includes one or a combination of silicon oxide and silicon nitride.

Specifically, in the annealing process, the doped ions in the doped layer 300 in the foreign substrate 200 may diffuse, and under a suitable annealing condition, the doped ions may react with the foreign substrate 200 to generate, for example, a silicon oxide layer, a silicon nitride layer, or other amorphous structure layer as the structure loosening layer 400, where the structure loosening layer 400 is looser than the base structure of the foreign substrate 200 and may accommodate water vapor generated at the bonding interface during the hydrophilic bonding process and ions and gas molecules at the bonding interface during the ion beam stripping and transferring process, thereby preventing the phenomena of electric field crowding and bonding interface blistering, avoiding the occurrence of bonding debonding, and improving the quality of the bonding interface. The annealing temperature can be 400 ℃, 500 ℃, 600 ℃, 800 ℃, 1000 ℃, 1100 ℃ and the like, the annealing time can be 1min, 30min, 1h, 10h, 100h, 240h and the like, and the annealing temperature can be specifically selected according to the needs.

Referring to fig. 6, the present embodiment further provides a hetero-bonding structure prepared by the above preparation method of the hetero-bonding structure, wherein the hetero-bonding structure includes the hetero-substrate 200, the structure relaxed layer 400, and the bonding material wafer 100, which are sequentially stacked, and the materials and the preparations of the hetero-substrate 200, the structure relaxed layer 400, and the bonding material wafer 100 are not described herein again.

Example two

Referring to fig. 7 to 10, the present embodiment provides another heterojunction structure and a manufacturing method thereof, and the difference between the present embodiment and the first embodiment is mainly that: the bonded material wafer includes a defect bonded material wafer 110 having a defect layer 120 formed using ion implantation.

First, referring to fig. 7, one surface of the defect bonding material wafer 110 is a polished surface 110a, and a defect layer 120 is formed at a predetermined depth, wherein the defect bonding material wafer 110 may include one of a gallium oxide wafer, a gallium nitride wafer, a silicon carbide wafer, an indium phosphide wafer, a gallium arsenide wafer, and a gallium antimonide wafer. The defect layer 120 may be formed by performing ion implantation using, for example, one or a combination of H ion implantation and He ion implantation, and the defect layer 120 has a predetermined depth, for example, 200nm to 500nm. The specific type and configuration of the defective bonding material wafer 110 is not overly limited herein.

Then, referring to fig. 8, in the same manner as in the first embodiment, a foreign substrate 210 is provided, and one surface of the foreign substrate 210 is a polished surface 210a, wherein reference may be made to the first embodiment regarding the type of the foreign substrate 210, which is not described herein again.

Next, referring to the first embodiment, ion implantation is performed from the polished surface 210a of the foreign substrate 210 to form the doped layer 310 in the foreign substrate 210, and detailed preparation is omitted here.

Next, referring to fig. 9, the polished surface 110a of the defect bonding material wafer 110 is bonded to the polished surface 210a of the foreign substrate 210 to prepare a composite structure.

Next, referring to fig. 10, the composite structure is annealed, wherein the dopant ions in the dopant 310 react with the foreign substrate 210 to transform into a structure-loose layer 410, resulting in a hetero-bonded structure.

As an example, when the annealing treatment is performed, the defect bonding material wafer 110 is preferably peeled off from the defect layer 120.

Specifically, when the annealing treatment is performed, the doping ions in the doping 310 and the foreign substrate 210 can react to be converted into the structure-loosening layer 410, and in particular, referring to the first embodiment, the defect bonding material wafer 110 can be peeled off from the defect layer 120 to form the hetero-bonded structure, which includes the foreign substrate 210, the structure-loosening layer 410 and the bonding material film 130 stacked in sequence, so that the process steps can be reduced, but not limited thereto, and the peeling process and the annealing treatment of the defect bonding material wafer 110 can be performed in steps, and are particularly, optionally, and not limited thereto. The parameters related to the annealing process may participate in the first embodiment, and are not described herein.

Referring to fig. 10, the present embodiment further provides a heterojunction structure, which is prepared by the preparation method of the heterojunction structure, wherein the heterojunction structure includes the foreign substrate 210, the structure relaxed layer 410, and the bonding material film 130, which are sequentially stacked, and details regarding the materials and the preparation of the foreign substrate 210, the structure relaxed layer 410, and the bonding material film 130 are not described herein.

In summary, according to the hetero-bonding structure and the preparation method of the hetero-bonding structure of the invention, the hetero-substrate is subjected to ion implantation and annealing to form a structure loose layer in the hetero-substrate so as to accommodate water vapor generated at the interface in the hydrophilic bonding process and ions and gas molecules at the bonding interface in the ion beam stripping and transferring process, thereby solving the problem of bubbling caused by water vapor accumulation at the bonding interface in the hydrophilic bonding process and the problem of electric field cluster and bubbling caused by ion accumulation at the bonding interface when the ion beam stripping and transferring technology is used for hetero-integration of semiconductor materials, optimizing the hetero-bonding process, improving the interface quality of the hetero-substrate and the bonding material, and the reliability of a device manufactured by using the hetero-bonding structure, and having great significance for the development of the device manufactured by the hetero-bonding structure.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for preparing a heterojunction structure is characterized by comprising the following steps:

2. The method of preparing a heterojunction structure according to claim 1, wherein: the ion implantation for forming the doped layer in the foreign substrate comprises one or a combination of O ion implantation and N ion implantation; the energy of the ion implantation is 15 keV-190 keV, and the dosage is 1 x 10 ¹⁶ ions/cm ² ～7×10 ¹⁷ ions/cm ² The temperature is 20-200 ℃.

3. The method of preparing a heterojunction structure according to claim 1, wherein: the thickness of the formed doping layer is 2 nm-100 nm.

4. The method of preparing a heterojunction structure according to claim 1, wherein: the structure loose layer comprises one or a combination of a silicon oxide layer and a silicon nitride layer.

5. The method of preparing a heterojunction structure according to claim 1, wherein: the process conditions for annealing the composite structure comprise that the annealing is carried out in a vacuum environment or in a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, the annealing temperature is 400-1100 ℃, and the annealing time is 1 min-240 h.

6. The method of preparing a heterojunction structure according to claim 1, wherein: the bonding material wafer comprises one of a gallium oxide wafer, a gallium nitride wafer, a silicon carbide wafer, an indium phosphide wafer, a gallium arsenide wafer and a gallium antimonide wafer; the foreign substrate includes one of a silicon substrate and a silicon carbide substrate.

7. The method of preparing a heterojunction structure according to claim 1, wherein: the bonding method comprises one of surface activation bonding, metal bonding, hydrophilic bonding and anodic bonding.

8. The method of preparing a heterojunction structure according to claim 7, wherein: the degree of vacuum of the bonding is 1 × 10 ^-7 Pa～5×10 ^-7 Pa, pressure of 10-20 MPa, and temperature of 25 deg.C.

9. The method of preparing a heterojunction structure according to claim 1, wherein: the bonding material wafer comprises a defect bonding material wafer with a defect layer formed by ion implantation; the defect bonding material wafer is peeled from the defect layer while the annealing treatment is performed.

10. A heterojunction structure, characterized by: the heterojunction structure is prepared by the preparation method of the heterojunction structure as claimed in any one of claims 1 to 9.