JPH01103826A - Manufacture of adhesive semiconductor substrate - Google Patents

Abstract

PURPOSE:To avoid any cracking and breakdown in grinding process and device manufacturing process by a method wherein the mirror surfaces of the first and the second semiconductor substrates in the surface roughness not exceeding specified value are bonded to each other to be heat-treated at the temperatures exceeding specific temperature and not exceeding the melting point temperature of the semiconductor substrate. CONSTITUTION:The surface roughness on the mirror surface of the first and the second semiconductor material substrates shall not exceed 130Angstrom represented by the maximum height Rmax(JIS B0601) measured by one side length 1mm of the reference surface set up on the specified part of mirror surface while the heat treatment temperature shall exceed 200 deg.C and not exceed the melting point of semiconductor substrates. The bond properties abruptly declines when the surface roughness exceeds 130Angstrom (positions of one dot chain line). Furthermore, if the surface roughness does not exceed 130Angstrom of the maximum height measured by one side length 1mm of the reference surface, the process control can be facilitated since to dark parts like the sea areas in moon and Mars are observed when examined by the infrared ray transmission image process.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing an adhesive semiconductor substrate,
Specifically, it is applied to the production of semiconductor substrates in which silicon substrates are directly bonded to each other, or substrates of the same type or different types such as Si, GaAs, or other semiconductor materials are directly bonded.

(Prior Art) With adhesive semiconductor substrates, pn junctions and petrojunctions, which are conventionally considered difficult to manufacture, can be easily manufactured in a short time. For example, a pn junction between an n-layer and a p-layer, each 50 to 100 μt thick, is too expensive to fabricate using conventional epitaxial methods, and the triple diffusion method takes 3 to 10 days. However, if the n-type wafer and the p-type wafer are directly bonded together, a pn junction can be formed in as little as two hours.

In the conventional manufacturing method of such a bonded semiconductor substrate, as shown in FIG. 1A, cleaning is applied to the mirror surface of the two silicon substrates 1 and 2, which corresponds to the bonding interface 3, and has a surface roughness (fi height) of 500 Å or less. After the cleaning process, the mirror surfaces are physically brought into close contact with each other in a clean, dust-free atmosphere, and then heat treated in N2 gas at 200°C or higher, usually 1100°C, for about 2 hours to bond the silicon substrates together. The bond was made chemically strong (see Japanese Patent Application Laid-Open No. 60-51700).

In such a bonded semiconductor substrate 4, the bonding strength in a closely bonded state before heat treatment is about 5 kg/cn+2, but after heat treatment, it is strengthened to over 100 kg/cn+'. After rough polishing and finishing polishing are applied to the outer surface of the bonded semiconductor substrate, which is not the bonding surface, the required elements in the substrate and electrodes on the substrate are formed in the same manner as the substrate.

By the way, in the above conventional method for manufacturing a bonded semiconductor substrate, if dust adheres to the surface before the adhesion step, adhesion between the surfaces is hindered and voids appear. It has been known that when a bonded semiconductor substrate with voids caused by such dust is observed using infrared transmission imaging (see Technical Report No. 85-6424), concentric interference fringes are detected around the dust. .

Therefore, we used two semiconductor substrate materials with a surface roughness of 500X or less and a flatness (TTV) of 5 μm or less over the entire bonding surface, and created a cleaning atmosphere to prevent the appearance of interference fringes due to voids caused by dust. It has been conventional practice to prepare and bond the two to obtain a bonded semiconductor substrate having a strong bonding strength (100 kq/cn') as described above.

When such a dust-free bonded semiconductor substrate 4 is inspected by infrared transmission imaging before heat treatment, dark areas such as the oceans on the surface of the Moon or Mars may be observed, as shown in Figure 1B. Ta. However, after proper heat treatment, the first
As shown in Figure C, this dark area disappeared, and the bonding strength of the bonded semiconductor substrate 4 finally obtained was sufficiently large as described above. Conventionally, the presence or absence of this dark area was used to determine whether the bonded semiconductor substrate was defective. No consideration was given to how this might be related to the occurrence of

Therefore, it has not been known so far what advantages can be obtained by preventing the occurrence of dark areas.

Furthermore, it was previously unknown how rough the surface of the substrate should be in order to prevent the formation of dark areas before heat treatment. In other words, the ocean-like dark areas on the surfaces of the Moon and Mars, observed using infrared transmission imaging, had not previously been associated with surface roughness and considered to be a form of defect.

A defect in the bonded semiconductor substrate can be detected when many circuit elements are formed on the substrate and then diced into small chips. FIG. 1D shows an example of the state of the bonded semiconductor substrate after elements have been formed on the bonded semiconductor substrate 4 of FIG. 1C, which appears to have no problems at first glance, and has been diced into small chips.

(Figure 1D is an image observed by traditional photography rather than infrared transmission method.) In Figure 1D, the vertical and horizontal lines indicate incision lines every 0.5 nun, and the diagonally shaded areas in Figure 1D are 1E, which is an enlarged perspective view of the circular portion of the figure, shows a defective portion where a 0.510 chip has peeled off from the adhesive interface. Even if such peeling does not occur, a chip whose two substrates are incompletely bonded is still a defective product.

In severe cases, the entire bonded semiconductor substrate may crack during the substrate polishing process or device manufacturing process (dicing process), rather than just the chip peeling off.

(Problems to be Solved by the Invention) An object of the present invention is to partially increase electrical resistance,
It is an object of the present invention to provide a method for manufacturing a bonded semiconductor substrate with improved yield without cracking or destruction during a polishing process or a device manufacturing process. Another object of the present invention is to provide a method for manufacturing an adhesive semiconductor substrate that has a uniformly bright image without dark areas like the sea in infrared transmission imaging.

[Structure of the Invention] (Means for Solving the Problems) The method for manufacturing an adhesive semiconductor substrate of the present invention includes a silicon substrate,
Germanium substrate, or Ga As, Ga P, I
The mirror surfaces of first and second semiconductor material substrates of the same or different types used as semiconductor element substrates, including compound semiconductor substrates such as nP, are brought into close contact with each other, and then heat treatment is performed at a predetermined temperature for a predetermined time in a predetermined atmosphere. In addition, when bonding the mirror surfaces, the surface roughness of the mirror surfaces of the first and second semiconductor material substrates is the maximum height measured with a side length of 111 mm on a reference surface set at a predetermined portion on the mirror surface. The heat treatment temperature is 200° C. or higher and lower than the melting point of the semiconductor substrate.

(Function) If the maximum height of the surface roughness is 130 Å or less when measured from the reference surface to the side length of 1 mm, first of all, when observed using infrared transmission imaging, images such as the Moon or Mars will appear in the image. One example is that dark areas such as the ocean do not appear.

Next, with a surface roughness (maximum height) in the range of 50 to 300X,
A large number of bonded sets of substrates with the same surface roughness are manufactured, and the bonded substrates are subjected to destructive tests to determine the percentage of non-bonded substrates that have even the slightest crack or breakage. Adhesion (%) The dependence of the adhesion on the surface roughness is shown in FIG. As can be seen from FIG. 2, when the surface roughness exceeds 130 (the position indicated by the - dotted chain line), the adhesiveness rapidly decreases.

Further, the resistance of the same sample bonded substrate as in the test shown in FIG. 2 was measured by attaching AI electrodes to both sides of the bonded substrate and dicing the sample into 2 nn+ pieces. At this time, the wafer used for bonding had a P-type paper resistance of 0.014 to 0.0.
It is 15Ω·co. Then, the variation σ of the majority resistance of the diced product was determined as a percentage (%) of the average resistance. The dependence of the resistance variation on the surface roughness is shown in FIG.

As can be seen from FIG. 3, as in the case of adhesiveness shown in FIG. 2, when the surface roughness exceeds 130X, the variation in resistance increases rapidly.

From these facts, the reference plane of the surface - the length of the side 1n + 11
Setting the surface roughness (maximum height) to 130 Å or less eliminates dark areas in images obtained using infrared transmission imaging, and uniformity of both adhesion and resistance is improved by setting the surface roughness to 130 Å or less. Therefore, the dark areas in the infrared transmission image are incompletely bonded areas, and the surface roughness is reduced to 130.
Setting it to X or less significantly improves the characteristics of the bonded semiconductor substrate.

It should be noted that the significance of the present invention in which the surface roughness is set to a maximum of 130X is that the length of the reference plane-side of the surface roughness is set to 1 nun. Also, the flatness of the entire surface of the wafer used (TTL)
The range is set to 5 μ■ or less.

(Example) Next, the present invention will be specifically explained using Examples 1 and 2.

Example 1 N with a diameter of 100100r and a specific resistance of 20 to 30Ω・CIl
The flatness of conventionally used silicon wafers (
TTV) At least 500 sheets with surface roughness of 5 μm or less and surface roughness distributed in the range of 30 to 280× were prepared. The method for measuring surface roughness is ■Non-contact surface roughness profile measuring machine S manufactured by Tokyo Seimitsu.
urfco1192 OA (spot diameter 1.6 μll
l ) and a magnification of 1. Goo, 000x, measurement distance 1
At n+i, the maximum height is measured at five points on the wafer, and the average is taken as the surface roughness of the wafer.

Then, from over 500 sheets measured, surface roughness 1
500 wafers of 30X or less were sorted into 10 lots, and the wafers in that lot were brought into close contact with each other in sets of 250 bonded wafers, and then heated at 1100'C (the melting point of silicon wafers is approximately 1400°C). Adhesion heat treatment was performed in N2 gas for 2 hours. Semiconductor wafer bonding technology using heat treatment is disclosed in detail in US Pat. No. 4,671,846 and US Pat. No. 4,700,466.

On the other hand, as a comparative example, the surface roughness was 30 to 28 without screening.
Another 500 wafers distributed in the 01 range were taken, and 250 bonded wafers of a comparative example were manufactured in the same manner as in Example 1.

FIG. 4 shows the contents of voids in the bonded wafers of Example 1 and Comparative Example by infrared transmission imaging inspection.

In other words, the overall voids in the comparative example include voids caused by dust shown by concentric interference fringes and voids caused by unevenness shown by dark areas such as the oceans of the Moon and Mars. Among the voids in Example 1, there were only voids caused by approximately the same amount of dust as in the comparative example, and there were no voids caused by unevenness.

FIG. 6A shows the state of representative sample A of Example 1 observed by an infrared transmission method. Predetermined 3 of sample A
The actual measurement results (partial) of the surface roughness at points (A, B, C) are shown in Figures 6B, 6C, and 6D, respectively.
The surface roughness values at A, B, and C are 92X, respectively.
124X, 106X. The example wafer of FIG. 6A shows that no voids are observed over the entire surface.

Note that the narrow ring-shaped edging around sample A shown in FIG. 6A is an unbonded area that inevitably has a width of about 2Illll for a semiconductor wafer with a diameter of 100n+n+, but in reality, it is difficult to process a bonded semiconductor substrate. This is the part that is removed during the process. This portion is caused by so-called surface sagging of the wafer, and is not related to the surface roughness, etc., which is the focus of the present invention.

FIG. 7A shows a typical sample B of the comparative example observed by an infrared transmission method. Three points of sample B (A
, B, and C) are shown in Figures 7B, 7C, and 7D, respectively.
, the values of surface roughness -11= at C are 286 people, 124 x, 146, respectively.
X, including both below 130X and above 130X.

In Figure 7A, the white areas indicate that the surface roughness is 130 degrees or less and there are no voids, and the crosshatch areas are areas that have surface roughness exceeding 130 degrees, indicating that poor adhesion occurred during dicing. show.

FIG. 5 is a graph showing the yield when bonded semiconductor substrates of Example 1 and Comparative Example were subjected to the same actual device process. As shown in the figure, Example 1 shows a 13% improvement in yield compared to Comparative Example, but this is because the surface roughness is reduced by 1.
It was confirmed that this was due to the fact that there were no substrate cracks or destruction defects due to the use of 30X or less.

Furthermore, it was also confirmed that the device characteristics related to the adhesive interface in the device of Example 1 (see FIG. 3) were significantly improved in variation compared to those of the comparative example.

The above results with a surface roughness of 130 or greater did not change even after repeated experiments.

Incidentally, a distortion-free mirror wafer with a surface roughness of 130X or less can be realized by the polishing method disclosed in ``Proceedings of the 1981 Autumn Conference of the Japan Society of Precision Machinery, pp. 440-451 (Ishikawa et al.).

In the above description, the infrared transmission method was used to observe the adhesive interface, but ultrasonic waves having a frequency of 10 to 30 MH7 or more can be used for this observation. One of the methods of using this ultrasonic wave is one that uses the well-known computer tomography (CT), and the other that uses the reflection of the ultrasonic wave at the adhesive interface. The latter method of utilizing ultrasonic reflection is disclosed, for example, in Japanese Patent Application No. 60-259715 (here, ultrasonic waves of 30 MHz or higher are used).

Example 2 As a semiconductor material substrate, Ge, GaAs, InP
When similar experiments were conducted using GaP, similar to Example 1, results were obtained in which the characteristics suddenly changed when the surface roughness reached 130.

[Effects of the Invention] According to the method for manufacturing a bonded semiconductor substrate of the present invention, by setting the surface roughness of the semiconductor material substrate before bonding to 130X or less, it is possible to completely prevent unbonded portions due to irregularities on the substrate surface. As a result, defects such as substrate cracking and destruction of bonded semiconductor substrates have been drastically reduced. Furthermore, variations in electrical properties at the bonded interface are eliminated, making it possible to stabilize the device properties of the bonded semiconductor substrate.

As described above, the manufacturing method of the present invention greatly contributes to improving the yield and reducing the cost of chip manufacturing using bonded semiconductor substrates.

[Brief explanation of the drawing]

Figure 1A is a cross-sectional view showing the schematic structure of the bonded semiconductor substrate, and Figure 1B is an example of a dark area like the oceans of Mars seen when the bonded semiconductor substrate of Figure 1A is observed using an infrared transmission method at the adhesion stage. Figure 1C is a diagram illustrating the state of the adhesive semiconductor substrate in Figure 1B observed by infrared transmission method after heat treatment, and Figure 1D is a diagram showing chips peeling off when the adhesive semiconductor substrate is diced. A diagram showing
FIG. 1E is an enlarged perspective view of the circular portion of FIG. 1D, FIGS. 2 and 3 are graphs explaining the operation of the manufacturing method of the present invention, and FIGS. 4 and 5 are graphs of the embodiment 1 of the present invention. A bar graph explaining the effect, FIG. 6A is a diagram obtained by observing sample A according to Example 1 using an infrared transmission method, and FIGS. 6B to 6D are cross sections of surface roughness at points A to 0 in FIG. 6A, respectively. The curve diagram, FIG. 7A is a diagram obtained by observing sample B according to a comparative example using an infrared transmission method, and FIGS. 7B to 7D are cross-sectional curve diagrams of surface roughness at points A to 0 in FIG. 7A, respectively. . ■, 2... Semiconductor material substrate, 3... Adhesive interface, 4...
...Adhesive semiconductor substrate. -15 = arm - part 8 8. Figure 1B Figure 1D Figure 1C Figure 1E Figure 4 Camellia Figure 5 Peng-ba ILIIIITIIJ Figure 6A Negative mEa ILNT: N Figure 7A

Claims (1)

[Claims] 1. A first semiconductor substrate having a mirror surface with a surface roughness of 130 Å or less in maximum height per 1 mm of length, and a second semiconductor substrate having a mirror surface with a surface roughness of 130 Å or less in maximum height per 1 mm of length. a step of preparing a semiconductor substrate and bringing a mirror surface of the first semiconductor substrate and a mirror surface of the second semiconductor substrate into close contact;
and the closely attached first and second semiconductor substrates at 200°C.
A method for manufacturing an adhesive semiconductor substrate, which comprises the step of heat treatment at a temperature lower than the melting point of the semiconductor substrate.