JP2018101745A - Method of producing pn-junction silicon wafer and pn-junction silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for producing a pn-junction silicon wafer capable of suppressing leak current in a vertical device.SOLUTION: A method for product a pn-junction silicon wafer includes: a first step of forming activation surfaces 10A, 20A by irradiating one side of a p-type single crystal silicon substrate 10 and one side of an n-type single crystal silicon substrate 20 with fluorine ions under vacuum at room temperature and performing etching processing of both single sides; and a second step of obtaining a pn-junction silicon water 100 by bringing the activation surface 10A into contact with the activation surface 20A under the vacuum at the room temperature and integrating the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 subsequent to the first step.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method of manufacturing a pn junction silicon wafer and a pn junction silicon wafer.

  Patent Document 1 describes an epitaxial growth method as a method of manufacturing a pn junction silicon wafer used for a vertical device. Specifically, an epitaxial layer having a conductivity type opposite to that of the support substrate is epitaxially grown on the support substrate by chemical vapor deposition or the like to obtain a pn junction silicon wafer. Here, in order to realize a high breakdown voltage operation in the vertical device, it is necessary to deposit an epitaxial layer of 100 μm or more.

  Patent Document 2 describes the following technique as a method of bonding silicon substrates together at a vacuum room temperature (hereinafter referred to as “vacuum room temperature bonding method”). First, an activation treatment is performed by irradiating each surface of two silicon substrates with an argon fast atom beam at room temperature in a vacuum, thereby making both the surfaces active surfaces. Subsequently, the two activated surfaces are brought into contact with each other at a vacuum room temperature, whereby the two silicon substrates are bonded to each other with the activated surfaces as the bonding surfaces.

Japanese Patent Application Laid-Open No. 9-213946 JP-A-10-92702

  However, in the epitaxial growth method described in Patent Document 1, it takes a long time to form an epitaxial layer having a layer thickness of 100 μm or more. Therefore, it has been found that the wafer cannot withstand thermal stress during epitaxial growth, causing problems such as slip and dislocation, and diffusion of dopant in the support substrate to the epitaxial layer.

  Therefore, the present inventors have considered producing a pn junction silicon wafer by using the vacuum room temperature bonding method described in Patent Document 2 as an alternative to the epitaxial growth method. In the vacuum room temperature bonding method, the activation treatment is generally performed by irradiating argon as in the technique described in Patent Document 2. Therefore, the present inventors produced a pn junction silicon wafer by the following method. First, by irradiating one side of a p-type single crystal silicon substrate and one side of an n-type single crystal silicon substrate with argon ions generated in a plasma atmosphere at room temperature in a vacuum, both of the one side are activated. It was. Subsequently, by bringing both of the activated surfaces into contact with each other at a vacuum room temperature, the p-type single crystal silicon substrate and the n-type single crystal silicon substrate are bonded together using the both activated surfaces as a bonding surface, A pn junction silicon wafer was obtained.

  However, it was found that when a voltage was applied to a vertical device manufactured using the pn junction silicon wafer thus obtained, the leakage current could not be suppressed, and there was room for improvement from the viewpoint of device characteristics.

  An object of this invention is to provide the manufacturing method of a pn junction silicon wafer which can suppress a leakage current in a vertical device, and a pn junction silicon wafer in view of the said subject.

  In order to solve the above-mentioned problems, the present inventors paid attention to the vicinity of the bonding surface of the pn junction silicon wafer and analyzed this. As a result, it was found that oxygen was present in the vicinity of the bonding surface, which was a source of leakage current. And when the present inventors advanced further examination, this oxygen originates in the natural oxide film of thickness 5-20cm formed in the surface layer of the p-type single crystal silicon substrate or the n-type single crystal silicon substrate. It turned out to be a thing. That is, a natural oxide film having a thickness of 5 to 20 mm is formed on the surface layer of a p-type single crystal silicon substrate or an n-type single crystal silicon substrate that is generally not maintained in a non-oxidizing atmosphere. Oxygen in the natural oxide film is pushed into a region deeper than the region where the natural oxide film exists by irradiation with argon ions (hereinafter referred to as “knock-on”). Then, when a p-type single crystal silicon substrate in which oxygen is knocked on and an n-type single crystal silicon substrate are bonded together to produce a pn-junction silicon wafer, oxygen remains in the vicinity of the bonding surface and becomes a source of leakage current. .

  Therefore, the present inventors examined a vacuum room temperature bonding method capable of suppressing oxygen from remaining in the vicinity of the bonding surface. The amount of oxygen in the natural oxide film or knocked-on oxygen The new idea that it can be suppressed by the etching action of was obtained. Based on this idea, it has been found that oxygen can be suppressed from remaining in the vicinity of the bonding surface by replacing the irradiated ions with fluorine ions instead of argon ions. Then, it was confirmed that the leakage current can be remarkably suppressed in the vertical device.

The present invention has been completed based on the above findings, and the gist of the present invention is as follows.
(1) First surface of p-type single crystal silicon substrate and one surface of n-type single crystal silicon substrate are irradiated with fluorine ions at room temperature under vacuum, and both of the one surface are etched to form an activated surface. 1 process,
Subsequent to the first step, both the activated surfaces are brought into contact with each other at a vacuum room temperature, thereby integrating the p-type single crystal silicon substrate and the n-type single crystal silicon substrate, thereby obtaining a pn junction silicon wafer. A second step of obtaining,
A method for producing a pn junction silicon wafer, comprising:

(2) Prior to the first step, an n-type silicon epitaxial layer having a thickness of 50 μm or less having a dopant concentration higher than that of the n-type single crystal silicon substrate is formed on one surface of the p-type single crystal silicon substrate. Having a process of forming,
In the first step, instead of one side of the p-type single crystal silicon substrate, the surface of the n-type silicon epitaxial layer is irradiated with fluorine ions at room temperature in a vacuum, and the surface is etched to activate. The manufacturing method of the pn junction silicon wafer as described in said (1) made into a surface.

(3) Prior to the first step, a p-type silicon epitaxial layer having a thickness of 50 μm or less having a dopant concentration higher than that of the p-type single crystal silicon substrate is formed on one surface of the n-type single crystal silicon substrate. Having a process of forming,
In the first step, instead of one surface of the n-type single crystal silicon substrate, the surface of the p-type silicon epitaxial layer is irradiated with fluorine ions at room temperature in a vacuum, and the surface is etched to activate. The manufacturing method of the pn junction silicon wafer as described in said (1) made into a surface.

(4) Any one of the above (1) to (3), wherein a dose amount of the fluorine ions irradiated in the first step is 1 × 10 ¹⁵ atoms / cm ² or more and 1 × 10 ¹⁸ atoms / cm ² or less. The manufacturing method of the pn junction silicon wafer as described in one.

  (5) The pn junction silicon according to any one of (1) to (4), wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate are silicon wafers containing no dislocation clusters and COPs. Wafer manufacturing method.

  (6) The method for producing a pn junction silicon wafer according to any one of (1) to (5), wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate have the same plane orientation.

  (7) The step (1) further comprising a step of grinding and polishing at least one of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate constituting the pn junction silicon wafer after the second step. The manufacturing method of the pn junction silicon wafer as described in any one of-(6).

(8) a p-type single crystal silicon substrate;
An n-type single crystal silicon substrate in contact with the p-type single crystal silicon substrate;
A pn junction silicon wafer having
A pn junction silicon wafer characterized by having no peak at the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate in an oxygen concentration profile in the depth direction of the pn junction silicon wafer.

(9) An n-type silicon epitaxial layer having a dopant concentration higher than that of the n-type single crystal silicon substrate and having a thickness of 50 μm or less between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. Further having a layer,
In the oxygen concentration profile in the depth direction of the pn junction silicon wafer, the n-type silicon epitaxial layer and the n-type single crystal are used instead of the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. The pn junction silicon wafer according to the above (8), which has no peak at the interface with the silicon substrate.

(10) A p-type silicon epitaxial layer having a dopant concentration higher than that of the p-type single crystal silicon substrate and having a thickness of 50 μm or less between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. Further having a layer,
In the oxygen concentration profile in the depth direction of the pn junction silicon wafer, the p-type silicon epitaxial layer and the p-type single crystal are used instead of the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. The pn junction silicon wafer according to the above (8), which has no peak at the interface with the silicon substrate.

  (11) The pn junction silicon according to any one of (8) to (10), wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate are silicon wafers containing no dislocation clusters and COPs. Wafer.

  (12) The pn junction silicon wafer according to any one of (8) to (11), wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate have the same plane orientation.

  According to the present invention, a pn junction silicon wafer capable of suppressing leakage current in a vertical device can be manufactured.

It is a schematic cross section explaining the manufacturing method of the pn junction silicon wafer 100 by the 1st Embodiment of this invention. It is a schematic cross section explaining the manufacturing method of the pn junction silicon wafer 200 by the 2nd Embodiment of this invention. In one Embodiment of this invention, it is a schematic cross section of the apparatus used when performing vacuum normal temperature joining. It is a figure which shows the defect distribution in sectional drawing of ratio of the pulling-up speed with respect to the temperature gradient in a solid-liquid interface, and a single crystal silicon ingot. It is a schematic cross section explaining the manufacturing method of the pn junction silicon wafer 300 by a comparative example. It is the graph which showed the oxygen concentration profile of the pn junction silicon wafer about (a) invention example and (b) comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In principle, the same components are denoted by the same reference numerals, and the description thereof is omitted. 1 and 2, for convenience of explanation, different from the actual thickness ratio, the native oxide films 12, 22, 34, and the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20, and The thickness of the silicon epitaxial layer 32 is exaggerated.

(First embodiment)
With reference to FIG. 1, a first embodiment of a method for producing a pn junction silicon wafer of the present invention will be described.

(First step)
Referring to FIG. 1, natural oxide films 12 and 22 having a thickness of 5 to 20 mm are formed on the surface layers of p-type single crystal silicon substrate 10 and n-type single crystal silicon substrate 20 that are not maintained in a non-oxidizing atmosphere. Has been. In the first step, first, fluorine ions are irradiated to one side of the p-type single crystal silicon substrate 10 and one side of the n-type single crystal silicon substrate 20 at a vacuum room temperature. As shown in FIG. 1, one side of the p-type single crystal silicon substrate 10 and one side of the n-type single crystal silicon substrate 20 are etched by the fluorine ion etching action and activation action, respectively, so that the activation faces 10A and 20A are activated. It becomes.
Dangling bonds (bonding hands) inherent to silicon appear on these activated surfaces 10A and 20A. A characteristic part of the present invention is that fluorine ions are used as irradiation ions in the first step, and the technical significance thereof will be described later.

(Second step)
Next, referring to FIG. 1, following the first step, both the activated surfaces are brought into contact with each other at a vacuum room temperature. As a result, a bonding force is instantaneously applied to both of the activated surfaces, and the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are firmly bonded using the both activated surfaces as a bonding surface. As a result, a pn junction silicon wafer is obtained. Thus, in the vacuum room temperature bonding method, the two substrates are bonded instantaneously and firmly at room temperature. Therefore, the dopant in the p-type single crystal silicon substrate 10 diffuses to the n-type single crystal silicon substrate 20 side, or the dopant in the n-type single crystal silicon substrate 20 diffuses to the p-type single crystal silicon substrate 10 side. It is suppressed. Also, unlike the prior art in which an epitaxial layer is grown over a long time on a support substrate to produce a pn junction silicon wafer, both substrates can be bonded instantaneously and firmly, thus preventing the occurrence of slips and dislocations. be able to.

  Below, with reference to FIG. 3, one form of the apparatus which implement | achieves a 1st process and a 2nd process is demonstrated. The vacuum room temperature bonding apparatus 40 includes a plasma chamber 41, a gas inlet 42, a vacuum pump 43, a pulse voltage application device 44, and wafer fixing bases 45A and 45B.

First, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are placed and fixed on the wafer fixing bases 45A and 45B in the plasma chamber 41, respectively. Next, the inside of the plasma chamber 41 is depressurized by the vacuum pump 43, and then a source gas composed of a fluorine source compound is introduced into the plasma chamber 41 from the gas inlet 42. The fluorine source compound is not particularly limited as long as it has an etching action and an activation action, and specific examples include CF ₄ and SF ₆ .

Subsequently, a positive voltage is applied in a pulse form to the wafer fixing bases 45A and 45B (and the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20) by the pulse voltage application device 44. Thereby, the source gas is decomposed to generate plasma, and fluorine ions (F ⁻ ) contained in the generated plasma are accelerated and irradiated toward the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20. The

The dose of fluorine ions to be irradiated is preferably 1 × 10 ¹⁵ atoms / cm ² or more and 1 × 10 ¹⁸ atoms / cm ² or less. If it is 1 × 10 ¹⁵ atoms / cm ² or more, the etching process and the activation process can be stably performed, and if it is 1 × 10 ¹⁸ atoms / cm ² or less, the alteration described later is performed only by heat treatment in the device process. This is because the crystallinity of the layer can be recovered.

  Hereinafter, the conditions of the chamber pressure, the pulse voltage, and the substrate temperature in the first step will be described in detail.

The chamber pressure in the plasma chamber 41 is preferably 1 × 10 ⁻⁵ Pa or less. By setting the pressure to 1 × 10 ⁻⁵ Pa or less, elements such as silicon ejected from the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 reattach to the substrates 10 and 20 and the activated surfaces 10A and 20A. This is because the dangling bond formation rate can be prevented from decreasing.

The pulse voltage applied to the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 is set so that the acceleration energy of fluorine ions (F ⁻ ) with respect to the substrates 10 and 20 is 100 eV or more and 5 keV or less. If it is 100 eV or more, fluorine ions can be prevented from depositing on the substrates 10 and 20 and the activated surfaces 10A and 20A, and dangling bonds can be formed by sputtering silicon atoms. If it is 5 keV or less, fluorine ions can be formed. This is because it can be prevented from being injected into the inside of the substrate.

  The frequency of the pulse voltage is preferably 10 Hz to 10 kHz. This is because the irradiation variation of fluorine ions can be absorbed when the frequency is 10 Hz or higher, and the ion irradiation amount is stable, and the plasma formation by glow discharge is stable when the frequency is 10 kHz or lower.

  The pulse width of the pulse voltage is preferably 1 μsec or more and 10 ms or less. This is because if it is 1 μsec or longer, fluorine ions can be stably irradiated onto the substrates 10 and 20 and the activated surfaces 10A and 20A, and if it is 10 ms or shorter, plasma formation by glow discharge is stabilized.

  The p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are not heated, and the temperature is normal temperature (usually 30 ° C. to 90 ° C.).

  The first process can be realized by setting the chamber pressure, the pulse voltage, and the substrate temperature within a range that satisfies the above conditions. Thereafter, in the second step, both the activated surfaces come into contact with each other by bringing the wafer fixing bases 45A and 45B closer to each other. Thereby, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are integrated, and a pn junction silicon wafer is obtained.

  By the above method, the first step and the second step can be realized using the vacuum room temperature bonding apparatus 40. However, the method according to the present invention is not limited to this, and the chamber pressure, the pulse voltage, and the substrate temperature may be set separately for the etching process and the activation process in the first step.

In the etching process in the first step, the chamber pressure in the plasma chamber 41 may be 1 × 10 ⁻³ Pa or less. This is because one side of each substrate can be etched if it is 1 × 10 ⁻³ Pa or less.

In the activation process in the first step, the pulse voltage applied to the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 is applied to the surfaces of the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20. The acceleration energy of fluorine ions (F ⁻ ) with respect to may be set to 100 eV or more and 5 keV or less. If it is 100 eV or more, fluorine ions can be prevented from depositing on the substrates 10 and 20 and the activated surfaces 10A and 20A, and dangling bonds can be formed by sputtering silicon atoms. If it is 5 keV or less, fluorine ions can be formed. This is because it can be prevented from being injected into the inside of the substrate.

(Grinding and polishing of pn junction silicon wafer)
After the second step, it may further include a step of grinding and polishing at least one of the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 constituting the pn junction silicon wafer. Thereby, the pn junction silicon wafer 100 having a desired thickness can be obtained. In the grinding and polishing step, known or arbitrary grinding and polishing methods can be suitably used, and specific examples include surface grinding and mirror polishing methods.

The characteristic part of the present invention is that fluorine ions (F ⁻ ) having an etching action and an activation action are used as irradiation ions. Below, this technical significance is demonstrated with an effect.

Referring to FIG. 5, natural oxide films 12 and 22 having a thickness of 5 to 20 mm are generally formed on the surface layers of p-type single crystal silicon substrate 10 and n-type single crystal silicon substrate 20. . Therefore, when an activation treatment is performed by irradiating one side of the p-type single crystal silicon substrate 10 and one side of the n-type single crystal silicon substrate 20 with argon ions (Ar ⁺ ) as in the prior art, the natural oxide films 12 and 22 Oxygen is knocked on in a region deeper than the region where the natural oxide films 12 and 22 exist. When the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are bonded together to produce a pn junction silicon wafer, oxygen remains in the vicinity of the bonded surface. The remaining oxygen becomes a source of leakage current.

  On the other hand, the present inventors have found that leakage current can be suppressed in a vertical device by irradiating with fluorine ions instead of argon ions. The present inventors consider the effects as follows.

  Referring to FIG. 1, even in the case where fluorine ion is irradiated to one side of p-type single crystal silicon substrate 10 and one side of n-type single crystal silicon substrate 20, oxygen in natural oxide films 12 and 22 Knock-on is performed at a position deeper than 20 mm from the surface of each of single-type single crystal silicon substrate 10 and n-type single crystal silicon substrate 20. However, fluorine ions are ions having an etching action and an activation action. Therefore, the native oxide films 12 and 22 can be removed by the etching action of fluorine ions, and further, the region where oxygen is knocked on can also be removed. Then, due to the activation of fluorine, one side of the etched p-type single crystal silicon substrate 10 and one side of the n-type single crystal silicon substrate become activation surfaces 10A and 20A, respectively. Thus, by utilizing the etching action and activation action of fluorine ions, a vacuum room temperature bonding method capable of suppressing the amount of oxygen remaining in the vicinity of the bonding surface can be realized. In this case, the leakage current can be suppressed.

Moreover, in addition to the above effects, the present inventors have found that the following effects can also be obtained. That is, when argon ions are irradiated, the irradiated argon ions are combined with electrons in the substrate to become argon (atoms). In the vicinity of the bonding surface, a plurality of these argon aggregates to form a plurality of massive precipitates. These precipitates also become a source of leakage current. On the other hand, when irradiating fluorine ions as in the present invention, the irradiated fluorine ions react with silicon constituting the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 to form silicon tetrafluoride. It becomes (SiF ₄ ) and gasifies. Therefore, according to the present invention, it is possible to suppress the generation of precipitates due to ion irradiation, thereby further suppressing the leakage current.

  From the viewpoint of further suppressing the leakage current, in the above activation process, the knocked-on oxygen may be removed to expose the bare silicon surfaces of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. Note that the “bare silicon surface” in this specification refers to a p-type single crystal silicon surface, an n-type single crystal silicon surface, or a p-type in which a natural oxide film does not exist and knocked-on oxygen does not exist. It means a silicon epitaxial surface or an n-type silicon epitaxial surface.

  Here, in the vicinity of the bonding surface of the pn-junction silicon wafer, an alteration in which the crystallinity inherent to the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 is disturbed due to the activation process in the first step. Layers are occurring. However, the crystallinity of the altered layer is restored to the original crystallinity by heat treatment at 600 ° C. or higher included in the device process. Therefore, the leakage current due to the altered layer is suppressed in the vertical device.

  As described above, since the disorder of crystallinity in the altered layer is recovered by the heat treatment in the device process, it is not necessary to perform an additional heat treatment for recrystallization after the second step and before the device process. . Therefore, manufacturing cost can be reduced. However, a heat treatment for recrystallization described below may be additionally performed after the second step and before the device process.

The heat treatment for recrystallization may be performed in a temperature range of 200 ° C. to 1300 ° C. for 30 minutes to 2 hours in an atmosphere containing at least one selected from N ₂ , Ar, and H _2. preferable. For example, when performing heat treatment for 1 to 2 hours in a temperature range of 1000 ° C. or higher, it is more preferable to employ a microwave annealing process in which the temperature increase and decrease rates are fast. In the microwave annealing treatment, the pn junction silicon wafer can be efficiently heated by irradiating the pn junction silicon wafer with an electromagnetic wave having a frequency of 300 MHz or more and 3 THz or less, which is called microwave in a broad sense. In general heat treatment using an external heater source (for example, heat treatment using a furnace), it takes several tens of minutes to raise and lower the temperature. Therefore, there arises a problem that the dopant in the substrate diffuses during the temperature rise and fall, which affects the device characteristics.

  This step can be performed using a commercially available microwave annealing apparatus. In this step, the pn junction silicon wafer can be heated to a temperature of 50 ° C. or more and 1300 ° C. or less by irradiating the pn junction silicon wafer with an electromagnetic wave for 10 minutes to 1 hour. In the microwave annealing treatment, it is possible to rapidly raise and lower the temperature of the pn junction silicon wafer, and the temperature raising and lowering rate is preferably 50 ° C./min to 200 ° C./min. If it is 50 ° C./min or more, there is no fear that the dopant in the substrate diffuses during the temperature rise / fall, and if it is 200 ° C./min or less, the thermal stress applied to the wafer during the temperature rise / fall can be suppressed. Slip or dislocation does not occur. In addition, the frequency of the electromagnetic wave to be irradiated is preferably 300 MHz to 300 GHz, and the output of the electromagnetic wave to be irradiated is preferably 500 W to 4 kW.

(Second Embodiment)
With reference to FIG. 2, a second embodiment of the method for producing a pn junction silicon wafer of the present invention will be described.

(Formation of n-type silicon epitaxial layer)
Referring to FIG. 2, first, n-type silicon epitaxial layer 32 having a dopant concentration higher than that of n-type single crystal silicon substrate 20 and having a thickness of 50 μm or less is formed on one surface of p-type single crystal silicon substrate 10. To do. If the thickness of the n-type silicon epitaxial layer 32 exceeds 50 μm, epitaxial growth takes a long time. For this reason, the wafer cannot withstand thermal stress, causing problems such as slip and dislocation, and diffusion of the dopant in the p-type single crystal silicon substrate 10 into the n-type silicon epitaxial layer 32.

The dopant concentration of the n-type single crystal silicon substrate 20 is preferably 8.4 × 10 ¹² atoms / cm ³ or more and 9.0 × 10 ¹⁴ atoms / cm ³ or less, and the dopant concentration of the n-type silicon epitaxial layer 32 is The dopant concentration of the n-type single crystal silicon substrate 20 is preferably 10 times or more and 1000 times or less. By setting it to 10 times or more, the spread in the vertical direction of the depletion layer region described later can be suppressed. Moreover, by setting it to 1000 times or less, electric field concentration that affects device characteristics can be suppressed.

  For the formation of the n-type silicon epitaxial layer 32, a known or arbitrary method can be suitably used. For example, a single wafer epitaxial growth apparatus can be used. A natural oxide film 34 having a thickness of 5 to 20 mm is also formed on the surface of the n-type silicon epitaxial layer 32 formed by epitaxial growth, as shown in FIG.

(First step)
Next, referring to FIG. 2, the surface of n-type silicon epitaxial layer 32 and one surface of n-type single crystal silicon substrate 20 are irradiated with fluorine ions under a vacuum at room temperature. As shown in FIG. 2, the surface of the n-type silicon epitaxial layer and one surface of the n-type single crystal silicon substrate 20 are etched by the etching action and activation action of fluorine ions, respectively, to become activated faces 32 </ b> A and 20 </ b> A. . Here, dangling bonds inherent to silicon appear on the activated surfaces 32A and 20A.

(Second step)
Next, referring to FIG. 2, following the first step, both the activated surfaces are brought into contact with each other at a vacuum room temperature. As a result, a bonding force is instantaneously applied to both of the activated surfaces, and the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are firmly bonded using the both activated surfaces as a bonding surface. As a result, a pn junction silicon wafer is obtained.

  Here, near the bonding surface of the pn junction silicon wafer, the crystallinity inherent to the n-type single crystal silicon substrate 20 and the n-type single crystal silicon epitaxial layer 32 is disturbed due to the activation process in the second step. Altered layer is generated. These altered layers are also recrystallized by heat treatment in the device process, as in the first embodiment. Therefore, the leakage current resulting from these altered layers is suppressed in the vertical device.

(Grinding and polishing of pn junction silicon wafer)
After the second step, it may further include a step of grinding and polishing at least one of the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 constituting the pn junction silicon wafer. Thereby, the pn junction silicon wafer 200 having a desired thickness can be obtained. In the grinding and polishing step, a method similar to the method described in the first embodiment can be used.

  As described above, the second embodiment has been described with reference to FIG. 2, but the effects obtained by adopting the first step and the second step in the second embodiment are the same as those in the first embodiment. Use the explanation. Below, with reference to FIG. 2, the effect obtained additionally by 2nd Embodiment is demonstrated in detail.

  Referring to FIG. 2, in the second embodiment, an n-type silicon epitaxial layer 32 is formed on one surface of p-type single crystal silicon substrate 10 prior to the first step. The mating surface can be shifted. In this way, the technical significance of shifting the pn junction surface and the bonding surface and making the dopant concentration of the n-type silicon epitaxial layer 32 higher than the dopant concentration of the n-type single crystal silicon substrate 20 is as follows. It explains together.

  The vertical device is manufactured through a device process after the pn junction silicon wafer 200 is manufactured. This device process includes heat treatment at 600 ° C. to 1300 ° C. for 10 minutes to 20 hours in a nitrogen or oxygen atmosphere. In addition, during device operation, a high voltage of 500 V or more and 1500 V or less is applied to the pn junction silicon wafer constituting the vertical device.

  Here, a region called a depletion layer in which almost no carriers exist is present on the pn junction surface. This depletion layer region has the property of spreading in the vertical direction of the vertical device when a voltage is applied. In addition, the bonding surface of the pn junction silicon wafer 200 has micro defects that are not revealed immediately after the pn junction silicon wafer is manufactured, but are manifested by the heat treatment in the device process. When the region where such a micro defect exists and the depletion layer region overlap, a reverse leakage current is generated, and as a result, device characteristics such as switching characteristics of the diode are affected.

  Thus, by shifting the pn junction surface and the bonding surface, it is possible to suppress overlap between the region where the micro defect exists and the depletion layer region. Furthermore, by making the dopant concentration of the n-type silicon epitaxial layer higher than the dopant concentration of the n-type single crystal silicon substrate, the spread of the depletion layer region in the vertical direction is suppressed even when a high voltage is applied during device operation. be able to. Therefore, overlap between the region where the minute defect exists and the depletion layer region can be suppressed, and the reverse leakage current is suppressed, so that the device characteristics such as the switching characteristics of the diode are further improved.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In this embodiment, the p-type single crystal silicon substrate is left as it is, and a p-type silicon epitaxial layer having a dopant concentration higher than that of the p-type single crystal silicon substrate is formed on one surface of the n-type single crystal silicon substrate. Is the same as in the second embodiment.

(P-type single crystal silicon substrate and n-type single crystal silicon substrate)
The p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 that can be used in the first to third embodiments of the present invention will be described below.

  As the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20, a single crystal silicon wafer made of a silicon single crystal can be used. As the single crystal silicon wafer, one obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) with a wire saw or the like can be used. Here, when the pn junction silicon wafers 100 and 200 having a desired thickness are used in a vertical device, if a defect exists in any region in the vertical direction of the device formation region, the pn junction is passed through the defect. Leakage current is generated between them, affecting the device characteristics. Therefore, from the viewpoint of obtaining better device characteristics, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are silicon wafers that do not contain dislocation clusters and vacancy agglomerated defects (COP: Crystal Originated Particles). It is preferable. Below, with reference to FIG. 4, the manufacturing method of the silicon wafer which does not contain a dislocation cluster and COP is demonstrated.

  One of the typical methods for producing a single crystal silicon ingot that is a material of a silicon wafer is a CZ method. In the production of a single crystal silicon ingot by this CZ method, a seed crystal is immersed in a silicon melt supplied in a quartz crucible, and the seed crystal is pulled up while rotating the quartz crucible and the seed crystal. Single crystal silicon ingot is grown.

  It is known that various types of grown-in defects that cause problems in the device process occur in the single crystal silicon ingot grown in this way. Typical examples are dislocation clusters generated in regions where interstitial silicon is dominant (hereinafter also referred to as “I region”) due to growth under slow pulling conditions, and voids due to growth under high pulling conditions. This is a COP generated in a dominant region (hereinafter also referred to as “V region”). Further, near the boundary between the I region and the V region, there exists a defect distributed in a ring shape called an oxidation induced stacking fault (OSF).

  It is known that the distribution of these defects in the grown single crystal silicon ingot depends on two factors, namely, the crystal pulling speed V and the temperature gradient G at the solid-liquid interface. FIG. 4 is a diagram showing the relationship between the ratio V / G of the pulling rate V to the temperature gradient G at the solid-liquid interface and the crystal region constituting the single crystal silicon ingot. As shown in FIG. 4, when V / G is large, the single crystal silicon ingot is dominated by the COP generation region 51 which is a crystal region where COP is detected. When V / G becomes small, a specific oxidation heat treatment is performed. As a result, an OSF latent nucleus region 52 that manifests as a ring-shaped OSF region is formed, and no COP is detected in the OSF region 52. In addition, since a COP generation region 51 occupies most of a silicon wafer collected from a single crystal silicon ingot grown under high-speed pulling conditions, COP is generated over almost the entire region in the crystal diameter direction.

  In addition, an oxygen precipitation promoting region (hereinafter also referred to as “Pv (1) region”) 53, which is a crystal region in which COP is not easily detected, is formed inside the OSF latent nucleus region 52.

  As V / G is decreased, an oxygen precipitation promoting region (hereinafter referred to as “Pv (2) region”), which is a crystal region in which oxygen precipitates exist and COP is not detected outside the OSF latent nucleus region 52. ) 54 is formed.

  Subsequently, when V / G is decreased, an oxygen precipitation suppression region (hereinafter also referred to as “Pi region”) 55, which is a crystal region in which COP is not easily detected due to oxygen precipitation, is formed, and dislocation clusters are detected. A dislocation cluster region 56 that is a crystalline region is formed.

  In a silicon wafer taken from a single crystal silicon ingot exhibiting such a defect distribution in accordance with the pulling speed, crystal regions other than the COP generation region 51 and the dislocation cluster region 56 are generally defect-free regions having no defects. A silicon wafer taken from a single crystal silicon ingot composed of these crystal regions, which is regarded as a crystal region, is a silicon wafer that does not contain dislocation clusters and COPs. Therefore, in the present invention, crystal regions other than the COP generation region 51 and the dislocation cluster region 56, that is, the OSF latent nucleus region 52, the Pv (1) region 53, the Pv (2) region 54, and the oxygen precipitation suppression region (Pi A silicon wafer taken from a single crystal silicon ingot made of any one of the region (55) crystal regions or a combination thereof is used as the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20.

  Here, the “silicon wafer not containing COP” in the present invention means a silicon wafer in which COP is not detected by observation and evaluation described below. That is, first, a silicon wafer cut out from a single crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (that is, ammonia water, hydrogen peroxide water, and ultrapure water are 1: 1: 15). The surface of the silicon wafer after cleaning is observed and evaluated using a Surfscan SP-2 manufactured by KLA-Tencor as a surface defect inspection device, and a bright spot defect estimated as a surface pit. (LPD: Light Point Defect) is specified. At this time, the observation mode is an Oblique mode (oblique incidence mode), and surface pits are estimated based on the detected size ratio of the Wide Narrow channel. The LPD thus identified is evaluated as to whether it is a COP by using an atomic force microscope (AFM). By this observation and evaluation, a silicon wafer in which COP is not observed is referred to as a “silicon wafer not including COP”.

  On the other hand, dislocation clusters are large (about 10 μm) defects (dislocation loops) formed as an aggregate of excess interstitial silicon, and are manifested by etching such as seco-etching or Cu decoration. By doing so, the presence or absence of dislocation clusters can be easily confirmed on a visual level. When a silicon wafer including a dislocation cluster is employed, a large amount of defects (such as stacking faults) originating from the dislocation cluster occur in the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20. A leak current is generated between the pn junctions via the defect, which affects the device characteristics.

When the single crystal silicon ingot is grown, if the oxygen concentration is too high, defects due to oxygen precipitates are likely to occur. In the case of a wafer in a crystal region including the OSF latent nucleus region 52, this defect is caused. In some cases, dangling bonds cannot be formed during the activation process. In order to suppress this, it is effective to reduce the oxygen concentration. Specifically, it is preferable to set the oxygen concentration to 6 × 10 ¹⁷ atoms / cm ³ or less (ASTM F121-1979). Further, from the viewpoint of thermal stress resistance of the wafer during the heat treatment in the device process, it is preferably set to 1 × 10 ¹⁶ atoms / cm ³ or more.

  Further, it is preferable that the plane orientations of the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are the same. Specifically, crystal orientation <100> and <110> can be mentioned. When the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 have different plane orientations, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 can be bonded together by a vacuum room temperature bonding method. However, when the subsequent heat treatment, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 constituting the pn-junction silicon wafer are displaced from each other, so that there are micro defects near the bonding interface of the pn-junction silicon wafer. This is because a leakage current caused by this minute defect is generated, which affects device characteristics.

  In the above, the manufacturing method of the pn junction silicon wafer by this invention was demonstrated about 1st-3rd embodiment. However, the manufacturing method of the pn junction silicon wafer according to the present invention is not limited to this.

(Pn junction silicon wafer)
Next, pn junction silicon wafers 100 and 200 obtained by the above manufacturing method will be described with reference to FIGS.

(First embodiment)
Referring to FIG. 1, pn junction silicon wafer 100 has a p-type single crystal silicon substrate 10 and an n-type single crystal silicon substrate 20 in contact with p-type single crystal silicon substrate 10. The oxygen concentration profile in the depth direction of the pn junction silicon wafer 100 is characterized by having no peak at the interface between the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20.

  According to the pn junction silicon wafer 100 of the present embodiment, leakage current can be suppressed in a vertical device. For this reason, the above explanation is used.

(Second Embodiment)
Referring to FIG. 2, pn junction silicon wafer 200 is in contact with p-type single crystal silicon substrate 10 and p-type single crystal silicon substrate 10 and has a dopant concentration higher than that of n-type single crystal silicon substrate 20. N-type silicon epitaxial layer 32 having a thickness of 50 μm or less, and n-type single crystal silicon substrate 20 in contact with n-type silicon epitaxial layer 32. The oxygen concentration profile in the depth direction of the pn junction silicon wafer 200 is characterized in that there is no peak at the interface between the n-type silicon epitaxial layer 32 and the n-type single crystal silicon substrate 20.

  According to the pn junction silicon wafer 200 of the present embodiment, leakage current can be suppressed in a vertical device, and device characteristics such as diode switching characteristics are further improved. For these reasons, the above description is incorporated.

  The p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are preferably silicon wafers that do not contain dislocation clusters and COPs. Moreover, it is preferable that the plane orientations of the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 are the same. For these reasons, the above description is incorporated.

  The first and second embodiments of the pn junction silicon wafer according to the present invention have been described above, but the present invention is not limited to these embodiments.

  For example, a pn-junction silicon wafer has an n-type single crystal silicon substrate and a p-thickness of 50 μm or less that is in contact with the n-type single crystal silicon substrate and has a dopant concentration higher than that of the p-type single crystal silicon substrate. And a p-type single crystal silicon group in contact with the p-type silicon epitaxial layer. In this case, the oxygen concentration profile in the depth direction of the pn junction silicon wafer has no peak at the interface between the p-type silicon epitaxial layer and the p-type single crystal silicon substrate. In addition, about the effect of this embodiment, description of 2nd Embodiment is used.

(Invention example)
By controlling the value of V / G by a known method so as not to include the COP generation region 51 and the dislocation cluster region 56 in FIG. 4, a silicon wafer not including the dislocation cluster and the COP is cut out, and a p-type single crystal silicon substrate is obtained. The crystal orientation is <100>, the diameter is 200 mm, the concentration of boron as a dopant is 4.4 × 10 ¹⁴ atoms / cm ³ , and the oxygen concentration (ASTM F121-1979) is 4.0 × 10 ¹⁷ atoms / cm ³ . A silicon wafer containing no dislocation cluster and COP was prepared. Similarly, a silicon wafer that does not contain dislocation clusters and COP is cut out, and an n-type single crystal silicon substrate has a crystal orientation <100>, a diameter of 200 mm, and the concentration of phosphorus as a dopant is 1.4 × 10 ¹⁴ atoms / cm ^3. Dislocation clusters having an oxygen concentration (ASTM F121-1979) of 5.0 × 10 ¹⁷ atoms / cm ³ and a silicon wafer containing no COP were prepared. Here, a natural oxide film having a thickness of 20 mm was formed on each surface layer of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate.

Next, according to the method shown in FIG. 1, a pn junction silicon wafer according to an example of the invention was manufactured. First, plasma is generated by flowing a source gas CF ₄ in a vacuum chamber at 25 ° C. and less than 1 × 10 ⁻⁵ Pa, and accelerated to one side of a p-type single crystal silicon substrate and one side of an n-type single crystal silicon substrate. F ⁻ was irradiated at a voltage of 300 eV. Here, the dose of fluorine ions was 2 × 10 ¹⁶ atoms / cm ² . As a result, one side of each of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate was etched to form an activated surface. By this etching treatment, the region where 20Å and oxygen were knocked on was removed from the respective surfaces of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate.

  Subsequently, both activated surfaces were brought into contact with each other at a vacuum room temperature, whereby the p-type single crystal silicon substrate and the n-type single crystal silicon substrate were bonded together to obtain a pn junction silicon wafer.

  Subsequently, the p-type single crystal silicon substrate and the n-type single crystal silicon substrate constituting the pn junction silicon wafer are ground and polished, and the thickness of the p-type single crystal silicon substrate is 100 μm. A pn junction silicon wafer having a thickness of 625 μm and a thickness of 725 μm was obtained.

(Comparative example)
First, the same p-type single crystal silicon substrate and n-type single crystal silicon substrate as those of the inventive examples were prepared. Next, according to the method shown in FIG. 5, a pn junction silicon wafer 300 according to a comparative example was produced.

First, a p-type single crystal silicon substrate 10 having a natural oxide film 12 formed on its surface by flowing Ar into a vacuum chamber at 25 ° C. and less than 1 × 10 ⁻⁵ Pa, and a natural oxide film on the surface. The n-type single crystal silicon substrate 20 on which 22 is formed is activated by irradiating Ar ⁺ at an acceleration voltage of 600 eV from each natural oxide film 12, 22 side, and both surfaces are activated surfaces. It was. Thereafter, both the activated surfaces were brought into contact with each other at room temperature under vacuum to bond the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 to obtain a pn junction silicon wafer.

  Subsequently, the p-type single crystal silicon substrate 10 and the n-type single crystal silicon substrate 20 constituting the pn junction silicon wafer are ground and polished, and the thickness of the p-type single crystal silicon substrate is 100 μm. A pn junction silicon wafer 300 having a substrate thickness of 625 μm and a thickness of 725 μm was obtained.

(Evaluation method)
The following evaluation was performed in the invention examples and the comparative examples.

<Concentration distribution of oxygen (SIMS measurement)>
First, in the inventive example and the comparative example, the oxygen concentration distribution in the vicinity of the bonding interface of the pn junction silicon wafer was measured by secondary ion mass spectrometry (SIMS). The measurement results are shown in FIG.

  Subsequently, the pn junction leakage measurement was performed on the pn junction silicon wafers according to the inventive example and the comparative example after performing a heat treatment corresponding to the heat treatment included in the device process. Here, the heat treatment corresponding to the heat treatment included in the device process was performed at 1100 ° C. for 2 hours in a nitrogen atmosphere.

<Measurement of pn junction leakage>
In the inventive example and the comparative example, an electrode for pn junction leak measurement was formed on the surface of the pn junction silicon wafer. Thereafter, the voltage on the surface on the p-type single crystal silicon substrate side was set to 0 V, and a voltage of 500 V was applied to the surface on the n-type single crystal silicon substrate side to perform pn junction leak measurement. Note that 500 V corresponds to a voltage (reverse bias) applied to the pn junction silicon wafer during device operation. The measurement results are shown in Table 1.

(Explanation of evaluation results)
First, in the comparative example, as shown in FIG. 6B, there was a peak in the oxygen concentration profile in the vicinity of the bonding surface. This peak indicates that oxygen in the natural oxide film remains in the pn junction silicon wafer. Therefore, as shown in Table 1, the leakage current could not be suppressed in the vertical device. On the other hand, in the inventive example, as shown in FIG. 6A, no peak was present in the oxygen concentration profile in the vicinity of the bonding surface. This is because oxygen in the natural oxide film is removed from the pn junction silicon wafer by the etching action of fluorine ions. At this time, as shown in Table 1, the leakage current was significantly suppressed in the vertical device.

  According to the present invention, a pn junction silicon wafer capable of suppressing leakage current in a vertical device can be manufactured.

100,200 pn junction silicon wafer 10 p-type single crystal silicon substrate 10A activated surface 12 natural oxide film formed on the surface of the p-type single crystal silicon substrate 20 n-type single crystal silicon substrate 20A activated surface 22 n-type single crystal Natural oxide film formed on the surface of the silicon substrate 32 n-type silicon epitaxial layer 32A Activation surface 34 Natural oxide film formed on the surface of the n-type silicon epitaxial layer 40 Vacuum room temperature bonding apparatus 41 Plasma chamber 42 Gas inlet 43 Vacuum Pump 44 Pulse voltage application device 45A, 45B Wafer fixing base 51 COP generation region 52 OSF latent nucleus region 53 Oxygen precipitation promotion region (Pv (1) region)
54 Oxygen precipitation promotion region (Pv (2) region)
55 Oxygen precipitation suppression region (Pi region)
56 Dislocation cluster region

Claims (12)

a first step in which one side of a p-type single crystal silicon substrate and one side of an n-type single crystal silicon substrate are irradiated with fluorine ions at room temperature in a vacuum, and both of the one side are etched to form an activated surface; ,
Subsequent to the first step, both the activated surfaces are brought into contact with each other at a vacuum room temperature, thereby integrating the p-type single crystal silicon substrate and the n-type single crystal silicon substrate, thereby obtaining a pn junction silicon wafer. A second step of obtaining,
A method for producing a pn junction silicon wafer, comprising: Prior to the first step, forming an n-type silicon epitaxial layer having a thickness of 50 μm or less and having a dopant concentration higher than that of the n-type single crystal silicon substrate on one surface of the p-type single crystal silicon substrate. Have
In the first step, instead of one side of the p-type single crystal silicon substrate, the surface of the n-type silicon epitaxial layer is irradiated with fluorine ions at room temperature in a vacuum, and the surface is etched to activate. The method of manufacturing a pn junction silicon wafer according to claim 1, wherein the surface is a surface. Prior to the first step, forming a p-type silicon epitaxial layer having a dopant concentration higher than that of the p-type single crystal silicon substrate on one side of the n-type single crystal silicon substrate and having a thickness of 50 μm or less Have
In the first step, instead of one surface of the n-type single crystal silicon substrate, the surface of the p-type silicon epitaxial layer is irradiated with fluorine ions at room temperature in a vacuum, and the surface is etched to activate. The method of manufacturing a pn junction silicon wafer according to claim 1, wherein the surface is a surface. 4. The pn according to claim 1, wherein a dose amount of the fluorine ions irradiated in the first step is 1 × 10 ¹⁵ atoms / cm ² or more and 1 × 10 ¹⁸ atoms / cm ² or less. Manufacturing method of bonded silicon wafer.   The manufacturing method of the pn junction silicon wafer as described in any one of Claims 1-4 whose said p-type single crystal silicon substrate and said n-type single crystal silicon substrate are silicon wafers which do not contain a dislocation cluster and COP.   The method for producing a pn junction silicon wafer according to any one of claims 1 to 5, wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate have the same plane orientation.   The method according to claim 1, further comprising a step of grinding and polishing at least one of the p-type single crystal silicon substrate and the n-type single crystal silicon substrate constituting the pn junction silicon wafer after the second step. A method for producing a pn junction silicon wafer according to claim 1. a p-type single crystal silicon substrate;
An n-type single crystal silicon substrate in contact with the p-type single crystal silicon substrate;
A pn junction silicon wafer having
A pn junction silicon wafer characterized by having no peak at the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate in an oxygen concentration profile in the depth direction of the pn junction silicon wafer. An n-type silicon epitaxial layer having a dopant concentration higher than that of the n-type single crystal silicon substrate and having a thickness of 50 μm or less is further interposed between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. Have
In the oxygen concentration profile in the depth direction of the pn junction silicon wafer, the n-type silicon epitaxial layer and the n-type single crystal are used instead of the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. The pn junction silicon wafer according to claim 8, which has no peak at the interface with the silicon substrate. A p-type silicon epitaxial layer having a dopant concentration higher than that of the p-type single crystal silicon substrate and having a thickness of 50 μm or less is further interposed between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. Have
In the oxygen concentration profile in the depth direction of the pn junction silicon wafer, the p-type silicon epitaxial layer and the p-type single crystal are used instead of the interface between the p-type single crystal silicon substrate and the n-type single crystal silicon substrate. The pn junction silicon wafer according to claim 8, which has no peak at the interface with the silicon substrate.   The pn junction silicon wafer according to any one of claims 8 to 10, wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate are silicon wafers containing no dislocation clusters and COPs.   The pn junction silicon wafer according to any one of claims 8 to 11, wherein the p-type single crystal silicon substrate and the n-type single crystal silicon substrate have the same plane orientation.

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