JP2002507058A - Equipment that can be formed by low-temperature direct bonding - Google Patents

Abstract

(57) Abstract: A semiconductor device comprises a semiconductor base (82, 96) extending in a lateral direction, a buffer (83) adjacent to the base and having a first conductivity type dopant, and an adjacent to the buffer and opposite to the base. A laterally extending emitter (85) having a second conductivity type dopant. The buffer (83) is thin and provides the semiconductor device with a negative temperature coefficient for increasing current and a positive temperature coefficient for forward voltage, so that the first conductivity type is higher than the second conductivity type dopant concentration of the adjacent emitter section. Having a dopant concentration. The buffer is silicon or germanium. The low-temperature junction type interface (103) is provided between the emitter and the buffer or between the buffer and the base. Another embodiment of a semiconductor device includes a localized lifetime kill portion (92, 102) that extends laterally between a first lateral extension portion and a second lateral extension portion that are doped in opposite polarities. )including. The localized lifetime kill portion has a plurality of lifetime kill regions that are limited in the lateral direction and have a gap in the lateral direction. Another semiconductor device has one or more PN junctions.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to the field of semiconductors, and more particularly, to a method of manufacturing a power semiconductor device and a semiconductor device manufactured by the method.

[0002] Power switching devices are widely used in numerous applications such as, for example, motor control, inverters, line switches, pulse circuits, and other power switching applications. A silicon controlled rectifier (SCR) or thyristor is a bistable semiconductor switching device formed from four layers of silicon. One type of power switching device, a MOS controlled thyristor (MCT), is particularly suitable for resonant (zero voltage or zero current) switching applications. MCTs have a forward voltage drop very similar to SCRs, with significantly reduced conducted power losses. MCTs can control high power circuits with very small amounts of input energy. This feature is common to SCRs. In the case of an MCT, turn-off is achieved by turning on a highly combined off-FET to short-circuit one or both emitter-base junctions of the thyristor.

[0003] Another advantageous power switching device is an insulated gate bipolar transistor (IGBT) designed for high voltage, low dissipation applications such as switching regulators and motor drives. IGBTs can be operated from low power integrated circuits. The IGBT is an insulated gate type and is the same electric field control type switching device as the MCT. Available MCTs and IGBTs are useful, for example, at higher switching frequencies than typically realized in power Darlington transistors. Additionally, MCTs and IGBTs operate at junction temperatures of 150 ° C. or higher and operate in switching circuits with switch ratings of 600 volts or higher.

One solution for manufacturing power switching devices is semiconductor-semiconductor direct wafer bonding. Wafer bonding is performed, for example, with a thickness of 100 μm.
For the purpose of replacing the thick epitaxial layer growth. For this bonding application, a high temperature bonding anneal at a temperature of about 1100 ° C. or higher is typically used to remove microwaves and bubbles. Both hydrophobic and hydrophilic bonding are used.

In recent years, MOSFE has been provided on both the front and back surfaces so that turn-off can be performed at higher speed.
There is increasing interest in the possibility of manufacturing switching power supplies provided with a T-current controller. Such power supplies are described, for example, in US Pat. No. 4,977, issued to Abbas.
No. 438. A conventional solution for manufacturing a double-sided MOSFET-controlled power supply involves a process and photographic steps on both sides of the wafer.
This solution, which requires very important control of the heat source, approximately doubles the number of manufacturing steps and increases the yield loss due to scratches and the like.

US Pat. No. 5,541,122 issued to Tu et al. Discloses, for example, an IGBT in which two wafers are bonded together and annealed at a temperature in the range of 800 ° C. to 1100 ° C.
Is disclosed. The N-type wafer is N + doped on the surface and bonded to the P + wafer to define an N + buffer region for the IGBT. Next, a gate is formed on the top surface and various diffusions are performed near the emitter-collector gate to define an emitter / collector surrounding the gate. An emitter contact is formed on the diffuser and a collector contact is deposited on the underside of the wafer using conventional techniques.

[0007] Unfortunately, fairly high temperature annealing and subsequent device processing steps adversely affect the doping profile of the buffer layer. Therefore, the turn-off speed is low. Furthermore, double-sided processing after annealing requires a very large number of process steps, and the substrate is susceptible to mechanical damage that reduces yield.

In view of the background art described above, it is an object of the present invention to provide improved features and characteristics to a semiconductor device that can be easily manufactured.

A semiconductor device according to a first embodiment, in which the above and other objects, effects, and features of the present invention are obtained, includes a semiconductor base extending in a lateral direction, a buffer adjacent to the base, and having a first conductivity type dopant, A laterally extending emitter having a second conductivity type dopant adjacent the buffer and opposite the base. Since the buffer is very thin and provides the semiconductor device with a negative temperature coefficient for increasing current and a positive temperature coefficient for forward voltage to the semiconductor device, the first conductivity type dopant is higher than the second conductivity type dopant concentration of the adjacent emitter section. Has a concentration. A negative temperature coefficient for increasing current reduces the thermal emissions of the semiconductor device and provides better short circuit protection.

[0010] The base may contain a first conductivity type dopant at a lower concentration than the first conductivity type dopant concentration in the buffer. Also, the buffer may be less than about 10 microns thick, and more preferably has a thickness in the range of about 200 to 500 nanometers. The dopant concentration of the buffer is preferably greater than or ^{equal to} about 3 × 10 ¹⁶ cm ⁻³ in one embodiment, and greater than or ^{equal to} about 1 × 10 ¹⁷ cm ⁻³ in another embodiment.

[0011] At least one of the base and the emitter comprises silicon, and in one embodiment, the buffer comprises silicon. In another embodiment, the buffer contains germanium.

The semiconductor device is formed by low-temperature bonding as described in detail below.
Thus, in one embodiment, the device further comprises an interface (junction interface) between the emitter and the buffer. The bonding interface may be provided between the buffer and the base. The bonding interface is preferably substantially free of oxide.

In one variation of the apparatus, the emitter has an epitaxial portion adjacent the buffer and a second portion opposite the epitaxial portion. Further, the semiconductor device may include a MOS formed on at least one of the first portion and the second portion.
Includes FET current control devices or other current control devices.

Yet another apparatus according to the present invention includes a localized lifetime kill portion that extends laterally between a first laterally extending portion and a second laterally extending portion that are doped in opposite polarities. Including.
The localized lifetime kill portion has a plurality of lifetime kill regions that are limited in the lateral direction and have a gap in the lateral direction. The bonding interface is provided between the localized lifetime kill portion and one of the first portion and the second portion. The interface is substantially free of oxide. The lifetime kill area is preferably, for example,
A predetermined distance, such as about 10 microns, is provided longitudinally from the bonding interface.

[0015] Each lifetime kill region includes at least one of a defect and implanted impurities. Further, the lifetime kill area is a circular shape having a diameter of about 2-2 μm,
There are 20 μm intervals. Alternatively, each lifetime kill region may be a band having a width of about 2 to 20 microns. Adjacent strips are separated by about 5 to 20 microns.

Another aspect of the invention involves a device having one or more PN junctions. The semiconductor device includes a first portion that includes a first conductivity type dopant and extends in a lateral direction; a second portion that includes the first conductivity type dopant and extends in a lateral direction on the first portion; And at least one doped region of the second conductivity type formed in the first portion adjacent to the interface between the second portion and the second portion and defining at least one PN junction. Further, the conductive layer may be disposed between at least one doped region and the second portion to reduce the resistance of the PN junction. The conductive layer is, for example, a metal or a silicon compound.

One implementation of a PN junction is to provide spaced junctions to define a vertical junction field effect transistor. The conductive layers may be arranged in a grid, in which case the device is a penetration base transistor. At least one of the first portion and the second portion may be silicon. Further, the bonding interface is provided between the first portion and the second portion. The bonding interface is preferably substantially free of oxide.

According to the present invention, there is provided a first portion including a first conductivity type dopant and extending in a lateral direction;
Semiconductor having a second portion including a dopant of a conductivity type and extending laterally on a first portion and a third portion including a dopant of a second conductivity type and extending laterally on a second portion It also relates to the device. At least one of the first portion and the second portion preferably has a higher dopant concentration than the third total dopant concentration. Further, the device preferably has a first active control device provided on an outer surface of the first part and a second active control device provided on an outer surface of the third part.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings showing preferred embodiments of the present invention. However, the invention can be implemented in many different forms,
The present invention is not limited to the embodiments described below. Rather, these embodiments are provided so that this disclosure will be thorough, and will fully convey the scope of the invention to those skilled in the art. Throughout the drawings, the same reference numbers designate the same elements.

First, an aspect of the manufacturing method of the present invention will be described with reference to a flowchart 50 shown in FIG. In this embodiment, a first wafer and a second wafer are processed. In the figure, the processing block for the first wafer is given the suffix "a" and the processing block for the second wafer is given the suffix "b". In the following, only the processing steps for the first wafer will be described in detail, but those skilled in the art will readily understand that in the present embodiment, similar processing steps can be selectively performed for the second wafer. I will admit.

The method starts at step 51, and at step 52a, a getter layer is formed on a second side of the first wafer, ie, the B side. The getter layer is effective in removing contaminants such as, for example, boron, as will be readily apparent to those skilled in the art. The getter region diffuses the lifetime kill transition metal from the wafer mass to the getter site before thinning and direct bonding. As will be apparent to those skilled in the art, typical gettering techniques include phosphorus diffusion, ion implantation, or argon or carbon and / or polysilicon deposition on the B side of the wafer.

In step 54a, one or more active devices are formed on the first side of the first wafer, ie, the A side. Active devices include one or more doped regions as formed by the prior art, as will be apparent to those skilled in the art. In one embodiment, a metal interconnect is formed as described in more detail below. Typical processing steps include at least one of implantation, diffusion, metal deposition, polysilicon deposition, silicide formation, oxide growth, and the like. Equal or heterogeneous MOSFET current controlled devices are fabricated on the first and second substrates. Devices formed in accordance with the present invention are defined to have current conduction in the vertical direction, i.e., perpendicular to the interface formed between the integrally joined surfaces, as will be apparent to those skilled in the art. Can be Operating a single-sided or double-sided device generally requires a flow of minority carriers for conductivity modulation across the interface. When the device has an N-base, it is desirable to inject a high density of holes (minority carriers) into the N-base to cause conductivity modulation. The condition of the conductivity modulation is that the electron and hole densities in the base are equal. Since conductivity modulation increases the electron density significantly above its equilibrium value, the N-base resistance is significantly reduced, as will be apparent to those skilled in the art.

The first wafer is fixed to a handling wafer or a support film (
In steps 56a) and 58a, the first wafer is thinned on the B side, thereby removing gettering layers and contaminants contained in the gettering layers. Wafers are thinned, for example, by grinding to reduce the thickness to less than about 200 μm, although thinner wafers are preferred for some applications. The handling wafer or support film is removed after thinning.

Side B is polished and cleaned in step 60a to minimize hydrocarbon voids and reduce oxygen at the final bonded interface. When a metal, such as a metal bond pad, is exposed on the surface, it is advantageous to protect the metal from the chemicals used to clean the wafer. One feasible technique for this is to deposit a protective insulating layer that is resistant to chemicals. The insulating layer can be removed after the wafer has been bonded. A polishing process such as chemical mechanical polishing (CMP) is used, and the surface of the B-side has a root mean square (RMS) surface roughness of less than about 1 nm. For surface roughness less than about 10 nm, it is desirable to bond two substrates directly to one. Furthermore, if pressure is used in the bonding process, a slightly worse surface roughness may be acceptable. Pressure is required during bonding because wafers tend to distort due to the presence of a thick dielectric layer. Of course, bonding may be performed at elevated temperatures, for example, from 200 ° C. to 400 ° C., as will be apparent to those skilled in the art.

Cleaning is the removal of hydrocarbons, organics, and metallic impurities from the surface. The cleaning process generally uses chemicals such as those used in RCA Clean and Piranha Cleans, as will be apparent to those skilled in the art. Plasma, UV,
Ozone and laser irradiation are used to clean the surface before bonding.

Etching is performed using dilute hydrofluoric (HF) acid to remove native oxides. It is desirable to minimize native oxide regrowth prior to bonding. In the case of silicon, one solution is to hydrogen terminate the silicon surface using a dilute HF etch, followed by an anhydrous rinse or minimal water rinse. Another more complex solution to minimize native oxides is to use two layers in an environment such as vacuum or purified nitrogen, argon, or hydrogen with a minimum oxygen concentration. Direct bonding of wafers. Possible bonding anneal environments include nitrogen, oxygen, argon, and hydrogen. One possible mechanism by which bond strength increases with annealing time is that in which hydrogen diffuses laterally along the bond interface and is released from the wafer. The environment affects the degree to which hydrogen can diffuse laterally.

As will be appreciated by those skilled in the art, native oxides prevent current flow through the interface.
The hydrophobic method is easily affected by hydrocarbon absorption, but the hydrophilic bonding method in which a thin oxide is present at the interface is not easily affected by hydrocarbon absorption.

Hydrogen termination, as will be apparent to those skilled in the art, means that most of the surface area will lose oxygen. In other words, native oxides or oxygen present at the surface are removed or minimized. Further, cleaning is desirable to remove contaminants such as hydrocarbons or metals from surfaces to be joined. It is considered that no oxide is contained at the interface. Power switching devices can operate even in the presence of very thin oxide layers. However, the oxide layer must be thin enough so that both electrons and holes can pass through the oxide. For example, it is desirable that the oxide layer be less than about 1 nm for satisfactory operation.

In step 62 a, side B of the first wafer is selectively implanted with dopants for lifetime kill and / or for layers in the power device, as described in more detail below. For example, ion implantation of proton, helium, carbon, argon, oxygen, etc. is used. A lifetime kill metal, such as platinum or gold, is implanted or diffused into the surface. Since the temperature required to diffuse the metal is typically higher than about 450 ° C., aluminum cannot be used on the back side during annealing.

In order to optimize the relationship between forward voltage and turn-off time, it is desirable for the power device to have a localized lifetime kill region rather than a uniform lifetime kill. In particular, the lifetime kill area is easily understood by those skilled in the art,
It is often desirable to localize in the N-type base region near the backside of the P + emitter anode and / or in the IGPT or MCT P + emitter. It is advantageous to localize the lifetime kill implant both horizontally and vertically. In this case, a photolithography step, or metal mesh, is used to laterally limit higher energy protons in certain areas.

It is desirable to provide an ultrathin dopant layer at or near the bonding interface of one or both of the wafer and the substrate. Since all high temperature processing steps are performed on the wafer before thinning, a high temperature step to diffuse the dopant in the thin region is not needed later, so the ultra-thin dopant layer at or near the junction interface is: Obtained by ion implantation or laser doping. Laser annealing of the implanted dopant is performed to activate the dopant, as will be readily appreciated by those skilled in the art.

As another example, a photolithography step is used to locate the implanted dopant. For example, in some cases, the implantation into the N + buffer layer may be determined for the IGBT or the MCT so that minority carriers are hardly injected into the region near the outside of the chip in order to realize a fast turn-off. desirable.

Since a plurality of individual dies are typically provided on the wafer, these dies are tested (step 64a) and the test results are used later for correlation with a second substrate. This improves overall process yield. However, yet another aspect of the present invention involves cutting the wafer along the outer street (step 66a). Thereby, the first wafer and the second wafer are precisely aligned in step 68. After the wafers are properly aligned, the wafers are collected at a center point and joined by atomic bonding to spread the wafers out of the center. In certain embodiments, it is desirable to have an ultra-high or ultra-high vacuum during the bonding process. The two wafers may be aligned based on the crystal orientation of the two wafers, as will be apparent to those skilled in the art.

At step 70, a low temperature anneal is performed. In particular, if aluminum is added later, the temperature will be less than about 800 ° C, but may be 450 ° C or less if aluminum metal interconnects are already provided. When the barrier metal layer is provided between the aluminum and the silicon substrate, for example, annealing at a higher temperature of about 450 to 550 ° C. is also allowed. The best overall yield is achieved when the two wafers have been completely processed before bonding.

As mentioned above, an important bond strength requirement is that the strength be sufficient to perform sawing or dicing during the 400 ° C. anneal. Therefore, 800
An interface energy of ergs / cm ² is empirically required. The 400 ° C. anneal is cold enough to potentially delay the formation of the Si—Al eutectic, as will be apparent to those skilled in the art. In another embodiment, laser cutting is used, and lower bonding strengths are acceptable, as will be apparent to those skilled in the art.

In step 74, if no further processing is required, the individual device dies /
The circuit is diced from the integrally bonded wafer using conventional techniques known to those skilled in the art. Power switching devices made in accordance with the present invention have current transport through the bonding interface, ie, perpendicular to the bonding interface.

The method of the present invention is a method of manufacturing a double-sided MOSFET controlled power switching device in which the number of sequential process steps is significantly reduced to about half of the prior art. The direct bonding method can refer to a conventional manufacturing recipe for manufacturing single-sided power devices, without having to develop a separate process sequence. The present invention avoids the tight control of the heat source as in conventional processing because the anneal is optimized for one dopant on the front surface of the substrate and not for another on the back surface. The conventional method causes a loss in yield due to scratches or the like. The present invention solves these disadvantages, and can remove metal impurities before bonding by a gettering operation. Yield is optimized by mapping the working dies to two wafers and aligning the wafers for best yield.
Direct bonding after processing according to the present invention is, for example, a high performance IGBT, MO
Used to implement SFETs and MCTs. Direct bonded devices have an ultra-thin N + buffer layer and can significantly improve turn-off time over alternative approaches detailed below. In addition, the direct junction type IGBT and M
A novel feature of CT is that it has a positive temperature coefficient for the forward voltage obtained by a negative temperature coefficient for the current increase.

It is also advantageous to join the silicon MOSFET current controlled voltage device in the first substrate to a second substrate containing a SiC material. Other material candidates for the second substrate include Ga
N, InP, and GaAs are included. Wide bandgap materials, such as SiC, typically have a high critical field of electrical breakdown and a high saturation drift velocity. Therefore, wide bandgap materials are desirably used to support most high voltage drops between depletion layers in power devices. Another reason for selecting a material other than silicon as the material for the second substrate is to obtain high thermal conductivity. SiC is used for the second substrate because it has three times the thermal conductivity of silicon. Of course, in other embodiments, two or more non-silicon substrates are processed,
It may be joined according to the invention.

Referring to FIGS. 2-5, one aspect of the invention is to fabricate two MOSFET current controllers on two separate wafers, thin the wafer from the back to about 200 μm, This is a method for realizing a double-sided MOSFET controlled power switching device using low-temperature direct semiconductor-semiconductor wafer bonding by performing aligned bonding. The greatest advantage of this approach is obtained when the two wafers are almost completely processed before bonding. In this case, the aluminum interconnect is on the surface and the maximum allowable bonding anneal temperature is about 4
50 ° C. When a barrier metal is used between the aluminum and silicon bond, a bond anneal temperature of about 450-550 ° C is used. In the absence of metal interconnects, higher temperature bonding anneals are allowed. In this case, the MOSFET current control wafer is fabricated by a contact window photo step. One important requirement is that the bonding anneal does not cause excessive diffusion of the source / drain implant, where 800-90
Bond anneal temperatures in the range of 0 ° C. are acceptable.

The initial processing of the first substrate 80 is shown in FIG. The first substrate 80 has a double-sided M
To generate CT 110 (FIG. 6), a second substrate 95 will be apparent to those skilled in the art.
Directly bonded to The gettering implantation 91 is performed as already described in detail. Next, as shown in FIG. 3, various dopant regions are formed on the upper surface of the substrate 80 together with the second gate region 81. The illustrated processed portion includes an N-type base 82, an N-type buffer layer 83 on the N-type base, and a P + emitter 85 on the P-type base. The substrate 80 further has an anode layer 86 and an N + region 87.

The first substrate 80 is connected to a handling substrate 90 or wafer, and the gettering layer 91 is removed by thinning to create the intermediate structure shown in FIG. Lifetime killing (lifetime killer) implantation 92 is shown in FIG.
Is formed on the substrate 80 as schematically shown in FIG. In FIG. 6, the first substrate 80 thus treated is cleaned, directly bonded, and after low-temperature annealing,
It is bonded to the second substrate 95. The second substrate 95 includes, for example, an N-type base 96, a P-type base 97 on the N-type base, an N + emitter 98 on the N-type base,
, A gate layer 99, a cathode layer 100, and an exemplary P + region 101. Second
Substrate 95 further includes, for example, a lifetime killing implant 102. Interface 103 is shown schematically between first substrate 80 and second substrate 95.

Special considerations are made for realizing a double-sided switching power device using low temperature direct bonding. As a first requirement, substantially ideal current conduction is required between bonding interfaces. Therefore, the amount of native oxide that can be present at the bonding interface is minimized. Previous work has shown that by using hydrophobic bonding where the silicon surface is hydrogen terminated, a bonding interface with minimal native oxide is obtained. Further consideration needs to be given to reducing boron and heavy metal contaminants during surface cleaning operations. Another requirement is that bubbles and microvoids be minimized at the bonding interface.

Low temperature, hydrophobically bonded wafers are particularly susceptible to hydrocarbon generated voids, and special attention should be paid to the cleaning process to remove hydrocarbons. Yet another requirement is that minority carrier recombination at the bonding interface be low. Low-temperature direct bonding is a conventional method (1100 ° C).
In contrast to the high temperature annealing bonding, since the drive energy for forming defects is small, the number of defects due to the lattice mismatch between two wafers included in the interface bonded at low temperature is advantageously reduced.

Referring to FIGS. 7-12, the results from the bonding experiments show that N-type vs. N-type and P-type vs. P-type silicon <100> wafers have either conduction band or valence band. That it can be hydrophobically bonded using a low temperature anneal without creating a potential barrier. The treatment used to achieve a hydrogen terminated surface includes a combination of O ₂ plasma and piranha clean, followed by a 10: 1 HF dip, with no rinsing after the HF dip. Electrical data for N-type wafers and N-type wafers for multiple annealing temperatures is shown in FIG.

The presence of the potential barrier appears in the resistance characteristics as the nonlinearity of the resistance to low bias. No potential barrier appears for annealing at 600 ° C and 700 ° C. The resistance is
Increased for 800 ° C. anneal, non-linear, indicating barrier formation. 100
For 0 ° C. annealing, the resistance decreases and there is no nonlinearity. If bonding is not required, the potential barrier observed for the 800 ° C. anneal is induced by activation of boron present on the wafer surface prior to bonding by boron absorbed from the atmosphere. In the case of a 1000 ° C. anneal, boron diffuses from the interface, reducing the height of the potential barrier.

Furthermore, the dependence of the resistance on a given area as a function of the area and the variation of the resistance was investigated to evaluate the quality of the junction interface. FIG. 8 shows a plot of resistance versus reciprocal area and a plot of resistance variation for an N-type wafer versus an N-type wafer annealed at 400 ° C. for 9 hours. FIG. 9 shows similar results for P-type to P-type bonds annealed at 400 ° C. for 24 hours.

The electrical properties of PN junctions prepared by low-temperature hydrophobic bonding were also investigated. FIG. 10 shows the forward and reverse current-voltage characteristics of 20 diodes fabricated from a P-type wafer and an N-type wafer hydrophobically bonded during a 600 ° C. bond anneal. The leakage current density is about 40 nA / cm ² for hydrophobically bonded wafers. This measurement shows a strong dependence on area, with the diode with the smallest area having the largest ideality factor value. The cause of the increase in the ideality factor value above 1.0 is typically a metallurgical bond or recombination of minority carriers occurring around the device. The measured dependence on the area indicates that the high ideality factor is due to recombination occurring at the edges of the unpassivated sawed mesa. The ideality coefficient increases with increasing diode area, l. Reaches the value of 0. There is the best ideality factor for low temperature bonded devices.

An important requirement in addition to the electrical properties is that the bond strength be sufficient for annealing at 400 ° C. for sawing or dicing the switching power device. From experience, bond interfacial energies above 800 ergs / cm ² are required to provide sufficient bond strength. FIG. 12 shows that the bond strength, representing the first order response to the bond reaction rate at 400 ° C., increases logarithmically with annealing time. The 400 ° C. anneal is chosen because this temperature is sufficiently low that it may slow the formation of the Si—Al eutectic.

According to experimental measurements, low-temperature direct wafer bonding is a dual gate MOS
It can be seen that this is a suitable method of manufacturing a FET controlled switching power device.
Nearly ideal electrical conductivity through the banding interface is obtained for bond anneal temperatures between 400 ° C and 700 ° C. The developed hydrophobic cleaning process minimizes hydrocarbon-generated voids and contains very little oxygen at the bonding interface. A bond interface energy of 1000 ergs / cm ² is about 9 at 400 ° C.
Obtained during the time anneal, which is sufficient to allow sawing of the wafer.

Another aspect of the present invention will be described with reference to FIG. Since a low bonding anneal temperature is used in accordance with the present invention, if necessary, a metal or silicon compound formed on one or both substrates prior to bonding, such that a low resistance is obtained at the interface PN junction. It is possible to define a line. A feasible process to achieve a low resistivity metal or silicide strap PN junction is to use photolithography to reliably implant a P-type dopant 121 into an N-type substrate 122 of an intermediate structure 120, as shown in FIG. Is to use steps. A second photo step is used to define the location of the metal or silicide piece 123 within the P-type dopant region 121. A resist mask is used to etch about 100 nm of silicon. About 30 nm of tungsten is deposited. Excess tungsten on the resist surface is removed by lift-off, and then annealing is performed to form a tungsten silicon compound 123. As will be readily appreciated by those skilled in the art, another solution is to use a polishing technique to polish the silicon compound formed on the silicon surface back planar with the adjacent silicon surface. This silicide is used to lower the resistance of the blanket doping layer so as to lower the P-type base resistance of the gate turn-off thyristor.

Referring to FIG. 14, a low resistance PN junction grid is used as the gate of vertical JFET 130. The illustrated pair of junctions 131 and 132 is used to modulate the current flow orthogonal to the junction, ie, the current flow through the interface 134. Of course, a plurality of junctions may be formed. Depletion region 135 is formed around P-doped region 123, as will be apparent to those skilled in the art. In yet another variation of the invention, the MOS gate is formed on the side of the trench and operates in a depletion mode in which current conducts between channels with zero source-gate bias. The grid of silicide lines at the interface between the two substrates 125 and 122 is:
As will be readily appreciated by those skilled in the art, a reverse-biased Schottky diode is used to form a permeable base transistor that is used to modulate the current flow orthogonal to the grid of silicide lines 123.

For the PN junction, the low-resistance P-type base layer, and the Schottky diode, it is necessary to provide a contact from the upper surface of any one of the substrates to the silicon compound. Vias are chemically or plasma etched into the silicide or metal layer from the top surface of either substrate using the silicide or metal layer as an etch stop layer. Another suitable technique is to laser drill the vias through top surface 125 (FIG. 13) and stop at the metal or silicide layer.

Yet another aspect of the invention is that a semiconductor layer can be epitaxially grown on one or both substrates before bonding. When aluminum interconnects are present on the substrate, the epitaxial growth should be performed at temperatures below 450 ° C and, if the barrier metal layer is used as described above, between 450 ° C and 550 ° C or less. For example, as shown in FIG. 15, to define a SiGe heterojunction layer 141 on the silicon surface of substrate 145 before bonding to second substrate 150,
An ultra-thin N + buffer layer can be grown. The completed IGBT 140 includes an anode layer 142, a P + substrate emitter layer 143 adjacent to the anode, and a SiGe buffer layer 141 adjacent to the interface 144. The upper surface 150 is formed on the external emitter layer 151.
And a gate layer 152 and an insulating layer 153 thereunder. The upper surface 150
It further has an N-type base 155 including the lifetime killing implant 156 described above. Other doped regions on top surface 150 are well known to those skilled in the art and will not be described further. A properly configured SiGe base-emitter heterojunction has a negative temperature coefficient for increasing current and a positive temperature coefficient for forward voltage. This property provides short circuit protection and helps prevent heat dissipation, as will be apparent to those skilled in the art.

An ultra-thin high-concentration dopant layer can be grown on the surface of the substrate before bonding. For example, as shown in IGBT 160 of FIG. 16, an ultra-thin N + buffer layer 161 is grown on lower substrate 162. IGBT 160 of FIG.
Are similar to those of FIG. 15 and are indicated by the same reference numerals. Therefore, a person skilled in the art will not need to elaborate in any more detail. The N + buffer layer is, for example, a thin layer of about 200 nm having an N-type dopant concentration of about 1 × 10 ¹⁹ cm ⁻³ such as arsenic, antimony, or phosphorus is implanted on the surface of the P + substrate. It is manufactured by P + substrate includes a P-type dopant concentration of about 3 × ^{10 16} to ¹ × ¹⁰ 1 9 ^{cm -3.} The substrate is annealed at a temperature of about 900-1000 ° C. to anneal defects formed during ion implantation, as will be readily appreciated by those skilled in the art.

As the N + buffer layer 161 becomes thinner, the turn-off time becomes shorter. Typically, just prior to turn-off, most of the stored base charge is in the N + buffer layer 16.
1 or in the N + buffer layer 161. Therefore, as will be readily appreciated by those skilled in the art, as the N + buffer layer 161 becomes thinner, the accumulated base charge approaches the P + emitter 143, and the accumulated base charge reaches the P + emitter and is recharged. The distance that must be spread to combine is reduced.

It is desirable to prevent minority charge carriers from being injected into regions outside the active region.
A technique for blocking injection is to reduce the efficiency of injection of holes into the region. Therefore, a photolithography step is performed to define a thick N + implant outside the active area, which reduces implantation efficiency. Other techniques may be used, such as defining an oxide barrier at the bonding interface 144.

[0057] Thin epitaxial layers of SiGe or high N-type dopants provide major advantages to high performance IGBTs or MCTs. For example, a thin high-concentration dopant layer requires a short turn-off time and a negative temperature coefficient for increasing current,
Used for N + buffer of IGBT. Of course, if the substrate is used as an N + emitter, the device is processed to provide a P + ultra-thin buffer layer, as will be readily apparent to those skilled in the art.

When the doping concentration of the N + buffer layer 161 is higher than the doping concentration of the P + emitter 143, the current of the backside emitter of the IGBT 160 or the MCT increases due to the physical characteristics of the semiconductor device having a narrow band gap in the highly doped semiconductor. It can be seen that a negative temperature coefficient for can be obtained. The equation for this principle is:

Electron injection efficiency (EIE) = J_e/ J_h  And

[0060]

(Equation 1) It is. Assuming a short base, ie, w >> L,

[0061]

(Equation 2) It is.

Case 1: Eg _N > Eg _P → + δEg

[0063]

[Equation 3] Thus, EIE decreases with increasing temperature.

Case 2: Eg _P <Eg _N

[0065]

(Equation 4) Thus, EIE decreases with increasing temperature.

The device physical properties of the P + emitter with the N + base buffer layer having a higher concentration than the P + emitter produce a negative temperature coefficient for increasing current. FIG. 17 shows profiles for various parts of the device near the interface. The interface is on one side of the N + buffer, as will be apparent to those skilled in the art. A negative temperature coefficient for increasing current means that the current of the IGBT or MCT decreases with increasing temperature.
A current that decreases at higher temperatures means that the forward voltage increases. Therefore, the IGBT and the MCT have a positive temperature coefficient with respect to the forward voltage. IGB
A positive temperature coefficient for the forward voltage for both T and MCT is important to prevent heat dissipation and provide a short circuit protection circuit.

When designing an N + buffer layer, it is important to provide a higher N + buffer concentration than the P + emitter. However, the N + buffer is the P + of IGBT and MCT.
It should be thin enough to give sufficient current gain to the backside emitter.

The approach of using a pre-fabricated substrate containing a direct bond or MOSFET current controller is particularly suitable for fabricating IGBTs or MCTs where the N + buffer concentration is higher than the P + substrate concentration and the backside P + emitter is acceptable. It is advantageous to make it thin enough to produce current gain. A common approach used to fabricate IGBTs or MCTs is to grow N + buffers using high temperature epitaxial growth. High-temperature epitaxial growth is performed by using a thick buffer layer (
N + dopant is diffused to produce a thickness of 10 to 20 μm). Since there is a maximum allowable value for the N + buffer integrated doping concentration, the N + concentration generally needs to be lower than the P + substrate concentration to obtain the backside P + emitter current gain. Also, high temperature (1100-1200 ° C.) anneals are typically used to diffuse P-type dopants to create a deep P-type junction for field termination.
If a temperature process step is used after the formation of the N + buffer, the anneal
Diffuse N-type dopants that increase the width of the N + buffer. As the thickness of the N + buffer increases, the integrated N + buffer dopant (concentration integrated over thickness) must be low to provide sufficient gain for proper IGBT and MCT operation. The concentration decreases. High temperature field termination anneal makes it difficult to obtain an N + buffer with a higher concentration than the P + emitter concentration.

A preferred approach to achieving an N + buffer with a dopant concentration higher than the dopant concentration in the P + emitter is to use N-type ions (arsenic, phosphorus, antimony) with P +
That is, ion implantation into a substrate. Since the implanted N-type dopant concentration is higher than the P + doping concentration, the N-type dopant overcompensates the P + doping concentration and a thin N + layer can be formed on the pre-bonded surface of the substrate. N +
The buffer implant is implanted into a pre-bonded surface of another substrate. One substrate has a thickness of 100 μm to 200 μm and is provided with metal interconnects on its surface, making ion implantation annealing more difficult.

Another approach to fabricating a thin N + buffer having a higher concentration than the P + emitter is to grow the N + buffer epitaxially on the pre-bonded surface of either substrate before bonding.

If the P + substrate concentration is very high (eg, the junction from P + to N + has a very low breakdown voltage, very high leakage current, or very high concentration, the N + buffer concentration is lower than the P + concentration Is also difficult to increase), another approach is to use a lower concentration P-type epitaxial layer as shown in FIG.
+ First to grow on substrate. It may be necessary to optimize the thickness and concentration of the P-type epitaxial layer. When the P-type epitaxial layer is sufficiently thick (when it must be thicker than the diffusion distance of electrons to the P + emitter)
, The doping concentration of the P-type epitaxial layer determines the effective emitter concentration that determines the injection efficiency. In this case, the P-type epitaxial layer must be several tens of microns thick and have a doping concentration of about 1 × 10 ¹⁷ cm ⁻³ . The diffusion distance of the electrons to the P-type emitter is determined by the recombination time of the electrons in the P-type emitter. Low P
For a type emitter concentration, a relatively low N + buffer concentration must meet the criterion that the N + buffer concentration is higher than the P + emitter concentration. The N + buffer ion implantation is performed on the epitaxially grown P-type layer, or the N + epitaxial layer is grown on the P-type epitaxial layer. This allows direct bonding of the two substrates.

As mentioned above, another way to obtain a negative temperature coefficient for current gain is to use SiG
An e-strained N + buffer layer is epitaxially grown on the pre-bonded surface of each substrate. Thin epitaxial layers of SiGe or high N-type dopants are an important advantage for high performance IGBTs and MCTs. For example, thin heavily doped layers are used in IGBT N + buffers to achieve short turn-off times and a negative temperature coefficient for current gain.

In particular, the layer of SiGe acts as an N + buffer layer for IGBT or MCT. The IGBT has a fast turn-off time because the N + buffer layer is thin. A properly designed SiGe base-emitter heterojunction has a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage. This property provides short circuit protection and aids in preventing heat dissipation. If a first substrate is used as the N + emitter, the device is processed such that a P + buffer is fabricated on the second substrate.

To obtain a positive temperature coefficient for the IGBT and / or MCT, there are several approaches other than bonding that achieve a higher N + buffer concentration than the P + emitter. The first approach is the ultra-thinning method, and an important requirement for obtaining an N + buffer concentration higher than the P + emitter concentration is to minimize the temperature steps after forming the N + buffer. Preferred production methods are: MOS necessary to realize IGBT or MCT on the surface of semiconductor substrate
Perform the processing steps required to form a FET current controller. One preferred approach completes all process steps, including metal interconnect steps prior to thinning, dielectric deposition steps, and photolithography steps.

2. The substrate is thinned to about 100 μm from the back surface.

[0076] 3. P + emitters are formed on the backside of the thinned substrate by implanting a large amount of boron ions at a peak implantation depth of about 100 nm.

[0077] 4. By implanting phosphorus ions to a depth of about 500 nm, a high concentration N + buffer is formed on the back surface of the substrate.

[0078] 5. Anneal to activate boron and phosphorus implanted dopants. If metal is present on the surface, the maximum anneal temperature is about 450-550 ° C. using a conventional furnace anneal process. Temperatures between 450 and 550 ° C. activate only some of the boron and phosphorus implanted dopants.

The technique of almost completely activating implanted boron and phosphorus ions, even when metal interconnects are present on the surface, uses repetitive short pulses of excimer laser irradiation. Another technique for achieving a higher concentration of the N + buffer than the P + emitter on the backside of the thinned substrate is to epitaxially grow the N + buffer and the P + emitter on the backside at a temperature of about 500 ° C. If a barrier metal is present below the aluminum interconnect, a growth temperature of 500 ° C. is acceptable. Molecular beam epitaxy (MBE) growth techniques include metal organic chemical vapor deposition (MOCVD) and ultra-high vacuum chemical vapor deposition (UHVCVD). N + amorphous silicon layer and P
+ An amorphous silicon layer may be deposited and the single crystal layer in the layer may be regrown at about 500 ° C using a solid phase epitaxial regrowth method. Another technique for forming a P + emitter on the backside is to use a P + polysilicon layer. This type of emitter can include a thin native oxide between the polysilicon layer and the single crystal layer, which can increase the current gain, and in some cases, the current gain is a function of temperature. Hardly changes.

A high anneal temperature is used to activate the dopants implanted on the backside if metal interconnects are not present on the front side in Step 1 (where the substrate is processed just before metal deposition) ). In this case, the substrate is thinned, boron and phosphorus are implanted on the backside, and an anneal at 800-900 ° C. is used to activate the implanted dopant. In order to complete the process of fabricating an IGBT, it is necessary to perform process and photolithography steps on the surface. A difficult aspect of this process is that the wafer is now about 100 μm thick. In general, it is necessary to temporarily attach the wafer to the support wafer during the remaining process steps and remove the support wafer at the end of the process step or just before the metal sintering step. Alternatively, the thinned IGBT or MCT substrate may be permanently bonded or soldered to a metal substrate and the remaining processing steps may be performed.

A technique for fabricating a fairly narrow N + buffer layer is to implant an N + buffer into the pre-bonded surface with a low N-type dopant concentration, anneal the implanted dopant, and
+ Direct bonding to the emitter substrate. N + buffer dopants may be implanted into the P + substrate to overcompensate the P + dopant concentration. N-type substrate is about 10
Diffusion and process steps to make the IGBT or MCT thinned to 0 μm are then performed. The highest temperature step is a 1100-1200 ° C. anneal that diffuses boron to form a deep junction to the field termination. This hot step diffuses the N + buffer, which in turn increases the thickness of the N + buffer. With proper design and annealing temperature steps, IGBTs or MOSFETs with N + buffer concentrations higher than P + emitter concentrations can be fabricated.

One approach to obtaining a higher N + buffer concentration than the P + buffer concentration is to add a rather thick (10 μm) P-type epitaxial layer to a dopant concentration of about 1 × 10 ¹⁷ cm ⁻³ , as shown in FIG. Growing on a P + substrate using concentration. The low-concentration N-type substrate with the N + buffer implanted on the previously bonded surface is directly bonded to the P-type epitaxial surface. The effective dopant concentration for P-type emitter implantation efficiency is the P-type epitaxial layer dopant concentration, not the P + substrate dopant concentration.

Still another approach to obtaining an N + buffer concentration higher than the P + buffer concentration is to add a rather thick (10 μm-20 μm) P-type epitaxial layer to about 1 × 10 ¹⁷ cm ⁻ , as shown in FIG. Growth on a P + substrate using a dopant concentration of ³ . This epitaxial growth is followed by an N + buffer epitaxial growth and a final N base layer epitaxial growth. Since epitaxial growth is a very high temperature process, it is difficult to obtain a thin N + buffer, and thus it is difficult to achieve the condition that the N + buffer concentration is higher than the P + emitter concentration. The effective dopant concentration for P-type emitter implantation efficiency is not the P + substrate dopant concentration, but the P-type epitaxial layer dopant concentration.

Another aspect of the invention relates to lifetime killing that is laterally localized near the direct bonding interface of the IGBT and MCT. It is advantageous to localize the lifetime killing implant 175 laterally and longitudinally, as shown schematically in the apparatus 170 of FIG. The device 170 is formed from an upper substrate 172 bonded to a lower substrate 171 at an interface 173 shown schematically. Lower substrate 171 has, for example, N + doped portion 176 and N doped portion 177. In this example, a photolithography step (or metal mesh) is used to determine high energy protons (or lifetime killing implants, defect generation techniques, or transition metal diffusion) and is laterally confined to a region. . Regions of the power device with lifetime killing typically have a high forward voltage because a large number of injected carriers recombine in the lifetime killing region rather than moving from the anode to the cathode. By laterally limiting the implanted lifetime killing, this portion of the device is ordered in a low (or ideal) order, as it provides an area of the device 170 that does not recombine while carriers move from anode to cathode. It has a directional voltage.

The minority carriers in the base layer are typically removed from the base layer by diffusing to the emitter-base junction or by diffusing to the recombination center. The lifetime killing implant 175 is laterally defined and minority carriers in the base diffuse laterally to the short lifetime recombination region. About 10
Since a μm thick resist can be photo-defined to a feature size of about 3 μm, the lifetime killing region is buried about 10 μm from the pre-bonded interface and has a diameter of 2 to 10 μm laterally spaced by about 10 μm. Includes a grid of 3 μm circular lifetime killing regions 175 (2 to 3 μm wide parallel lines at 10 μm intervals are optional). The effective distance over which minority carriers must move in the lateral direction for recombining is about 5 μm. Because of this short distance, the recombination time is short. Therefore, when the lifetime killing is limited in the lateral direction, most of the injected PN junction area does not have the lifetime killing, a substantially ideal turn-off time is realized, and the minority carriers are recombined in the lateral direction. As a result, a fast turn-off time is also realized.

Most of helium ion implantation damage in silicon is 400 to 600 ° C.
Is not annealed during the annealing in the temperature range. Therefore, the implantation lifetime killing damage remains until after the low-temperature bonding annealing.

The technique for limiting the lifetime killing in the lateral direction has the same advantages as a non-junction type device such as a PN diode. Since diodes preferably have a low forward voltage, it is desirable that most diode areas do not include lifetime killing. It is also desirable to achieve a fast turn-off time. Since the majority of the charge stored in the diode is near the PN junction, a laterally limited lifetime killing region (possibly driven by a high energy helium implant) is preferably Approximately 4μm to 8μ into the mold base
m. A lifetime killing region spaced apart by about 10 μm in the lateral direction has almost no lifetime killing in its area, but the carrier is diffused laterally by about 5 μm so that carriers recombine in the lateral direction. By realizing a fast turn-off time. The laterally limited lifetime killing has the same effect as a thin film IGBT where the P + emitter anode is formed on the back side of the IGBT or MCT device structure on the cathode side.

In the case of IGBTs and MCTs, it is desirable that lifetime killing exists near or within the N + buffer. A common approach to fabricating punch-through IGBTs is to epitaxially grow an N + buffer and N- berth layer on a P + substrate. Diffusion of IGBT or MCT near the cathode and MOSF
Processing steps for the ET controller are performed. For high temperature epitaxial layer growth (typically above 1000 ° C.), lifetime killing such as proton or HE implantation or transition metal diffusion is typically performed after epitaxial growth. Although there are several types of ion implantation killing techniques, they do not remain as minority carrier recombination centers after high temperature epitaxial growth. An important requirement of these lifetime killing techniques is that ion implantation causes defects on the surface on which the epitaxial layer is grown so that a good quality epitaxial layer can be grown. One technique is that the energy is sufficient to be buried about 0.5 μm below the surface and that the He gas expands when the substrate is heated, creating bubbles below the silicon surface. He ions are implanted in an appropriate amount (1 × 10 ¹⁶ cm ⁻³ ). These bubbles remain until after the epitaxial layer growth. The silicon side wall of the bubble acts as a transition metal deposition center and a minority carrier resynthesis center. An approach for laterally localizing lifetime killing uses a photolithographically defined resist masking layer, so that the He implant defines a grid of circular lifetime killing regions of 2-3 μm diameter. It is possible to do. The lifetime killing region is buried about 0.5 μm below the surface on which the epitaxial layer is grown, and is laterally spaced apart by about 10 to 20 μm. Parallel lines of 2-3 μm width are optionally separated by 10-20 μm. The process for forming and growing the epitaxial layer and lateral lifetime killing is as follows. 1. An epitaxial layer including an N + buffer having a thickness of about 10 μm and an N base layer having a thickness of 10 μm is grown on a P + substrate. 2. Perform a photolithography step that defines an area for the laterally localized He implant. 3. He implantation is performed. 4. Heat to generate bubbles in silicon. 5. Grow the remaining N-based epitaxial layers.

Alternatively, another process includes the following steps. 1. grow a 20 μm N-based epitaxial layer, cover implanted arsenic for N + buffer, perform photolithography step for He implant,
Perform the implant, heat, and grow the remaining N-based epitaxial layer. 2. Other ion implantation lifetime killing nuclei that can be used in the same manner as the He implantation described above are as follows. a) Oxygen implant to produce oxygen precipitates embedded below the silicon surface and acting as recombination centers. Annealing to produce oxygen precipitates typically involves a long anneal at 650 ° C. to nucleate the precipitate and a 950 to grow the precipitate.
C. anneals and, in some cases, 1100 C. anneals to grow stacking faults. The ion implantation dose typically required to produce a high density of oxygen is typically less than about 1 × 10 ¹⁵ cm ⁻³ and does not roughen the surface as in the case of He implants that create bubbles. . b) Carbon implants that produce carbon deposition on the underside of the substrate. c) Ge implants that create lateral regions of unadapted dislocations embedded below the surface on which the epitaxial layer is grown. d) In some cases, a localized killing region other than the lateral direction of the lifetime killing epitaxially grown in advance is desirable.

The following description is based on 1) an N + buffer near the P-type body on the anode side of the device, 2) a positive temperature coefficient for forward voltage for double-sided power devices, and 3) polishing before bonding. Relating to the use of silicon-on-insulator (SOI) substrates to form thin anode-side and cathode-side devices that are not needed, and 4) another approach to achieving electrochemical etching to form thin power device layers I do.

Many power switching applications require only forward blocking operation and do not require reverse blocking operation. In this case, the active device structure and the electric field termination are:
While a high breakdown voltage is required on the cathode side of the device, only a low breakdown voltage device is required on the anode side of the device. In this case, often to achieve a higher breakdown voltage for a given overall thickness of the device, since the majority of the hole charge stored in the N base is in or near the N + buffer, and It is desirable to place an N + buffer near the P-type emitter on the anode side of the device to achieve the negative temperature coefficient for the current gain described above.

The principle method of realizing an N + buffer in the two-sided device is to perform direct bonding after the substrate is processed. There are several suitable methods for implementing a power switching device manufactured using conventional double-sided semiconductor processing.

[0093] Epitaxial growth is used on the anode-side substrate before the anode-side active device is fabricated. In this approach, an epitaxial layer having an N- base layer 182, an N + buffer layer 181, and finally a lower doped N layer is grown on a floating zone N-type substrate 183, as shown in FIG. . In some cases, two doping concentration buffers are desirable for robustness. Two doping buffers include epitaxial growth of a wide low doping N-type buffer and a thin N + buffer. The N + buffer layer is generally provided at a position of 2 μm to 20 μm from the upper surface. MOSF installed on the anode side of the device
The ET current controller can be fabricated in a P-type body 185 as shown. The P-body forms the emitter of a PNP-type bipolar transistor consisting of a P-type body emitter, an N + buffer / N-type base and a P-type collector on the cathode side of the device.

The direct bonding method used to manufacture the double-sided power device including the N + buffer described above, as shown in FIG.
μm to 200 μm thin, polishing and cleaning the substrate, hydrogen termination of the substrate,
It is directly bonded to the thinned and polished cathode substrate 190. The direct bond method is
The N-type substrate concentration of the anode-side substrate 180 has the desired concentration of the lower concentration N-type buffer of the two-step N-type buffer, thereby forming the above-described two-step N-buffer. The double-sided power device near the anode-side current controller is manufactured by the above-described epitaxial growth, but a double-sided semiconductor process may be used instead of the direct wafer bonding technique.

A high energy implant of phosphorus is used to form the N + buffer region 181 ′ of the substrate 180 ′ as shown in FIG. The other parts of the substrate 180 'are the same as the parts shown in FIGS. 20 and 21, and will not be described further.

A positive temperature coefficient for the forward voltage of a double-sided power device is obtained by providing a higher N + buffer concentration than a P-type body emitter concentration, as described above. In this case, it is generally desirable to provide the N + buffer layer 210 next to or near the P-type body 202, as shown in the anode-side substrate 200 in FIG. FIG.
At 5, the anode-side substrate 200 thus formed is directly bonded to the illustrated cathode-side substrate 210.

Another approach to implementing an N + buffer is to use silicon-on-insulator (SOI) technology. In this approach, the N + buffer 21
The ion implantation is performed on one surface of the anode-side substrate 220 as shown in the upper part of FIG. Thereafter, the substrate 220 is placed on SO 2 as shown in the lower part of FIG.
In order to form the I-substrate 225, it is bonded to a silicon substrate 227 provided with an oxide film 226 on the surface. Next, the active device portion of the anode-side substrate 220 is fabricated as shown in the upper part of FIG. Prior to direct bonding to form a double-sided power device, the silicon substrate and SOI layer protect the front side of the wafer, grind the interior of the oxide to 50 μm, chemically etch the silicon, and stop etching at the oxide. Finally, the oxide film is removed by chemical etching. An advantage of an SOI substrate is that the surface roughness is made sufficiently small, so that a polishing operation is not required. As shown in FIG. 27, the pre-fabricated anode-side substrate 220 can be directly bonded to the pre-fabricated cathode-side substrate 230. The ion-implanted N + buffer is formed in a pre-bonded surface of a pre-fabricated ultra-thin anode-side substrate. In the approach of forming an N + buffer layer near the P body of the anode substrate, the N + implant is performed on one of the pre-bonded surfaces of either the anode substrate or the cathode substrate. The anode side substrate is about 3 μm in order to form an N + buffer near the P body.
It is generally desirable for the thickness to be between 20 and 20 μm. The ultra-thin anode side substrate is
Grinding, polishing, hydrogen ion implantation layer splitting, and electrochemical etch stop and polishing can be implemented by the SOI approach just described.

As described above, the thin anode-side substrate is formed by epitaxially growing an N-type base layer, an N + buffer, and an N-type base layer on a P-type substrate to form an anode-side active device. In the case of an electrochemical etch stop approach, typically
The P-type substrate is etched by etch stopping in the PN junction depletion layer. Thus, an active substrate is formed. What is generally needed is that the substrate be polished to obtain a sufficiently small surface roughness so that it can be directly bonded to the cathode-side substrate. Electrochemical etch stop technology requires a method of making electrical contacts on the front of the device that protects the front of the wafer. A potential approach uses a conductive polymer to perform both functions.

Another SOI approach to making a thin substrate with direct bonding to form a double-sided power supply is to fabricate one or both sides of a double-sided power supply in the upper silicon layer of the SOI substrate, remove the substrate and oxide, Two prefabricated substrates are directly bonded to form a device. The main advantage of this approach is that there is no need to polish the pre-bonded surface before direct bonding. The SOI approach of directly bonding a double-sided power device is effective regardless of whether an N + buffer is included or not, even when only a single-sided IGBT or MCT device is formed. In forming an SOI substrate, a typical process is to directly bond an oxidized surface with a small surface roughness (<1 nm) and advance the surface finish of the silicon wafer to the silicon handle substrate. Therefore, the surface roughness of the silicon surface adjacent to the buried oxide film is small. An approach using an SOI substrate to form a double-sided power device is to polish the top silicon layer to a desired thickness, typically in the range of about 3 to 100 μm, to fabricate a power switching device on the top silicon layer. Then, the silicon handle substrate is removed, the oxide film is removed, and the potentially pre-bonded surface is ion implanted, and the two prefabricated substrates are directly bonded to form a double-sided power switching device. This process is more clearly illustrated with reference to FIGS. In FIG. 28, the anode-side substrate 230 is made of SOI
29, the anode-side substrate 230 is joined to the cathode-side substrate 250 after the SOI substrate is removed in FIG.

As will be readily appreciated by those skilled in the art, it is also desirable to bond more than two substrates. For example, some high voltage power devices require a silicon substrate thickness of 2 mm. This silicon substrate is a considerably thick substrate, and has a thickness of 0.5 mm.
The upper and lower substrates are formed by bonding two substrates together and have been pre-treated before bonding according to the present invention.

One embodiment of the semiconductor device is a laterally extended semiconductor base, a buffer adjacent to the base and having a first conductivity type dopant, and adjacent to the buffer and opposite the base;
A laterally extending emitter having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration higher than the second conductivity type dopant concentration of the adjacent emitter section to provide a negative temperature coefficient for the device current gain and a positive temperature coefficient for the forward voltage. Has a concentration. The buffer is silicon or germanium. The low temperature bonded interface is between the emitter and the buffer or between the buffer and the base. Another embodiment of the device includes a laterally extended localized lifetime killing portion between the first and second laterally doped oppositely doped portions. The localized lifetime killing portion includes a plurality of laterally-limited, laterally spaced lifetime killing regions. Another device includes one or more PN junctions.

[Brief description of the drawings]

FIG. 1 is a flowchart of a semiconductor device manufacturing method according to the present invention.

FIG. 2 is a cross-sectional view of a substrate processed according to the present invention.

FIG. 3 is a cross-sectional view of a substrate processed according to the present invention.

FIG. 4 is a cross-sectional view of a substrate processed according to the present invention.

FIG. 5 is a cross-sectional view of a substrate processed according to the present invention.

FIG. 6 shows an IGBT manufactured using the steps shown in FIGS.
FIG.

FIG. 7 is a graph showing the resistance characteristics of an NN hydrophobic bonded wafer as a function of annealing temperature.

FIG. 8 is a graph showing the relationship between the resistance and the reciprocal of the die area for an NN hydrophobic bonded wafer annealed at 400 ° C., and the expected resistance value is indicated by a solid line.

FIG. 9 is a graph showing the relationship between the resistance and the reciprocal of the die area for a PP hydrophobic bonded wafer annealed at 400 ° C., and the expected resistance value is indicated by a solid line.

FIG. 10 is a graph of forward and reverse current-voltage characteristics for 20 diodes manufactured from hydrophobic junction P-type and N-type silicon wafers.

FIG. 11 is a graph showing the relationship between diode ideal characteristics and forward bias as a function of the diode area of a hydrophobic junction PN junction.

FIG. 12 shows the bond strength of a hydrophobic bonded wafer annealed at 400 ° C. as a function of annealing time, with the dotted line indicating 800 ergs / cm ² required for sawing and processing, and the solid line as A + Blog (x 4 is a graph showing a least-mean-square fit to ().

FIG. 13 is a cross-sectional view of a bonding PN junction region between two substrates according to the present invention.

FIG. 14 is a cross-sectional view of a PN junction pair of a direct bond interface used to form a vertical JFET that switches conduction of current through the bond interface.

FIG. 15 is a cross-sectional view of a direct bonded IGBT including a thin N + SiGe layer according to the present invention.

FIG. 16 is a cross-sectional view of a direct bonded IGBT including an ultra-thin ion implanted or epitaxially grown N + buffer layer according to the present invention.

FIG. 17 is a graph showing a relationship between a doping concentration and a distance in the vicinity of an N + buffer layer and a P-type anode of an IGBT or MCT according to the present invention.

FIG. 18 is a graph showing the relationship between doping concentration and distance near an N + buffer layer and a P-type emitter anode further including a P-type epitaxial layer grown on a P-substrate according to the present invention.

FIG. 19 is a cross-sectional view of a bond interface region showing a localized recombination region according to the present invention.

FIG. 20 is a cross-sectional view of an anode-side substrate including an N + buffer epitaxial layer according to the present invention.

FIG. 21 is a cross-sectional view of the anode-side substrate as shown in FIG. 20 that has been further processed and joined to the cathode-side substrate.

FIG. 22 is a cross-sectional view of an anode side substrate illustrating a high energy implant to form an N + buffer layer according to the present invention.

FIG. 23 is a cross-sectional view of the anode-side substrate as shown in FIG. 22 that has been further processed and joined to the cathode-side substrate.

FIG. 24 is a cross-sectional view of an anode-side substrate including an N + buffer layer near a P body diffusion according to the present invention.

FIG. 25 is a cross-sectional view of the anode-side substrate as shown in FIG. 24 that has been further processed and joined to the cathode-side substrate.

FIG. 26 is a sectional view of an anode-side substrate bonded to an SOI substrate according to the present invention.

FIG. 27 is a cross-sectional view of the anode-side substrate as shown in FIG. 26 joined to the cathode-side substrate.

FIG. 28 is a cross-sectional view of an anode-side substrate including an N + buffer layer and a base floating zone mounted on an SOI substrate according to the present invention.

FIG. 29 is a cross-sectional view of the anode-side substrate as shown in FIG. 28 that has been further processed and joined to the cathode-side substrate.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] March 9, 2000 (200.3.9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

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[Claims]

[Claims]

A first portion extending laterally with 45. A first conductive type dopant, is on the first portion, a second portion extending laterally of the first conductivity type dopant, the A third laterally extending portion having a second conductivity type dopant overlying the second portion , a first active control device on an outer surface of the first portion, and an outer surface of the third portion; and a second active control unit in said one of the first portion and the second portion has a remote high dopant concentration by the dopant concentration in the third portion, the semiconductor device.

[Procedure amendment]

[Submission date] January 9, 2001 (2001.1.9)

[Procedure amendment 1]

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──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 658K 29/80 658H 29/80 V (31) Priority claim number 09/036 , 815 (32) Priority date March 9, 1998 (1998.3.9) (33) Priority country United States (US) (81) Designated country EP (AT, BE, CH, CY, DE, DK) (ES), ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), JP, KR (72) Inventor Temple, Victor Keith 12065 Clifton Park, New York, USA Main Street 962 (72) Inventor Neilson, John Manning Savage United States of America Pennsylvania 19403 Norista 2620 (72) Hobart, Carl Inventor Maryland, USA 20772 Upper Marlboro Croom Road 8610 F-term (reference) 5F005 AA02 AA03 AB02 AB03 AC02 AD01 AE09 AF01 AF02 AG02 AH02 AH04 GA01 5F102 GB04 GC07 GD04 GD10 GJ02 GJ03 GJ10 GK02 GQ01 HC01 HC07 HC21

Claims (178)

[Claims] A laterally extending semiconductor base extending laterally; a laterally extending buffer adjacent to the base and having a dopant of a first conductivity type; a laterally extending buffer adjacent to the buffer and opposite the base; A laterally extending emitter having a type dopant, wherein the buffer is relatively thin to provide a negative temperature coefficient for the current gain of the device and a positive temperature coefficient for the forward voltage of the device. A semiconductor device having a first conductivity type dopant concentration higher than a two conductivity type dopant concentration. 2. The semiconductor device according to claim 1, wherein said base has a first conductivity type dopant concentration lower than said first conductivity type dopant concentration of said buffer. 3. The buffer of claim 1, wherein said buffer has a thickness of less than about 10 microns.
13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said buffer has a thickness in a range of about 200 to 500 nanometers. 5. The semiconductor device according to claim 1, wherein the dopant concentration of the buffer is higher than about 3 × 10 ¹⁶ cm ⁻³ . 6. The semiconductor device according to claim 1, wherein the dopant concentration of the buffer is higher than about 1 × 10 ¹⁷ cm ⁻³ . 7. The semiconductor device according to claim 1, wherein at least one of said base and said emitter contains silicon. 8. The semiconductor device according to claim 7, wherein said buffer contains silicon. 9. The semiconductor device according to claim 7, wherein said buffer contains germanium. 10. The semiconductor device according to claim 1, further comprising a bonded interface bonded between said emitter and said buffer. 11. The semiconductor device according to claim 10, wherein said bonded interface contains substantially no oxide. 12. The semiconductor device according to claim 1, further comprising a bonded interface bonded between said buffer and said base. 13. The semiconductor device according to claim 12, wherein said bonded interface contains substantially no oxide. 14. The semiconductor device according to claim 1, wherein said emitter includes an epitaxial portion adjacent to said buffer and a second portion opposite said epitaxial portion. 15. The semiconductor device according to claim 1, further comprising means for controlling a current flow to and from the base. 16. The means for controlling a current flow comprises at least one MOS transistor.
16. The semiconductor device according to claim 15, comprising a FET current control device. 17. A laterally extending semiconductor base, a laterally extending buffer having a first conductivity type dopant adjacent to the base, and a second conductivity type dopant adjacent to the buffer and opposite the base. A laterally extending emitter having a bonded interface extending laterally between the base and the buffer, and between one of the buffer and the emitter. A semiconductor device having a first conductive type dopant concentration that is substantially thinner than a second conductive type dopant concentration of an adjacent emitter portion, and wherein the laterally extending bonded interface is substantially free of oxide. 18. The semiconductor device according to claim 17, wherein said base has a first conductivity type dopant concentration lower than said first conductivity type dopant concentration of said buffer. 19. The semiconductor device according to claim 17, wherein the buffer has a dopant concentration higher than about 1 × 10 ¹⁷ cm ⁻³ . 20. The semiconductor device according to claim 17, wherein at least one of said base and said emitter contains silicon. 21. The semiconductor device according to claim 20, wherein said buffer contains silicon. 22. The semiconductor device according to claim 20, wherein said buffer contains germanium. 23. The semiconductor device according to claim 17, further comprising means for controlling a current flow into and out of said base. 24. The means for controlling the current flow comprises at least one MOS
24. The semiconductor device according to claim 23, comprising a FET current control device. 25. A laterally extending laterally extending semiconductor base containing silicon, a laterally extending buffer adjacent to the base and having a first conductivity type dopant and containing germanium, and adjacent to the buffer and adjacent to the base. A laterally extending emitter having a second conductivity type dopant and containing silicon, and a laterally extending emitter between the base and the buffer, and between the buffer and the emitter. A laterally extending bonded interface, wherein the laterally extending bonded interface is substantially free of oxide, and wherein the buffer has a negative temperature coefficient for device current gain and a positive for forward voltage. Semiconductor device that is relatively thin in order to provide a temperature coefficient of 26. The semiconductor device according to claim 25, wherein the base has a first conductivity type dopant concentration lower than the first conductivity type dopant concentration of the buffer. 27. The semiconductor device according to claim 25, wherein said buffer has a thickness of less than about 10 microns. 28. The semiconductor device according to claim 25, wherein said buffer has a thickness in a range of about 200 to 500 nanometers. 29. The semiconductor device according to claim 25, further comprising a bonded interface bonded between said emitter and said buffer, wherein said bonded interface is substantially free of oxide. 30. The semiconductor device according to claim 25, further comprising means for controlling a current flow into and out of said base. 31. The means for controlling the current flow comprises at least one MOS
31. The semiconductor device according to claim 30, including a FET current control device. 32. A laterally extending first portion having a first conductivity type dopant; a laterally extending second portion having a second conductivity type dopant overlying the first portion; A localized lifetime killing portion extending laterally between the first portion and the second portion, wherein the localized lifetime killing portion is laterally confined and laterally spaced apart; A semiconductor device having a plurality of lifetime killing regions. 33. The semiconductor device of claim 32, wherein a bonded bonded interface is defined between said localized lifetime killing portion and said first portion. 34. The semiconductor device according to claim 33, wherein the lifetime killing region is vertically separated from the bonded interface by a predetermined distance. 35. The semiconductor device according to claim 34, wherein said predetermined distance is about 10 microns. 36. The semiconductor device according to claim 33, wherein the bonded interface contains substantially no oxide. 37. The semiconductor device according to claim 32, wherein a bonded bonded interface is defined between the localized lifetime killing portion and the second portion. 38. The semiconductor device according to claim 37, wherein the lifetime killing region is vertically separated from the bonded interface by a predetermined distance. 39. The semiconductor device according to claim 38, wherein said predetermined distance is about 10 microns. 40. The semiconductor device according to claim 37, wherein the bonded interface contains substantially no oxide. 41. The semiconductor device according to claim 32, wherein each of the lifetime killing regions includes at least one of a defect and an implanted impurity. 42. Each of said lifetime killing regions has a diameter of about 2 to 2
33. The semiconductor device of claim 32, having a 0 micron circular area, wherein adjacent circular areas are separated by about 5 to 20 microns. 43. The method of claim 32, wherein each of the lifetime killing regions has a band that is about 2 to 20 microns in width, and adjacent bands are spaced about 5 to 20 microns apart. Semiconductor device. 44. The semiconductor device according to claim 32, further comprising means for controlling a current flow to and from the base. 45. The means for controlling the current flow comprises at least one MOS
The semiconductor device according to claim 44, further comprising an FET current control device. 46. A laterally extending first portion having a first conductivity type dopant; a laterally extending second portion having a second conductivity type dopant overlying the first portion; At least one doped region of the second conductivity type formed in the first portion adjacent to the interface between the first portion and the second portion and defining at least one PN junction; and the at least one doped region And the second portion, and the P
A conductive layer that reduces the resistance of the N junction. 47. The semiconductor device according to claim 46, wherein said at least one doped region includes a pair of spaced apart doped regions and is a vertical junction field effect transistor. 48. The semiconductor device according to claim 46, wherein the conductive layers are arranged in a lattice and are magnetically permeable base transistors. 49. The semiconductor device according to claim 46, wherein said conductive layer contains at least one of a metal and silicon. 50. The semiconductor device according to claim 46, wherein at least one of said first portion and said second portion contains silicon. 51. The semiconductor device according to claim 46, further comprising a bonded interface bonded between said first portion and said second portion. 52. The semiconductor device according to claim 51, wherein the bonded interface contains substantially no oxide. 53. The semiconductor device according to claim 46, further comprising means for controlling a current flow to and from the base. 54. The means for controlling the current flow comprises at least one MOS
54. The semiconductor device according to claim 53, comprising a FET current control device. 55. A laterally extending first portion having a first conductivity type dopant, a laterally extending second portion having a first conductivity type dopant overlying the first portion, and A laterally extending third portion overlying the second portion and having a second conductivity type dopant; a first active control device on an outer surface of the first portion; and an outer surface of the third portion. A second active control device according to claim 1, wherein one of said first portion and said second portion has a dopant concentration higher than a dopant concentration of said third portion. 56. The semiconductor device according to claim 55, further comprising a bonded interface bonded between said second portion and said third portion. 57. The semiconductor device according to claim 56, wherein the bonded interface contains substantially no oxide. 58. The first active control device and the second active control device,
The semiconductor device according to claim 55, further comprising a first MOSFET current controller and a second MOSFET current controller. 59. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: treating at least one surface of at least one substrate; thinning at least one substrate; Bonding the processed substrate and the thinned substrate together such that the processed surface defines an outer surface of the semiconductor device, and adversely affects the at least one processed surface. Annealing the bonded integral substrate at a relatively low annealing temperature. 60. The method of claim 59, wherein said thinning removes a surface portion of at least one substrate opposite the treated surface. 61. The method of claim 59, wherein the step of thinning comprises thinning to a thickness of less than about 200 μm. 62. The method of claim 59, further comprising polishing the thinned surface to a predetermined surface roughness. 63. Before the step of thinning the at least one substrate,
60. The method of claim 59, further comprising forming a gettering layer, wherein the thinning removes the gettering layer. 64. The method of claim 63, wherein said step of forming a gettering layer performs at least one of phosphorus diffusion, argon or carbon implantation, and polysilicon deposition. 65. The method of claim 63, wherein said step of forming a gettering layer forms said gettering layer before said processing step. 66. The method of claim 59, further comprising, prior to the bonding step, forming a implanted region on a surface of the at least one substrate opposite the processed substrate. 67. The method of claim 66, wherein the step of forming the implant region comprises implanting using a lifetime kill implant. 68. The method of claim 67, wherein said step of forming an implant includes implanting in a predetermined pattern to define a plurality of laterally spaced lifetime killing implants. 69. The lifetime killing implant comprises proton, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron, and
68. The method of claim 67, comprising at least one of nickel. 70. The method of claim 59, further comprising, prior to the bonding step, forming a doped layer on a surface of the at least one substrate opposite the processed substrate. 71. The method of claim 70, wherein forming the doped layer comprises implanting a dopant into the substrate. 72. The method according to claim 72, wherein the at least one substrate has a first conductivity type dopant, and the step of implanting the dopant includes a higher concentration of the second conductivity type dopant than the first conductivity type dopant in the substrate. 71. The method of claim 70, wherein said doped layer is implanted.
The described method. 73. The method of claim 71, further comprising the step of activating said implanted dopant. 74. The method of claim 72, wherein the step of forming a doped layer forms an epitaxially doped layer. 75. The method of claim 59, further comprising, before the bonding step, forming an epitaxial layer on a surface of the at least one substrate opposite the processed substrate. 76. The method of claim 75, wherein said at least one substrate comprises silicon and said epitaxial layer comprises germanium. 77. The method of claim 59, wherein said processing comprises forming a highly doped buffer layer of a first conductivity type on the doped substrate of the first conductivity type. 78. The method of claim 59, wherein said processing comprises implanting a highly doped buffer layer of a first conductivity type into a doped substrate of the first conductivity type. 79. The method of claim 59, wherein said bonding is performed in a vacuum. 80. The method according to claim 59, further comprising, before the step of thinning, mounting at least one substrate to be thinned on a handling substrate.
The described method. 81. The method of claim 59, further comprising, prior to said bonding, aligning said substrate. 82. The step of aligning includes defining a predetermined corresponding portion on each substrate; cutting the substrate along the predetermined portion to define a cutting edge; Aligning the substrate along an edge.
The described method. 83. The method of claim 81, further comprising: testing individual devices on each substrate; and aligning the substrates to increase semiconductor device yield. 84. The method of claim 59, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 85. The method of claim 59, wherein said treating forms an aluminum layer. 86. The method of claim 85, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C. to 550 ° C. 87. The processing step further comprises forming at least one doped region, and after the annealing step, forming at least one metal layer, wherein the annealing temperature is less than about 800 ° C. 60. The method of claim 59. 88. The method according to claim 59, wherein said annealing temperature is about 400 ° C. or higher. 89. The method of claim 59, wherein said annealing step anneals for a predetermined time. 90. The method of claim 59, wherein said substrate comprises silicon and further comprising hydrogen terminating the silicon surface prior to said bonding step. 91. The method of claim 59, further comprising the step of cleaning the surface to be bonded to remove hydrocarbons and / or metals. 92. The method of claim 59, wherein said processing steps form at least one MOSFET controller. 93. The method of claim 59, wherein said plurality of substrates is two, and wherein said processing step processes both substrates. 94. The method of claim 59, wherein said bonding comprises bonding at a predetermined temperature, a predetermined environment, and a predetermined pressure. 95. The method of claim 59, wherein said annealing step comprises annealing at a predetermined environment and a predetermined pressure. 96. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: forming a gettering layer on at least one substrate; and processing at least one surface of the semiconductor device. A method comprising: thinning at least one substrate; and annealing the bonded one-piece substrate at a relatively low annealing temperature so as not to adversely affect the at least one treated surface. 97. The step of forming a gettering layer comprises performing at least one of phosphorus diffusion, ion implantation of argon, silicon, oxygen, or carbon, and polysilicon deposition. the method of. 98. The processing step forms a metal layer, wherein the annealing temperature is lower than a temperature related to a property of the metal layer.
The described method. 99. The processing step forms a metal layer, wherein the annealing temperature is lower than a temperature related to properties of the metal layer.
The described method. 100. The method of claim 96, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 101. The method of claim 100, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C. to 550 ° C. 102. The step of forming further comprises forming at least one doped region, forming at least one metal layer after the annealing, wherein the annealing temperature is less than about 800 ° C. 97. The method of claim 96. 103. The method according to claim 96, wherein said annealing temperature is about 400 ° C. or higher. 104. The method of claim 96, wherein said processing step completely processes said at least one substrate to form all active devices and interconnects. 105. The step of processing comprises at least one MOSFET
60. The method of claim 59, forming a controller. 106. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: processing at least one surface of at least one substrate; and at least one substrate opposite the processed surface. Implanting the processed substrate; and bonding the processed substrate together such that the at least one processed surface defines an outer surface of the semiconductor device; and the at least one processed surface. Annealing the bonded integral substrate at a relatively low annealing temperature so as not to adversely affect the implanted area. 107. The method of claim 106, further comprising, prior to said bonding, thinning said at least one substrate. 108. The method of claim 106, wherein said driving step includes driving with a lifetime killing drive. 109. The method of claim 108, wherein said driving step includes driving in a predetermined pattern to define a plurality of laterally spaced lifetime killing driving regions. 110. The lifetime killing implant includes at least one of proton, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron, and nickel. the method of. 111. The method of claim 106, wherein said implanting comprises implanting a dopant into said substrate. 112. The at least one substrate has a first conductivity type dopant, and the step of implanting the dopant includes a higher concentration of the second conductivity type dopant in the substrate than the first conductivity type dopant. 12. The implant of claim 11, wherein said doped layer is implanted.
The method of claim 1. 113. The processing step forms a metal layer, and wherein the annealing temperature is lower than a temperature related to properties of the metal layer.
6. The method according to 6. 114. The method of claim 106, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 115. The method of claim 114, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C to 550 ° C. 116. The method of claim 106, wherein said processing steps form at least one doped region, and further comprise forming at least one metal layer after the annealing has been performed at less than about 800 ° C. . 117. The anneal temperature is about 400 ° C. or higher.
The described method. 118. The method of claim 106, wherein said processing step completely processes said at least one substrate to form all active devices and interconnects. 119. The method according to claim 119, wherein the processing includes at least one MOSFET.
107. The method of claim 106, forming a controller. 120. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: processing at least one surface of at least one substrate; and at least one substrate opposite the processed surface. Forming an epitaxial layer on the surface of the semiconductor device, bonding the at least one processed surface to define an outer surface of the semiconductor device, and not adversely affecting the at least one processed surface. Annealing the bonded integral substrate at a relatively low annealing temperature. 121. The method of claim 119, further comprising, prior to said bonding step, thinning said at least one substrate. 122. The step of forming an epitaxial layer includes forming an epitaxially doped layer to define a relatively thin buffer layer.
19. The method according to item 19. 123. The step of forming said epitaxially doped layer comprises:
122. The method of claim 121, wherein forming an epitaxially doped layer having a higher dopant concentration than an adjacent substrate portion. 124. The method of claim 120, wherein said at least one substrate comprises silicon and said epitaxial layer comprises germanium. 125. The processing step forms a metal layer, wherein the annealing temperature is lower than a temperature related to properties of the metal layer.
0. The method of claim 0. 126. The method of claim 120, wherein said processing step forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 127. The method of claim 126, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C to 550 ° C. 128. The processing step further comprises forming at least one metal layer after forming at least a doped region and annealing, wherein the annealing temperature is less than about 800 ° C. 120. The method of claim 120. 129. The anneal temperature is about 400 ° C. or higher.
The described method. 130. The method of claim 120, wherein said processing completely processes said at least one substrate to form all active devices and interconnects. 131. The step of processing comprises at least one MOSFET
121. The method of claim 120, forming a controller. 132. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: treating at least one surface of at least one substrate; defining a plurality of laterally spaced lifetime kill implant regions. Implanting, in a predetermined pattern, a region of at least one substrate opposite the treated surface; and wherein the at least one treated surface defines an outer surface of the semiconductor device. Bonding the treated substrate together; and relatively annealing the bonded integral substrate so as not to adversely affect the at least one treated surface and the implanted area. Annealing at a temperature. 133. The method of claim 132, further comprising, prior to said bonding, thinning said at least one substrate. 134. The lifetime killing implant includes at least one of proton, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron, and nickel. the method of. 135. The processing step forms a metal layer, and wherein the annealing temperature is lower than a temperature related to properties of the metal layer.
2. The method according to 2. 136. The method of claim 132, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 137. The method of claim 136, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C to 550 ° C. 138. The step of processing further comprises forming at least one doped region, forming at least one metal layer after the annealing step, wherein the annealing temperature is less than about 800 ° C. 133. The method of claim 132. 139. The anneal temperature is about 400 ° C. or higher.
The described method. 140. The method of claim 132, wherein said processing completely processes said at least one substrate to form all active devices and interconnects. 141. The step of processing comprises at least one MOSFET
133. The method of claim 132, forming a controller. 142. A method for manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: processing at least one surface of at least one substrate; wherein the at least one processed surface is an outer surface of the semiconductor device. Bonding the treated substrate so as to define the step of: annealing the bonded integral substrate at a relatively low annealing temperature so as not to adversely affect the at least one treated surface. And a method comprising: 143. The processing step forms a metal layer, wherein the annealing temperature is lower than a temperature related to a property of the metal layer.
2. The method according to 2. 144. The method of claim 142, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 145. The method of claim 144, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C to 550 ° C. 146. The method of claim 142, wherein said processing steps form at least a doped region, and wherein said annealing temperature is less than about 900 ° C. 147. The method of claim 146, further comprising forming at least one metal layer after said annealing step. 148. The method of claim 142, wherein said treating forms at least a doped region, and wherein said annealing temperature is less than about 800 ° C. 149. The method according to claim 148, further comprising forming at least one metal layer after said annealing step. 150. The method of claim 142, further comprising the step of cutting said semiconductor device after said annealing step, wherein said annealing temperature is sufficient to provide a predetermined surface energy allowing cutting. Method. 151. The annealing temperature is at least about 400 ° C., and the predetermined surface energy is at least about 800 ergs / cmμ.
50. The method of claim 50. 152. The method of claim 142, wherein said annealing step anneals for a predetermined amount of time. 153. The method of claim 142, wherein said processing step completely processes said at least one substrate to form all active devices and interconnects. 154. The method of claim 142, wherein said substrate contains silicon, and further comprising the step of hydrogen terminating the silicon surface prior to said bonding step. 155. The method of claim 142, further comprising cleaning the surface to be bonded to remove at least one of a hydrocarbon and a metal. 156. The step of processing comprises at least one MOSFET
142. The method of claim 142, forming a controller. 157. The method of claim 142, wherein said plurality of substrates is two, and said processing comprises processing both substrates. 158. A method of manufacturing a semiconductor device from a plurality of silicon substrates, comprising: processing at least one surface of at least one silicon substrate; and at least one processed surface is an outer surface of the semiconductor device. Bonding the treated silicon substrate and the hydrogen-terminated surface together, and annealing the bonded integrated silicon substrate at an annealing temperature of less than about 800 ° C. to define How to have. 159. The method of claim 158, further comprising the step of hydrogen terminating the silicon surface to be bonded together. 160. The method as recited in claim 15, wherein said annealing temperature is about 400 ° C. or higher.
8. The method according to 8. 161. The method of claim 158, wherein said processing step completely processes said at least one silicon substrate to form all active devices and interconnects. 162. The method according to claim 158, further comprising the step of removing at least one of the hydrocarbon and the metal from the surface to be bonded. 163. The step of processing comprises at least one MOSFET
159. The method according to claim 158, wherein the method forms a controller. 164. The method of claim 158, wherein said plurality of substrates is two, and said processing comprises processing both substrates. 165. A method of manufacturing a semiconductor device from a plurality of silicon substrates, comprising: treating at least one surface of at least one silicon substrate; and bonding to remove at least one of a hydrocarbon and a metal. Cleaning the surface of the semiconductor device and bonding the processed silicon substrate and the cleaned silicon substrate together such that at least one of the processed surfaces defines an outer surface of the semiconductor device; Annealing the bonded unitary silicon substrate at a relatively low annealing temperature of less than about 800 ° C. 166. The anneal temperature of about 400 ° C or higher.
5. The method according to 5. 167. The method of claim 165, wherein said processing step completely processes said at least one silicon substrate to form all active devices and interconnects. 168. The processing step comprises at least one MOSFET
166. The method according to claim 165, wherein the control is formed. 169. The method of claim 165, wherein said plurality of substrates is two, and wherein said processing step processes both substrates. 170. A method of manufacturing a semiconductor device from a plurality of semiconductor substrates, comprising: processing at least one surface of at least one substrate to form a metal layer; and at least one processed surface. Bonding the processed substrate together so as to define an outer surface of the semiconductor device; and bonding the bonded integrated substrate to a relatively low temperature lower than a temperature related to a property of the metal layer. Annealing at an annealing temperature. 171. The method of claim 170, wherein said annealing temperature is a temperature related to at least one of a melting point of said metal layer and a reaction temperature of said metal and said substrate. 172. The method of claim 170, wherein said treating forms an aluminum layer, and wherein said annealing temperature is less than about 450 ° C. 173. The method of claim 172, further comprising forming a barrier metal between the aluminum and the substrate, wherein the anneal temperature ranges from about 450 ° C to 550 ° C. 174. The method of claim 170, wherein said processing step completely processes said at least one substrate to form all active devices and interconnects. 175. The method of claim 170, wherein said processing step completely processes said at least one substrate to form all active devices and interconnects. 176. The method of claim 170, wherein said substrate comprises silicon, and further comprising the step of hydrogen terminating the silicon surface prior to said bonding step. 177. The step of processing comprises at least one MOSFET
170. The method of claim 170, forming a controller. 178. The method of claim 170, wherein said plurality of substrates is two, and said processing comprises processing both substrates.