JPH027467A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control a thickness of a semiconductor layer simply and with high accuracy including a thick part and a thin part by a method wherein a second semiconductor substrate is pasted onto an insulating layer on the surface of a first semiconductor substrate, the first semiconductor substrate and a first compound layer for stopper use are removed and a circuit element is formed on the exposed semiconductor surface. CONSTITUTION:A first silicon oxide layer 3 for stopper use is formed at a depth of 1.5mum from the side of a surface 2 of a first semiconductor substrate 1; a second silicon oxide layer 5 for stopper use is formed selectively at a depth of 1.0mum. A part on the side of the surface 2 of the silicon oxide layer 5 is removed. Then, a silicon oxide layer 7 is formed; an SOG layer 8 is formed on the surface of the silicon oxide layer 7. Then, a second semiconductor substrate 9 is pasted onto the surface of the SOG layer 8 of the first semiconductor substrate 1; the first semiconductor substrate 1 is etched from the rear side; the first silicon oxide layer 3 for stopper use is exposed. After that, the silicon oxide layer 3 is removed; a semiconductor layer 6 is exposed; a thick part is used as a bipolar region and a thin part is used as a CMOS region.

Description

[Detailed description of the invention] The present invention will be described in accordance with the following sequence.

A. Industrial field of application B1 Overview of the invention C1 Technical background "Figure 2" D5 Problems to be solved by the invention E1 Means for solving the problems F5 Effects G. Examples [Figure 1] H1 Effects of the Invention (A. Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a Sol structure in which the thickness of a semiconductor layer on which a circuit element is formed is made different.

(B. Summary of the Invention) The present invention provides the method for manufacturing a semiconductor device described above, in which oxygen, etc. A compound layer such as a silicon oxide layer for the first stopper is formed by ion implantation, and a silicon oxide layer or the like for the second stopper is selectively implanted by ion implantation of oxygen or the like into a shallower area than the compound layer for the stopper. After forming a compound layer and removing the semiconductor on the surface side of the compound layer, an insulating layer is formed on the surface of the first semiconductor substrate so that the surface is flat, and a second semiconductor is formed on the insulating layer-J2. The substrates are bonded together, the first semiconductor substrate is removed from the back side, the first stopper compound layer is removed to expose the semiconductor, and a circuit element is formed on the exposed semiconductor surface. be.

(C, Technical Background) [Fig. 2] Semiconductor devices in which different types of circuit elements such as bipolar transistors and CMO3) transistors are formed on a Sol substrate are becoming increasingly necessary. by the way,
When forming a bipolar transistor, the thickness of the semiconductor layer needs to be, for example, about 1 to 2 μm, but in the case of a CMOS transistor, it is sufficient to have a thickness of about 0.1 to 0.5 μm, so it is not necessary to make the semiconductor layer thicker than necessary. If it is thick, the characteristics of Sol cannot be effectively utilized and it becomes difficult to create an ultra-high performance CMO3 circuit.

Therefore, as shown in FIG. 2, 5io2
It is conceivable to make the thickness of the semiconductor layer C formed via 11Qb smaller in the bipolar region than the CMO3 region.

However, in the case shown in FIG. 2, a step d occurs on the surface of the semiconductor layer C due to the difference in the thickness of the core layer C. This level difference d is not desirable because it has a negative effect on the formation of wiring and the like. Specifically, wire breakage and the like are more likely to occur.

Therefore, there has arisen a need to be able to form a semiconductor layer C having a flat surface and having a thickness that varies depending on the location. The technology that attempted to meet this need was published in Japanese Patent Application Laid-Open No. 57-1
It is introduced in Publication No. 30448. This technology forms a U-shaped etching groove on the surface of a silicon semiconductor substrate, forms an insulating layer slightly deeper than the surface of the semiconductor substrate, and then epitaxially grows a semiconductor layer on the surface of the semiconductor substrate. The surface of the semiconductor layer formed by polishing is polished to make it flat, and the thickness of the semiconductor layer becomes thicker where the U-shaped groove is formed.
The thickness of the semiconductor layer becomes thinner in areas where no grooves are formed.

(D. Problems to be Solved by the Invention) By the way, the technique described in the above-mentioned Japanese Patent Application Laid-open No. 130448/1983 had the following problems.

First, there is the problem that it is difficult to control the depth of the U-shaped groove. This is because, in this technology, the depth of the U-shaped groove determines the difference in thickness between the thick and thin parts of the semiconductor layer, and this variation directly determines the variation in the thickness of the semiconductor layer. Therefore, the depth of the U-shaped groove must be controlled with high precision to form higher performance circuit elements. However, since no stopper is provided for this etching, it is very difficult to control the etching depth, and there is a possibility that variations of several μm may occur.

Further, after a semiconductor layer is formed by epitaxial growth, the semiconductor layer is polished to flatten the surface, but there is no stopper for this polishing. Therefore, there is a problem in that the thickness of the semi-quadruple layer varies depending on whether the thickness is set thick or thin depending on the variation in the thickness to be polished.

The present invention has been made in view of the above circumstances, and includes a method for manufacturing a semiconductor device in which the thickness of the semiconductor layer on which the circuit element f is formed is varied so that the surface of the semiconductor layer is flat. At the same time, it is an object of the present invention to enable the thickness of each of the thin and thick portions of the semiconductor layer to be controlled with high precision.

(E. Means for Solving the Problems) In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device of the present invention implants ions of oxygen or the like into a region deeper than the surface of the first semiconductor substrate. Form a compound layer such as a silicon oxide layer for a second stopper, selectively form a compound layer such as a silicon oxide layer for a second stopper at a shallower depth than the compound layer for a second stopper by implanting ions such as oxygen, and form a compound layer such as a silicon oxide layer for a second stopper. After removing the semiconductor on the surface side, an insulating layer is formed on the surface of the first semiconductor substrate so that the surface is flat, a second semiconductor substrate is bonded on the insulating layer, and the first semiconductor substrate is The first stopper compound layer is removed from the back side, and the semiconductor is exposed by removing the first stopper compound layer, and a circuit element is formed on the exposed surface of the t-conductor.

(F. Effect) According to the method for manufacturing a semiconductor device of the present invention, the depth of the first stopper compound layer of the first semiconductor substrate determines the thickness of the J-shaped portion of the semiconductor layer, and the depth of the first stopper compound layer of the first semiconductor substrate determines the thickness of the J-shaped portion of the semiconductor layer. The depth of the second stopper compound layer formed therein determines the thickness of the thin part of the semiconductor layer, and the depth of the compound layer can be controlled with high precision by changing the energy during ion implantation. . Therefore, the thickness of the semiconductor layer can be controlled with high precision in both thick and thin areas. Of course, this first stopper compound layer serves as a stopper when removing from the first semiconductor substrate side by polishing or etching, and the second stopper compound layer also acts as a stopper when removing from the first semiconductor substrate side by polishing or etching. It acts as a stopper in etching, and there is no risk of polishing or etching having too few or too many flea marks.The interface between the first stopper compound layer and the first semiconductor substrate is on the surface of the semiconductor layer on which circuit elements are formed. Therefore, unless the first semiconductor substrate is selected to have an uneven surface, the surface of the semiconductor layer can be made flat.

(G. Embodiment) [FIG. 1] Hereinafter, a method for manufacturing a semiconductor device of the present invention will be explained in detail according to the illustrated embodiment.

FIGS. 1A to 1H are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.

(A) First, as shown in the same figure (A), a first semiconductor substrate l made of non-crystalline silicon Si is prepared, and oxygen 0 is introduced from the surface 2 side of the first semiconductor substrate 1 from the surface 2 side. For example, ions are implanted at a depth of 1.5 μm to form a silicon oxide layer 5iOx (first stopper silicon oxide layer) 3.
form. This ion implantation is performed using channeling so that a silicon oxide layer S i Ox3 is formed at a desired depth using energy.

(B) Next, as shown in the same figure (B), a photoresist film 4 is selectively formed on the surface 2 of the first semiconductor substrate 1,
Using the stiffness as a mask, oxygen 0 is ion-implanted from the surface 2 side of the first semiconductor substrate 1 to a depth of, for example, 1.0 μm, thereby selectively forming a second stopper silicon oxide layer 5iOx5. do. Specifically, C
A silicon oxide layer Si, 9x5 is formed in the MOS region, and no silicon oxide layer 5iOx5 is formed in the bipolar region. In other words, the bipolar region is masked with photoresists 1 and 4, and zero oxygen ions are implanted. Of course, this ion implantation requires lower implantation energy than the ion implantation shown in FIG. 1(A).

(C) Next, as shown in FIG. 1(C), the silicon oxide layer of the first conductor substrate 1 is etched by etching the surface of the first semiconductor substrate 1 using the photoresist film 4 as a mask. Remove the portion corresponding to the surface 2 side of 5. This etching has a thickness of about 1.0 μm, but it is preferable to perform RIE to a thickness of about 0.8 μm, and then perform solution etching using KOH. I mean,
This is because the silicon oxide layer 5 has very strong corrosion resistance against KOH, so it functions very effectively as a stopper and can prevent the risk of excessive etching.

(D) Next, the photoresist 1 and 4 are removed, and then the surface of the semiconductor layer 6 (semiconductor portion above the silicon oxide layer 3) is heated and oxidized to form silicon oxide as shown in FIG. 1(D). A layer (Sin2) 7 is formed. This thermal oxidation changes the silicon oxide layer 5 from the Siox layer to the Si
02 layer 7. This thermal oxidation is performed in order to prevent the silicon oxide layer (SiO2) 7 from penetrating the semiconductor layer 6 with undesirable impurities in the 5OGWA formed in the subsequent step.

(E) Next, as shown in FIG. 1(E), a 500 layer 8 is formed on the surface of the silicon oxide layer 7. The 300 layer 8 is formed in order to obtain an insulating layer whose surface is flat even though the underlying surface is uneven.

(F) Next, as shown in FIG. 1(F), the second semiconductor substrate 9 is bonded to the surface of the 500 layer 8 of the first semiconductor substrate 1. Reference numerals 10 and 11 denote silicon oxide layers on both main surfaces of the second semiconductor substrate 9.

(G) Next, as shown in FIG. 1(G), the first semiconductor substrate 1 is polished from the back side and etched with KOH to expose the first silicon oxide layer 3 for a stopper. Since the silicon oxide layer 3 has significantly greater hardness than silicon Si and is highly resistant to corrosion by KOH, it functions effectively as a stopper against polishing and etching by KOH.

(H) Thereafter, as shown in FIG. 1(H), the stopper silicon oxide layer 3 is removed by etching, and the semiconductor layer 6 is removed by etching.
expose. This semiconductor layer 6 has a γ-flat surface 12 and partially differs in thickness, with thicker areas serving as bipolar regions and thinner areas serving as CMOS regions.

According to this semiconductor device manufacturing method, a first stopper silicon oxide layer formed by ion-implanting oxygen 0 deep from the surface 2 of the first semiconductor substrate 1; 1 becomes the surface of the semiconductor layer 6 on which circuit elements are formed, and the surface of the semiconductor layer 6 can be made flat.

The thicknesses of the thick and thin portions of the semiconductor layer 6 are determined by adjusting the energy of the ion implantation for forming the first silicon oxide layer 3 for a stopper and the ion implantation for forming the second silicon oxide layer 5 for a stopper. Can be controlled with high precision. The second silicon oxide layer 5 for a stopper is etched using OH in the step shown in FIG. 1(C), and the first silicon oxide layer 3 is etched during the polishing shown in FIG. 1(G). Since it functions as a strong stopper, it is possible to prevent excessive or insufficient etching or polishing.

Note that nitrogen N ions may be used instead of oxygen O as the ions to be implanted, and the silicon nitride layer may be formed as a stopper.

(Effects of the H1 invention) As described above, the method for manufacturing a semiconductor device of the present invention is as follows:
A first compound layer for a stopper is formed in a place deeper than the surface of the first semiconductor substrate, a second compound layer for a stopper is selectively formed in a place shallower than the compound layer by ion implantation, and the second compound layer for a stopper is formed in a place shallower than the compound layer. After removing a portion of the substrate corresponding to the surface side of the silicon oxide layer, an insulating layer is formed on the surface of the first semiconductor substrate so that the surface is flat, and a second semiconductor substrate is attached on the insulating layer. In addition, the first semiconductor substrate is removed from the back side, and the first stopper compound layer is further removed to expose the semiconductor.

Therefore, according to the method for manufacturing a semiconductor device of the present invention, a circuit element is formed at the interface between the first stopper compound layer formed by ion implantation from the surface of the first semiconductor substrate and the first semiconductor substrate. The surface of the semiconductor layer can be easily made flat unless a substrate with an uneven surface is selected as the first semiconductor substrate.

Then, the depth from the surface of the first semiconductor substrate of the first stopper compound layer of the first semiconductor substrate and the compound layer selectively formed in a shallower area is the thickness of the semiconductor layer.
The depth of the two compound layers can be controlled with high precision by ion implantation. Moreover, the compound layer functions effectively as a stopper during etching due to its corrosion resistance against the substrate etching solution, and during polishing due to its significantly greater hardness than that of the semiconductor substrate. Therefore, the thickness of the semiconductor layer including thick and thin parts can be easily and precisely controlled.

[Brief explanation of the drawing]

FIGS. 1A to 1H are cross-sectional views illustrating two embodiments of the method for manufacturing a semiconductor device of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing the technical background of the invention. Explanation of symbols 1: first semiconductor substrate, surface of first semiconductor substrate, first stopper compound layer, mask, second stopper compound layer, semiconductor layer, 8... insulating layer, first 2 semiconductor substrate. C)

Claims (1)

[Claims] (1) A step of implanting ions that react with the substrate to form a compound from the surface of the first semiconductor substrate to form a first stopper compound layer deeper than the surface; A second compound layer is selectively formed deeper than the surface and shallower than the first stopper compound layer by selectively masking and implanting ions that react with the substrate to form a compound from the surface. a step of removing a portion of the first semiconductor substrate on the surface side of the second compound layer; a step of forming an insulating layer having a flat surface on the surface of the first semiconductor substrate; a step of fixing a second semiconductor substrate to the surface of the layer; removing the first semiconductor substrate from the back side up to the second stopper compound layer; and further removing the stopper compound layer to expose the semiconductor. A method for manufacturing a semiconductor device, comprising the steps of: