GB2309826A - A method of fabricating a SOI substrate - Google Patents

A method of fabricating a SOI substrate Download PDF

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Publication number
GB2309826A
GB2309826A GB9626980A GB9626980A GB2309826A GB 2309826 A GB2309826 A GB 2309826A GB 9626980 A GB9626980 A GB 9626980A GB 9626980 A GB9626980 A GB 9626980A GB 2309826 A GB2309826 A GB 2309826A
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United Kingdom
Prior art keywords
substrate
device substrate
isolation film
forming
layer
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Granted
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GB9626980A
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GB2309826B (en
GB9626980D0 (en
Inventor
Jae Kap Kim
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of GB9626980D0 publication Critical patent/GB9626980D0/en
Publication of GB2309826A publication Critical patent/GB2309826A/en
Application granted granted Critical
Publication of GB2309826B publication Critical patent/GB2309826B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Description

2309826 METHOD OF FABRICATING SILICON-ON-INSULATOR SUBSTRATE
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a si licon-oninsulator PSOI") substrate, and more particularly to a method of fabricating a SOI substrate including a Si device layer having a constant thickness.
In general, in a fabrication process of a complementary metal oxide semiconductor PCNOSER) transistor, an isolation region of a large area is needed required in order to isolate devices and prevent latch-up of a CMOS transistor. There are, however, problems in that an isolation region of a large area results in a reduced chip dimension and reduced integration of devices.
A SOI technique had been proposed in order to above problems. With complete isolation between devices, a SOI substrate, having a buried insulating layer sandwiched between a Si handling substrate and a Si device substrate, prevents latch- up of a CMOS transistor and allows for high operational speed of devices.
one of fabrication methods of the SOI substrate is a separation by implanted oxygen (11SIMOX'1) method that implants oxygen ions within a Si substrate. The SIMOX method, however, has a disadvantage in that dislocation in a surface of a Si layer easily occurs when implanting 1 oxygen ions, thereby generating a great quantity of leakage current. Therefore, it is difficult to control thickness of the Si layer where a device is to be formed.
Another available method of fabrication is a bond and etch-back siliconon- insulator (11BES0III) technique wherein a Si device substrate is bonded to a Si handling substrate where an insulating layer is formed at either substrate, and the Si device substrate is then back-etched to form a Si device layer.
Referring to FIG.1A, there are provided a Si device substrate 1 and a handlinr substrate 2 where a buried insulating layer 3 is formed. The buried insulating layer may be formed by oxidation on either the device substrate 1 or the handling substrate 2.
is Referring to FIG.1B, the handling substrate 2 and the device substrate 1 are fusion-bonded, with the buried oxide film 3 existing between substrates 1 and 2. Next, most of the device substrate 1 is etched to a predetermined thickness by grinding and lapping process and is then chemical and mechanical polished to a degree of high precision, thereby forming a Si device layer IA. Referring to FIG.1C, an isolation film 4 is formed in the Si device layer IA to define an active region, thereby forming a SOI substrate 100.
However, in said chemical and mechanical polishing process for forming the Si device layer 1A, since it is difficult to precisely control a polishing stop point, the 2 is thickness of the Si device layer 1A is not constant. Therefore, yield of semi-conductor devices is reduced.
In order to solve above problem, an alternative BESOI method of fabricating a SOI substrate has been provided.
Referring to FIG.2A, there are a Si device substrate 11 and Si handling substrate 12. On the Si device substrate 11, etching stopper 14 doped with high impurity ions and a silicon device layer 15 are grown respectively by epitaxial deposition. on the handling substrate 12, a buried insulating layer 13 is formed.
Referring to FIG.2B, thh device substrate 11 is bonded to the handling substrate 12 and then etched to a thickness of 20-5Ogm by a grinding and lapping. The remaining device substrate 11 and the etching stopper 14 are removed by a selective chemical and mechanical polishing method to form a Si device layer 15 having a constant thickness. Referring to FIG.2C, a field oxide 16 is formed at the Si device layer 15 to define an active region, thereby forming a SOI substrate 200.
Accordingly, the conventional BESCI technique can form a Si device layer 15 having a constant thickness to improve yield. But, it has a disadvantage in that a separate additional process is required for forming the etching stopper 14 and the Si device layer 15.
SUMMY OF THE INV=ON 3 An object of the present invention is to provide a method, of fabricating a SOI substrate, which forms a Si device layer having a constant thickness.
Another object of the present invention is to provide a method, of fabricating a SOI substrate, which improves yield by forming a Si device layer having a constant thickness without an additional process. - In accordance with one embodiment, there is provided a method of fabricating a SOI substrate, comprising the steps of: providing a Si device substrate and a handling substrate; forming an isolation film in the Si device substrate; forming a first buried oxide film on the Si device substrate including the isolation film; forming a second oxide film on the handling substrate, respectively; bonding the Si device substrate and the handling substrate to contact surfaces of the buried oxide films; and etching the device substrate to form a Si device layer having a constant thickness.
In one embodiment, the step for forming the isolation film includes the step for: forming a pad oxide and silicon nitride layer, respectively, on the Si device substrate; patterning the pad oxide and silicon nitride layer to expose a portion of the Si device substrate where the isolation film is to be formed; oxidizing the exposed portion of the Si device substrate to form a field oxide as the isolation film; and removing the pad oxide an silicon nitride.
4 In another embodiment, the step for forming the isolation film includes the step for: forming a photoresist pattern on the device substrate to expose the portion of the device substrate where the isolation film is formed; etching the exposed portion of the device substrate to a predetermined thickness to form trenches; removing the photoresist pattern; forming an oxide film sufficient to fill in the trenches over the device substrate; and etching back the oxide film to form the isolation film in trenches.
In one embodiment, the Si device layer is formed by grinding, lapping, and then chemical and mechanical polishing the device substrate until the isolation film is exposed.
In another embodiment, the Si device layer is formed 15 by grinding, lapping, and then etching back the device substrate until the isolation film is exposed.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and feature of the invention may be better understood with reference to the following detailed description, appended claims, and attached drawings wherein:
FIG.1A through FIG.1C are sectional views illustrating a process of fabricating a SOI substrate according to a conventional BESOI technique; FIG.2A through FIG.2C are sectional views illustrating a process of fabricating a SOI substrate according to an alternative conventional BESOI technique; FIG. 3A through FIG. 3D are sectional views illustrating a process of fabricating a SOI substrate in accordance with one embodiment of the present invention; and FIG.4A through FIG.4C are sectional views illustrating a process of fabricating a SOI substrate in accordance with another embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION a
Referring to FIG. 3A, in accordance with one embodiment of the present invention, there are provided a Si device substrate 20 and a handling substrate 25. On the Si device 15 substrate 20, a pad oxide 21 and a silicon nitride layer 22 are formed respectively and then are patterned to expose a portion of the device substrate 20 where an isolation film is to be formed.
Referring to FIG.3B, a field oxide 23, as the isolation region, is formed at the exposed portion of the device substrate 20 by a thermal oxidation and the pad oxide 21 and the silicon nitride layer 22 are then removed. Herein, the thickness Ild', of the field oxide 23, that is the oxidation depth of the Si device substrate, is same thickness of a Si device layer and is preferably 0.1-0.Sgm.
Referring to FIG.3C, buried oxide films 24A and 24B are formed to a predetermined thickness on the device 6 substrate 20 and the handling substrate 25, respectively. The buried oxide films 24A and 24B may both be also formed just one of either substrate. At this time, the buried oxide 24A formed on the device substrate 20 has a topology as a result of the field oxide 23. Therefore, the buried oxide 24A is chemical and mechanical polished to remove the topology, thereby obtaining an even planar surface.
Referring to FIG.3D, the device substrate 20 and the handling substrate 25 are bonded to contact the surface of the buried oxide film 24A and the surface of the buried oxide film 24B. The devich substrate 20 is etched to a predetermined thickness by grinding and lapping and is then chemical and mechanical polished until the surface of the field oxide 23 is exposed thereby using the field oxide 23 is as an etching stopper. A Si device layer 20A is thus formed.
According to one embodiment, without a separate process for forming an etching stopper, the Si layer 20A is formed by an etching process using the field oxide 23 as a etching stopper. Therefore a SOI substrate 300 i S fabricated having: the handling substrate 25; an insulating layer 24 consisting of the buried oxide films 24A and 24B; and the Si layer 20A having a constant thickness without an additional process.
Referring to FIG.4A, in accordance with another embodiment of the present invention, there are provided a Si device substrate 30 and a handling substrate 35. A 7 photoresist pattern (not shown) is formed on the device substrate 30 exposing a portion of the device substrate 30 where a trench T is to be formed.
Next, by an anisotropic etching method, the exposed portion of the device substrate 30 is etched to a predetermined depth to form the trench T wherein an isolation film is to be formed. The depth of the trench is preferably 0.1-0.Sgm. In addition, the depth of the trench T later determines the thickness of a Si device layer where a device is to be formed.
After the formation of'the trench T, the photoresist pattern is removed. A oxide film 31 is formed over the device substrate 30 at a thickness sufficient to fill in the trenches T.
Referring to FIG.4B, the oxide film 31 is etched back until the surface of the device substrate 30 is exposed to form an isolation film 31B located in the trenches T. By a thermal oxidation, buried oxide films 32A and 32B are formed over the device substrate 30 including the isolation film 31B and the handling substrate 35, respectively.
Referring to FIG.4C, the device substrate 30 and the handling substrate 35 are bonded by a conventional bonding method contacting the surfaces of the buried oxide films 32A and 32B. Then, the device substrate 30 is etched to a predetermined thickness by grinding and lamming and is then chemical and mechanical polished to expose the surface of the isolation film 31B, thereby forming a Si device layer 8 30A. Therefore, a SOI substrate 400 includes: the handling substrate 35; an insulating layer 32 including the buried oxide films 32A and 32B; the Si layer 30A having a constant thickness; and the isolation film 31B.
According to the embodiments, although the Si device layer is formed having a constant thickness and an even surface by grinding and lapping and then chemical and mechanical polishing a device substrate, it may be formed by grinding, lapping and then etching back the device substrate.
According to the preseht invention, an isolation film is formed on the device substrate before the bonding process and the device substrate is etched by using the isolation film as an etching stopper. Accordingly, a Si device layer having a constant thickness is formed without an additional process for forming an etching stopper, thereby improving yield of semiconductor devices.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as falling within the true scope of the invention.
is 9

Claims (12)

What is claimed is
1. A method of fabricating a silicon-on-insulator substrate, comprising the steps of:
providing a Si device substrate and a handling substrate; forming an isolation film in said Si device substrate; forming a first buried oxide film on said Si device substrate including said isolation film; forming a second buried oxide film on said handling substrate; 1 banding said Si device substrate and said handling substrate to contact surfaces of said first and second buried oxide films; and etching said device substrate to form a Si device layer having a constant thickness.
2. The method as claimed in claim 1, wherein said step for forming said isolation film includes the step for:
forming a pad oxide and silicon nitride layer, respectively, on said device substrate; patterning said pad oxide and silicon nitride layer to expose a portion of said device substrate where said isolation film is to be formed; oxidizing said exposed portion of said device substrate to form a field oxide as said isolation film; and removing said pad oxide and silicon nitride layer.
3. The method as claimed in claim 2, wherein said thickness of said si device layer is dependent upon an oxidation depth of said device substrate in said step for oxidizing.
4. The method as claimed in claim 3, wherein said oxidation depth of said Si device substrate is 0.1-0.Sgm.
5. The method as claimed in claim 1, wherein said step for forming said isolation film includes the step for:
forming a photoresist ptLttern on said device substrate to expose the portion of said device substrate where said isolation film is formed; etching said exposed portion of said device substrate to a predetermined depth to form trenches.
removing said photoresist pattern; forming an oxide film sufficient to fill in said trenches over said devise substrate; and etching back said oxide film to form said isolation film in trenches.
6. The method as claimed in claim 5, wherein said step for etching back said oxide film is carried out until said device substrate is exposed.
7. The method as claimed in claim 5, wherein said thickness of said Si device layer is dependent upon said 11 depth of said trench.
8. The method as claimed in claim 7, wherein said depth of said trench is 0.1-0.5pm.
9. The method as claimed in claim 1, wherein said step for forming buried oxide films is carried out by a thermal oxidation.
10. The method as claimed in claim 1, wherein said step for etching said devide substrate is carried out by using said isolation film as an etching stopper.
11. The method as claimed in claim 1, wherein said Si iS device layer is formed by grinding and lapping said Si device substrate to a predetermined thickness and then chemical and mechanical polishing said Si device substrate until said isolation film is exposed.
12. The method as claimed in claim 1, wherein said Si device layer is formed by grinding and lapping said Si device substrate to a predetermined thickness and then etching back said Si device substrate until said isolation film is exposed.
12
GB9626980A 1995-12-30 1996-12-27 Method of fabricating silicon-on-insulator substrate Expired - Lifetime GB2309826B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069452A KR970052020A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method

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GB2309826A true GB2309826A (en) 1997-08-06
GB2309826B GB2309826B (en) 2000-07-05

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JP (1) JPH1050824A (en)
KR (1) KR970052020A (en)
CN (1) CN1078737C (en)
DE (1) DE19653199A1 (en)
GB (1) GB2309826B (en)
TW (1) TW348302B (en)

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Publication number Priority date Publication date Assignee Title
KR20010056788A (en) * 1999-12-16 2001-07-04 박종섭 Method for fabricating soi substrate
CN102148183B (en) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950000106B1 (en) * 1992-01-08 1995-01-09 삼성전자 주식회사 Manufacturing method of semiconductor device
EP0753886A1 (en) * 1995-07-13 1997-01-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate

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Publication number Priority date Publication date Assignee Title
JPH0719839B2 (en) * 1989-10-18 1995-03-06 株式会社東芝 Method for manufacturing semiconductor substrate
JPH03180070A (en) * 1989-12-08 1991-08-06 Seiko Epson Corp Semiconductor device and manufacture thereof
JP2754819B2 (en) * 1989-12-28 1998-05-20 株式会社日本自動車部品総合研究所 Method for manufacturing dielectric-separated semiconductor substrate
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JP3099446B2 (en) * 1991-08-30 2000-10-16 株式会社デンソー Semiconductor substrate having dielectric isolation region

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950000106B1 (en) * 1992-01-08 1995-01-09 삼성전자 주식회사 Manufacturing method of semiconductor device
EP0753886A1 (en) * 1995-07-13 1997-01-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WPI Abstract Accession No 96-440999/44 & KR 950000106 B *

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KR970052020A (en) 1997-07-29
JPH1050824A (en) 1998-02-20
GB2309826B (en) 2000-07-05
GB9626980D0 (en) 1997-02-12
TW348302B (en) 1998-12-21
CN1162836A (en) 1997-10-22
CN1078737C (en) 2002-01-30
DE19653199A1 (en) 1997-07-03

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Expiry date: 20161226