JPH09213786A - Method of isolating element of semiconductor device, and cmos device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materilialize the isolation of a diffused layer and the isolation of a well with high integration, and also, secure the well potential easily. SOLUTION: In a CMOS device which isolates wells 11A-11D by providing trenches 10A-10D, impurity layers 8A and 8B capable of electric connection with the same conductivity type of wells 11A-11C existing on both sides of the trenches 10A and 10B separated by the trenches 10A and 10B are provided at the bottom parts of the trenches 10A and 10B. These impurity layers 8A and 8B are of the same conductivity type as those of the wells 11A-11C existing on both sides of the trenches 10A and 10B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device element isolation method and a CMOS device, and more particularly to a trench element element isolation method for forming a diffusion layer isolation and a well isolation of a semiconductor device, and a CMOS device having a trench. Is.

[0002]

As a method for element isolation of a semiconductor device, there is a trench isolation in which a trench is provided which extends vertically to a semiconductor substrate and spatially and mechanically divides the substrate region. A feature of trench isolation is that it can achieve both a narrow isolation width and high isolation characteristics, and it is an element isolation method that has attracted attention along with the recent miniaturization of patterns and high integration.

Particularly in the case of the CMOS structure, a deep trench which can be used as both the isolation of the diffusion layer of the transistor and the isolation of the well is desirable from the viewpoint of cost. Such a conventional deep trench structure is shown in the device structure diagram of FIG. That is, the CMOS device 100 has a trench, e.g.
03B separates the diffusion layers 104 and 105 on the surface, and further separates the P-type well 101 and the N-type well 102.

Here, when the well in the substrate is divided,
Since the potentials are not common, a drift or the like of the operating point occurs, which is not preferable. For this reason, conventionally, a diffusion layer for a well contact can be formed at the same time when the diffusion layer of the transistor is formed by an ordinary lithography technique. For example, in FIG. 9, the diffusion layer 106 applies a well potential to the P-type well 101, and similarly, the diffusion layer 107 applies a well potential to the N-type well 102.

However, providing such a diffusion layer for well contact on the limited device surface is not preferable in terms of integration degree. In particular, in the case of an SRAM memory cell, it is not a good idea to provide such a well contact diffusion layer for each cell because it increases the cell size.

A conventional element isolation mode will be described. First, a CMOS having a LOCOS structure as shown in FIG.
In the device 110, the diffusion layer 11 is formed by the field oxide film 111.
4, 115 are separated. In such a configuration, L
The OCOS film thickness was a depth suitable for separating the diffusion layers 114, 115 on the surface, and was not suitable for separating wells 112, 113 deeper than this. That is, the wells are connected to each other at a sufficiently deep position (lower part). With such a configuration, it is not necessary to make a well contact for each cell, and it is sufficient to make a well contact for several cells at once.

Also, the CMOS device 12 shown in FIG.
Shallow trench (shallow trench) 123 such as 0
There are also attempts to apply only to the isolation of the diffusion layers 124, 125 of the transistor. In this case, well 121,
Although the separation of 122 is performed by another method, for example, PN separation, in this case, in order to prevent latch-up and punch through between the diffusion layers via the well separation, the diffusion layers 124, 125 close to the well separation are formed. A certain forbidden distance (X, Y in FIG. 11) is required between them, which reduces the degree of integration of the device.

On the other hand, in deep trench isolation,
At the same time as separating the diffusion layer of the transistor and the separation between the well substrates (or wells of opposite conductivity type) in the same process, the depth of the trench should be the same as or deeper than the depth of the well. Will be done.
Even in the case of a deep trench, for example, it is possible to make the depth of the well sufficiently deeper than the depth of the trench and electrically short the wells under the well.
In this case, the same problem as in the case of PN separation occurs. Further, since the lower part of the well has a high concentration, there is a disadvantage that an electrical short circuit becomes insufficient.

As described above, the depth of the trench is set to be equal to or more than the depth of the well in order to enhance the isolation capability, while
There has been a demand for a structure in which a common potential between wells can be easily obtained.

The present invention has been made in order to solve the above-mentioned problems and drawbacks of the prior art, and its purpose is to realize the separation of the diffusion layer and the well separation with a high degree of integration and to easily secure the well potential. An object of the present invention is to provide a semiconductor device element isolation method and a CMOS device.

[0011]

In order to solve the above problems, an element isolation method for a semiconductor device according to the present invention is an element isolation method for a semiconductor device having a CMOS structure, in which a trench is provided to isolate at least a well. An impurity layer electrically connected to wells of the same conductivity type existing on both sides of the trench, which are separated by a trench, is provided on the bottom surface of the trench, and the impurity layer has the same conductivity type as the wells existing on both sides of the trench. Is characterized in that.

The CMOS device according to the present invention is a semiconductor device having a CMOS structure in which at least wells are isolated by providing a trench, and wells of the same conductivity type existing on both sides are electrically isolated from each other by the trench. An impurity layer connectable to the bottom surface of the trench is provided, and the impurity layer has the same conductivity type as the well.

According to the element isolation method of the semiconductor device and the CMOS device of the present invention, the deep trench structure surely isolates the well, while the impurity of the same conductivity type as the well provided in the bottom portion of the trench isolation. The layer electrically connects wells of the same conductivity type with low resistance, so that a well potential is applied to each well.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a CMOS based on an embodiment of an element isolation method for a semiconductor device according to the present invention.
It is a device structure figure of an apparatus. As shown in FIG.
The CMOS device 1 according to the present invention includes three P-type wells 11A, 11B and 11C, one N-type well 11D and four trenches 10A and 10B on an N-type silicon substrate 2.
Two trenches 10A and 10B provided with 10c and 10D
Is provided with P-type impurity layers 8A and 8B at the bottom thereof.

Further, the diffusion layers 12A-1A are provided at the interface of the substrate.
2E is formed. These diffusion layers are the source / drain of the device, and there is no diffusion layer for well contact.

The P-type wells 11A and 11B are formed in the trench 1
Completely separated by 0A. However, the P-type wells 11A and 11B are in electrical contact with the P-type impurity layer 8A at the deepest portion. On the other hand, the trench 10B
Separates the diffusion layers 12A and 12B from the P-type wells 11B and 11C, and the impurity layer 8B electrically shorts the P-type wells 11B and 11C. Similarly, the trench 10C has diffusion layers 12C and 12D.
And P-type wells 11C and 11D are separated. As described above, the impurity layer is formed in two of the four trenches and keeps the three P-type wells at the same potential.

2 to 8 are schematic views for explaining the process of the element isolation method for a semiconductor device according to the present invention.
The process based on the drawings will be described below. In FIG. 2, after an oxide film 3 having a thickness of about 10 nm is grown on an N-type silicon substrate 2, a silicon nitride (Si3N4) film 4 and a polysilicon (PolyS) which serve as a stopper for CMP in a subsequent process.
i) The film 5 is deposited by CVD to 100 nm and 50 nm, respectively.

The resist in the element isolation region is removed by a known photoresist technique, and the polysilicon film 5, the silicon nitride film 4, and the underlying silicon substrate 2 are etched by RIE (reactive ion etching) processing.
(FIG. 3) The etching depth of the underlying silicon substrate 2 depends on the depth of the well to be separated, but is 0.5 μm in this embodiment.
It is. By this RIE processing, trench holes 6A to 6D
Are formed perpendicular to the silicon substrate 2.

Next, for the purpose of stabilizing the element isolation characteristics,
The inner walls of the trench holes 6A to 6D are oxidized to, for example, 30n.
m oxide film 7 is formed (FIG. 4). Furthermore, the trench holes 6 are selectively formed only in the isolation regions of wells of the same conductivity type and of the same potential, for example, by the PR technique.
The same type of impurity (boron B in this embodiment) is ion-implanted into the bottoms of A and 6B to increase the well concentration in those portions. (Fig. 5)

Next, the bias ECR or LP (reduced pressure) T
Silicon dioxide 9 is deposited on the entire surface by EOS or the like (FIG. 5), and is polished by chemical mechanical polishing (CMP) until the underlying two-layer stopper 4 or 5 is exposed (FIG. 6). The reason why the stopper has a two-layer structure is to facilitate the end point determination. The initial deposited film thickness is 1.2
μm.

Here, the stopper layers 4 and 3 are further removed. Trench 10A-10D is formed in each trench hole (FIG. 7). Then, by a process such as doping, P-type wells 11A to 11C and N-type well 11D are formed.
Are formed (FIG. 8). P-type wells 11A to 11C, N
The depth from the interface of both the mold wells 11D is the trench 10
Almost equal to A to 10D, and trenches 10A to 10D
It is formed so that it is not deeper than.

In FIG. 8, P-type wells 11A and 11B are provided.
Focusing on the trench 10A, the P-type wells 11A and 11B are completely separated by the trench 10A. On the other hand, the impurity layer 8A is formed of the P-type wells 11A and 11A.
It is in contact with any of B. Since the impurity layer 8A is P-type and has conductivity, the P-type wells 11A and 11B are electrically short-circuited. As a result, the P-type wells 11A and 11B have the same potential.

The same applies to P-type wells 11B and 11C.
Then, the same holds for the trench 10B. That is, the P-type wells 11B and 11C are short-circuited via the impurity layer 8B. As a result, the P-type wells 11B and 11C have the same potential. As a result of the above, P-type well 1
1A, 11B and 11C all have the same potential.

Further, a P-type well 11C and an N-type well 1
Focusing on 1D and the trench 10C, the P-type well 11
The C and N-type wells 11D are completely separated by the trench 10C. On the other hand, since the trench 10C does not have an impurity layer on the bottom surface, the electrical separation ability between the P-type well 11C and the N-type well 11D on both sides is not deteriorated. In this way, the element isolation region is completed.

After completing the element isolation region as described above, ordinary PR, RIE, oxidation, CVD, ion implantation,
The CMOS device 1 as shown in FIG. 1 is completed by processes such as annealing and sputtering.

[0026]

As described above, in the semiconductor device element isolation method and the CMOS device according to the present invention, the diffusion layer isolation called the deep trench and the well isolation are simultaneously performed in the same step, and the trench is formed. Since the impurity layer provided at the lower end is configured to conduct wells separated from each other, it is not necessary to provide a diffusion layer for applying a well potential to each well, and the device can be highly integrated. The method and apparatus are particularly effective when it is difficult to make a well contact for each memory cell, such as an SRAM cell having an all CMOS structure.

[Brief description of drawings]

FIG. 1 is a device structure diagram of a CMOS device based on an embodiment of an element isolation method for a semiconductor device according to the present invention.

FIG. 2 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 3 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 4 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 5 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 6 is a schematic view illustrating a process of a device isolation method for a semiconductor device according to the present invention.

FIG. 7 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 8 is a schematic diagram illustrating a process of an element isolation method for a semiconductor device according to the present invention.

FIG. 9 is a device structure diagram of a conventional trench isolation CMOS device.

FIG. 10 is a device structure diagram of a conventional LOCOS type CMOS device.

FIG. 11 is a device structure diagram of a conventional shallow trench isolation CMOS device.

[Explanation of symbols]

 1 CMOS device 2 Substrate 8A, 8B Impurity layer 10A to 10D Trench 11A to 11D Well 12A to 12E Diffusion layer

Claims (2)

[Claims] 1. A method for isolating a semiconductor device having a CMOS structure in which at least a well is provided by providing a trench, the method being capable of being electrically connected to wells of the same conductivity type existing on both sides of the trench and separated by the trench. An impurity layer is provided on the bottom surface of the trench, and the impurity layer has the same conductivity type as the wells existing on both sides of the trench. 2. A semiconductor device having a CMOS structure in which a trench is provided to isolate at least the well, and an impurity layer electrically isolated from the trench and electrically connectable to wells of the same conductivity type existing on both sides of the trench. A CMOS device, characterized in that it is provided on the bottom surface of the well and the impurity layer has the same conductivity type as the well.