CN1162836A - Method for fabricating silicon-on-insulator substrate - Google Patents

Method for fabricating silicon-on-insulator substrate Download PDF

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Publication number
CN1162836A
CN1162836A CN96123936A CN96123936A CN1162836A CN 1162836 A CN1162836 A CN 1162836A CN 96123936 A CN96123936 A CN 96123936A CN 96123936 A CN96123936 A CN 96123936A CN 1162836 A CN1162836 A CN 1162836A
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Prior art keywords
silicon chip
silicon
film
manufacture method
soi substrate
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CN96123936A
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CN1078737C (en
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金载甲
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A method for forming a SOI substrate of a silicon device layer with a uniform thickness is disclosed, without increasing the processing steps, which can improve the percent of pass of the silicon device layer with a uniform thickness. Said method comprises following steps of forming an isolation film in the predetermined parts of the Si device substrate; forming buried oxide films on the surface of the silicon device substrate wherein an isolation film is also formed or on the handling substrate; bonding the device substrate and the handling substrate between the buried oxide films; removing the device substrate until to expose the isolation film to form the silicon device layer.

Description

The manufacture method of SOI substrate
The present invention relates to the manufacture method of SOI substrate, the manufacture method of the SOI substrate of the silicon layer that is formed uniformly element is particularly arranged on the SOI substrate.
Usually, in the transistorized manufacturing process of CMOS, separate and prevent the transistorized latch-up phenomenon of CMOS, form element and separate in order to ensure the element on large tracts of land.At this moment, increase the marker space and just reduced chip region, thereby become the factor that hinders high integrationization.
For addressing this is that, the SOI technology has been proposed.
As element separation structure completely, the interlayer SOI substrate of the embedded insulation film of predetermined thickness is set between silicon supporting substrate and device are with silicon chip, prevent the transistorized latch-up phenomenon of CMOS, realize the high speed motion of device.
One of method that forms the SOI substrate is to inject SIMOX (forming separation by the oxygen that the injects) technology of oxonium ion to silicon chip., the technology of injecting oxygen because of the ion of this SIMOX technology has following shortcoming, promptly easily misplaces on the device formation face, can not correctly regulate the thickness of formation device, thereby generation is than the gross leak electric current.
In the past, BESOI (bonding and reverse corrosion SOI) technology was arranged, promptly will have at least a slice formed two silicon chips of dielectric film bonding after, oppositely corrosion device with silicon chip, form the silicon layer of fabricate devices.
As shown in Figure 3A, in the existing BESOI technology, device silicon chip 1 and supporting substrate 2 that preparation is made up of silicon.On arbitrary relative of device, form buried insulating layer 3 by oxidation with silicon chip 1 or supporting substrate 2.
Shown in Fig. 3 B, with silicon chip 1 and supporting substrate 2, between embedding oxide-film 3, carry out melting adhered to device.
Remove most of device with after the silicon chip 1 with grinding and polishing, carry out high-precision chemistry, mechanical lapping, form silicon device layer 1A.Then, shown in Fig. 3 C, form the element separation membrane 4 of the active area that limits silicon device layer 1A, thereby form SOI substrate 100.
, as mentioned above, for forming silicon device layer 1A, when carrying out chemistry, mechanical lapping, also have following point, promptly be difficult to correctly control and grind anti-stop, silicon device layer 1A's is in uneven thickness, thereby reduces qualification rate.
Fig. 4 illustrates other BESOI method that in the past solves such problem.Shown in Fig. 4 A, for example, form the etching block film 14 be mixed with high concentration impurities, the silicon device layer 15 that forms device at device on silicon chip 11 in regular turn with epitaxial growth method.
Shown in Fig. 4 B, bonding device is used silicon chip 11 and is formed the supporting substrate 12 of buried insulating layer 13.Then, remove device substrate 11 with grinding and glossing, residual about 20～50 μ m remove residual silicon chip 11 and etching block film with chemistry, the mechanical lapping selected, form certain thickness silicon device layer 15.Shown in Fig. 4 C, form the field oxide film 16 that is limited with the source region, thereby form the SOI substrate.
Yet, though said method can improve the qualification rate that forms certain thickness silicon device layer 15, owing to adopted the technology that forms etching block film 14 and silicon device layer 15 respectively, thereby have the shortcoming that increases operation.
Therefore, main purpose of the present invention provides a kind of manufacture method that the SOI substrate of certain thickness silicon device layer is arranged.
Other purpose of the present invention does not provide and need increase additional process, just can improve the manufacture method of the SOI substrate of the qualification rate that is formed with certain thickness silicon device layer.
For achieving the above object, according to the present invention, the manufacture method of SOI substrate comprises the following steps:
Be equipped with device silicon chip and supporting substrate;
Form the element separation membrane at above-mentioned device on silicon chip;
Form the first embedding oxide-film at the device that forms the said elements separation membrane with silicon chip top;
On above-mentioned supporting substrate, form the second embedding oxide-film;
Bonding device makes the described first and second embedding oxide-film surface contacts with silicon chip and supporting substrate;
The above-mentioned device silicon chip of etching forms silicon device layer.
In addition, according to the embodiment of the invention, the step that forms the element separation membrane at above-mentioned device on the silicon chip predetermined portions comprises the following steps:
Form the photoresist figure, device is exposed with the predetermined element separated region on the silicon chip;
Corrode the above-mentioned silicon chip desired depth of exposing, form groove;
Remove above-mentioned photoresist figure;
But form the oxide-film of the thickness of filling slot on silicon chip at above-mentioned device;
Oppositely the above-mentioned oxide-film of corrosion forms the element separation membrane in groove.
In addition, by the embodiment of the invention, the above-mentioned device of grinding and polishing carries out chemistry, mechanical lapping with after the silicon chip, up to exposing the element separation membrane, forms above-mentioned silicon device.
By another embodiment of the present invention, grind, polish above-mentioned device with after the silicon chip, oppositely corrode, up to exposing the element separation membrane, form above-mentioned silicon device layer.
Figure 1A-1D is the profile of the manufacture method of one embodiment of the invention SOI substrate;
Fig. 2 A-2C is the profile by the manufacture method of the SOI substrate of another embodiment of the present invention;
Fig. 3 A-3C is the profile by the SOI substrate manufacture method of common BESOI technology;
Fig. 4 A-4C is the profile by the SOI substrate manufacture method of other method.
Below, present invention will be described in detail with reference to the accompanying most preferred embodiment.
Referring to Figure 1A, fabricate devices is with silicon chip 20 and supporting substrate 25, at device stacked in regular turn liner oxide film 21 and silicon nitride film 22 on the silicon chip 20.Make liner oxide film 21 and silicon nitride film 22 compositions, expose the predetermined element isolated area of device with silicon chip 20.
Referring to Figure 1B, use thermal oxidation, with forming field oxide film 23 on the silicon chip 20, remove liner oxide film 21 and silicon nitride film 22 at the device that exposes.Wherein, device with silicon chip 20 on the degree of depth of oxidation be about 0.1～0.5m.
Referring to Fig. 1 C,, wherein, also can only use and form embedding oxide- film 24A, 24B on silicon chip 20 or the supporting substrate 25 at device at embedding oxide-film 24A, the 24B of device with silicon chip 20 and supporting substrate 25 tops formation predetermined thickness.At this moment because field oxide film 23, device with silicon chip 20 on the embedding oxide-film 24A of formation topological graph is arranged.For removing this topological graph, chemistry, mechanically grind embedding oxide-film 24A, make device have smooth surface with silicon chip 23.
Then, referring to Fig. 1 D, bonding device makes embedding oxide- film 24A, 24B contact with silicon chip 20 and supporting substrate 25.For making device predetermined thickness be arranged, to its grinding, polishing with silicon chip 20.Then, make the etching block film with field oxide film 23, the device of chemistry, mechanically grinding remnants exposes field oxide film 23 surfaces with silicon chip 20, is formed with certain thickness silicon device layer 20A.
Do not need the step of other formation etching block film, form silicon device layer by make the etching block film with field oxide film, preparation has certain thickness silicon device layer under the situation of additional process steps not, can form SOI substrate 300.
Fig. 2 A-2C is the figure that is used to illustrate other embodiment of the present invention, with reference to Fig. 2 A, and fabricate devices silicon chip 30 and supporting substrate 35.In order to form groove T, with forming photoresist figure (not shown) on the silicon chip 30, expose predetermined element marker space at device.
With this photoresist figure, by the anisotropic etch method, corrode desired depth on silicon chip 30 at device, form groove T.Wherein, regulate the silicon device layer thickness that forms device, the thickness that makes groove T is that 0.1～0.5 μ m is better.
Then, remove the photoresist figure.Oxide-film 31 is inserted on the thickness of groove T fully, forms device silicon chip 30.
Then, shown in Fig. 2 B, oppositely corrosion oxidation film 31 is exposed out with silicon chip 30 surfaces up to device, forms the groove element separation membrane 31B that fills out in groove T.Then, on device usefulness silicon chip 30 and/or supporting substrate 35, form embedding oxide-film by thermal oxidation.
Shown in Fig. 2 C, use known method, bonding device makes embedding oxide- film 32A, 32B contact with silicon chip 20 and supporting substrate 25.Then, the grinding and polishing device after the residual predetermined thickness, up to exposing groove element separation membrane 31B surface, forms the uniform silicon device layer 30A of thickness with chemistry, mechanical lapping with silicon chip 30.Thereby, need not increase processing step, just can improve the qualification rate that forms certain thickness silicon device layer, form SOI substrate 400.
In the foregoing description, the grinding and polishing device form silicon device layer smooth, uniform thickness with chemistry, mechanical lapping mode, but the present invention uses promptly reverse etch also can form silicon device layer smooth, uniform thickness with after the silicon chip.
More than, specific embodiment of the present invention is illustrated, but those skilled in the art can carry out various variations to it, and can not break away from the scope of the claim that the application's text put down in writing.
So, according to the present invention, cause formed the element separation membrane, makes etching block film, etch device substrate formation silicon device layer with this element separation membrane before the technique for sticking step, thereby did not need the formation processing step of other etching block film, just can form the uniform silicon device layer of thickness.

Claims (12)

1, a kind of manufacture method of SOI substrate is characterized in that comprising the following steps:
Configuration device silicon chip and supporting substrate;
Form the element separation membrane at described device on silicon chip;
Form the first embedding oxide-film at the device that forms described element separation membrane on silicon chip;
On described supporting substrate, form the second embedding oxide-film;
For making the described first and second embedding oxide-film surface contacts, bonding device silicon chip and supporting substrate;
The described device silicon chip of etching forms silicon device layer
2, SOI substrate manufacture method as claimed in claim 1 is characterized in that, the step that forms the element separation membrane at described device on the silicon chip predetermined portions also comprises:
Device with silicon chip on the step of stacked liner oxide film, silicon nitride film;
Remove the silicon nitride film and the liner oxide film of predetermined portions, expose the step of described predetermined element marker space;
Make the device that exposes silicon chip oxidation, form the step of field oxide film.
3, the manufacture method of SOI substrate as claimed in claim 2 is characterized in that, regulates the thickness of described silicon device layer in described oxidation technology with the oxidation depth of silicon chip according to device.
4, the manufacture method of described SOI substrate as claimed in claim 3 is characterized in that, to device with silicon chip in the degree of depth of oxidation be 0.1～0.5 μ m, form described field oxide film.
5, the substrate manufacture method of described SOI as claimed in claim 1 is characterized in that, the step that forms the element separation membrane at described device on the silicon chip predetermined portions also comprises:
For exposing predetermined element marker space at device on silicon chip, forming the step of photoresist figure;
Corrode the described silicon chip that exposes to desired depth, form the step of groove;
Remove the step of described photoresist figure;
Form the oxide-film of the thickness can fill and lead up groove on silicon chip at described device;
Oppositely the described oxide-film of corrosion is formed on the step of the element separation membrane in the groove.
6, the manufacture method of SOI substrate as claimed in claim 5 is characterized in that, oppositely corrodes in the step of described oxide-film, corrodes till the silicon chip surface is exposed.
7, the manufacture method of SOI substrate as claimed in claim 5 is characterized in that, according to the thickness of the described silicon device layer of depth adjustment of groove.
8, the manufacture method of SOI substrate as claimed in claim 7 is characterized in that, the degree of depth of described groove is 0.1～0.5 μ m.
9, the manufacture method of SOI substrate as claimed in claim 1 is characterized in that, thermal oxidation device usefulness silicon chip and supporting substrate, the formation described first and second embedding oxide-films.
10, the manufacture method of SOI substrate as claimed in claim 1 is characterized in that, forms in the step of described silicon device layer, and the element separation membrane is as the etching block film.
11, the manufacture method of SOI substrate as claimed in claim 1 is characterized in that, the described device of grinding and polishing is with after the silicon chip, chemistry, mechanically grinds described silicon device, up to exposing the element separation membrane.
12, the manufacture method of SOI substrate as claimed in claim 1 is characterized in that, the described device of grinding and polishing is with after the silicon chip, oppositely corrodes described silicon device layer, up to exposing the element separation membrane.
CN96123936A 1995-12-30 1996-12-30 Method for fabricating silicon-on-insulator substrate Expired - Lifetime CN1078737C (en)

Applications Claiming Priority (2)

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KR1019950069452A KR970052020A (en) 1995-12-30 1995-12-30 SOH eye substrate manufacturing method
KR69452/95 1995-12-30

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CN1162836A true CN1162836A (en) 1997-10-22
CN1078737C CN1078737C (en) 2002-01-30

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KR (1) KR970052020A (en)
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DE (1) DE19653199A1 (en)
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TW (1) TW348302B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148183A (en) * 2011-03-10 2011-08-10 上海宏力半导体制造有限公司 Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer

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KR20010056788A (en) * 1999-12-16 2001-07-04 박종섭 Method for fabricating soi substrate

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JPH0719839B2 (en) * 1989-10-18 1995-03-06 株式会社東芝 Method for manufacturing semiconductor substrate
JPH03180070A (en) * 1989-12-08 1991-08-06 Seiko Epson Corp Semiconductor device and manufacture thereof
JP2754819B2 (en) * 1989-12-28 1998-05-20 株式会社日本自動車部品総合研究所 Method for manufacturing dielectric-separated semiconductor substrate
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JP3099446B2 (en) * 1991-08-30 2000-10-16 株式会社デンソー Semiconductor substrate having dielectric isolation region
KR950000106B1 (en) * 1992-01-08 1995-01-09 삼성전자 주식회사 Manufacturing method of semiconductor device
US6103598A (en) * 1995-07-13 2000-08-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148183A (en) * 2011-03-10 2011-08-10 上海宏力半导体制造有限公司 Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer
CN102148183B (en) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer

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DE19653199A1 (en) 1997-07-03
GB2309826B (en) 2000-07-05
GB9626980D0 (en) 1997-02-12
JPH1050824A (en) 1998-02-20
KR970052020A (en) 1997-07-29
CN1078737C (en) 2002-01-30
GB2309826A (en) 1997-08-06
TW348302B (en) 1998-12-21

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