JP2000012674A - Manufacture of semiconductor device and method for separating element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve quality of a buried oxide film and to suppress the crystal defects caused by a thermal stress being generated on annealing by limiting timing, conditions, and the type of the oxide film for annealing. SOLUTION: A shallow groove 6 is formed on an Si substrate 1 at an STI region. Then, thermal oxidation is made and a thermal oxide film 7 is formed at the bottom and the side wall of the groove 6. After that, a second CVD oxide film 8 is deposited as the buried material of STI. Then, a second SiN film 9 is deposited on it and further an opening 11 is formed at a projecting part 12 on an element region. Then, before eliminating and flattening the projecting part 12, annealing is made in a 1,000 deg.C/N2 atmosphere to make fine the buried oxide film 8, and the projecting part 12 is eliminated for flattening with the first SiN film 3 and the second SiN film 9 as stoppers, thus making fine the quality of the buried oxide film 8 and suppressing the reduction of film being generated in a later etching process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device and a method for separating elements.

[0002]

2. Description of the Related Art In a semiconductor device, constituent elements such as transistors, diodes, capacitors, and resistors, which are electrically separated from each other on a semiconductor substrate, are interconnected by wiring. A technique for separating these elements is an element isolation technique.

In element isolation, it is necessary to reduce the element isolation width as much as possible while reducing the surface flatness, simplifying the process, and reducing the defect density to obtain good element characteristics, reliability and circuit performance. It is considered desirable.

The element isolation technology is based on LOCOS (LOCal Oxid
of Silicon) and STI (Shallow Trench Isolati)
on).

LOCOS for selectively oxidizing the surface of a semiconductor substrate
However, there is a problem in that a so-called bird's beak erodes the element formation region and generates a crystal defect due to a local stress generated when the field oxide film is formed.

As a device isolation technique which is an improvement of the LOCOS method, a BOX (Buried OXide) method, an improved coplanar method, a direct nitride mask method, a SWAMI (Side Wall Ma
(Sked Isolation), selective epitaxial method, U group method and the like have been proposed. Above all, the BOX method, which is an oxide film embedding method, has attracted attention as a device isolation technology in VLSI and the like on the order of submicrons. This is a method in which a U-groove is formed in a semiconductor substrate and is deposited so as to fill the U-groove with an insulating material.

As a trench element isolation method using the BOX method, Japanese Patent Application Laid-Open No. 9-82703 discloses a method in which hydrogen in a silicon oxide embedded insulating film is replaced with oxygen. Japanese Patent Application Laid-Open Publication No. HEI 9-214, pp. 157-210, discloses a method in which a buried oxide film is subjected to a heat treatment at 1100 ° C. to 1350 ° C. before or after flattening so that a 5-membered or more ring structure and a 4-membered or less ring structure in the buried oxide film have a predetermined ratio. 8-153776
Japanese Patent Application Laid-Open No. 63-237542 discloses a method of burying an insulator made of a solid solution of an oxide of a Group IV element (Si, Ge, Sn). Each of the methods using the silicate glass is disclosed.

On the other hand, the STI method is advantageous for miniaturization. Specifically, after forming a groove in the element isolation region by RIE (reactive ion etching), an oxide film serving as a filling material is deposited by a CVD (chemical vapor deposition) method, and the oxide film deposited in a portion other than the groove is removed. , CMP (Chemical Mechanical Polishing) or the like to remove and flatten to perform element isolation.

Conventionally, since the thermal expansion coefficient of the semiconductor substrate is different from the thermal expansion coefficient of the insulating material embedded in the trench, stress is generated in the semiconductor substrate due to a thermal process during or after formation of the element isolation region, and crystal defects occur. There was a problem.

[0010] In particular, due to thermal stress at the time of annealing performed to densify the composition of the insulating material, crystal defects are generated particularly in the peripheral portion of the element isolation, and the leakage current does not reach the crystal defects. There was a problem that occurs.

Further, for example, when a silicon oxide film is used as an insulating material, 100 to 20 ppm of water is contained as an unavoidable impurity in the current technology. In addition to the difference in thermal expansion coefficient between the semiconductor substrate and the oxide film described above,
There is also a problem that excessive compressive stress is applied to the semiconductor substrate due to shrinkage of the film due to dissociation of moisture in the oxide film.

That is, a semiconductor device having a flat surface and no crystal defects after element isolation has been desired. In particular, it has been desired to suppress crystal defects caused by thermal stress during annealing.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an annealing process in which an insulating film is annealed at the time of element isolation of a semiconductor integrated circuit with less stress.

[0014]

According to the method of manufacturing a semiconductor device of the present invention, there are provided (A) a step of forming a groove in a surface of a semiconductor substrate, (B) a step of embedding an insulating material in the groove, and (C) an insulating material. (D) a step of removing an insulating film on the insulating material while leaving it partially, (E) a heat treatment of the insulating material from which the insulating film has been removed, (F) Flattening the heat-treated insulating material.

Further, a method of manufacturing a semiconductor device according to the present invention
(A) a step of sequentially depositing and patterning a first insulating material and a first insulating film on a surface of a semiconductor substrate to form a groove, and (B) a step of embedding a second insulating material in the groove.
(C) a step of laminating a second insulating film on the second insulating material, (D) a step of removing a part of the second insulating film on the second insulating material, and (E). Heat-treating the second insulating material from which the second insulating film has been removed, (F) flattening the heat-treated second insulating material, and (G) forming the first and second insulating films. And a removing step.

Further, the device isolation method of the present invention comprises the steps of (A)
Forming a groove on the surface of the semiconductor substrate, (B) embedding an insulating material in the groove, (C) laminating an insulating film on the insulating material, and (D) forming an insulating film on the insulating material. And (F) flattening the insulating material from which the insulating film has been removed, and (F) flattening the heat-treated insulating material.

The heat treatment temperature in the method for manufacturing a semiconductor device and the method for separating elements according to the present invention is 950 ° C. or higher. Further, it is characterized in that the insulating material is an oxide film and the insulating film is a nitride film.

More specifically, the present invention relates to annealing of a buried CVD oxide film in an element isolation step by the STI method, and is characterized in that annealing of the CVD oxide film is performed before flattening the STI.

That is, the quality of the buried oxide film is improved by limiting the timing, conditions, and type of the oxide film for performing the annealing, and the generation of crystal defects caused by thermal stress during the annealing is suppressed.

When comparing the magnitude of the stress caused by the annealing before and after the STI flattening, the stress is reduced when the annealing is performed before the STI flattening, compared with the case where the annealing is performed after the STI flattening.

That is, by annealing before the STI flattening, the stress is reduced, and the generation of crystal defects is suppressed.
Leakage current due to stress can be reduced.

The method of manufacturing a semiconductor device according to the present invention will be described in detail below.

A step of sequentially depositing an oxide film, a first insulating film acting as a stopper, and a layer acting as a mask on the surface of the semiconductor substrate, and forming the oxide film, the first insulating film and the mask film; Forming an opening in the semiconductor substrate, removing the mask layer remaining on the uppermost layer on both sides of the opening, and depositing a buried insulating material in the first opening; Forming a second insulating film acting as a stopper thereon, performing etching using the second insulating film as a stopper, annealing the buried insulating material, and annealing the buried insulating material And a step of removing the first and second insulating films.

The oxide film is, for example, SiO _2, and the first and second insulating films are, for example, SiN.

The annealing conditions will be described. In the present invention, in particular, the timing of annealing is important. By performing it before planarization, thermal stress can be reduced, and thus, the occurrence of crystal defects due to thermal stress and the resulting leakage current can be suppressed. Can be. The purpose of this annealing is to densify the CVD film. The annealing temperature is 95
The temperature may be 0 ° C or higher, but is preferably 950 ° C to 1100 ° C. The annealing atmosphere is an inert atmosphere such as nitrogen or argon, oxygen or a mixed gas thereof, and may be normal pressure or reduced pressure.

The first insulating film and the buried insulating material include:
For example, it is deposited by CVD. Examples of the CVD include a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, a photo CVD method using ultraviolet light, a liquid phase CVD method, and the like. Normal pressure C
The VD method is an ozone-based normal pressure CVD using ozone (O ₃ ) formed by introducing O ₂ into an ozonizer and discharging.
It may be a law. Low-pressure CVD (LPCVD) is, for example,
The reaction of TEOS-O3 may be performed under a reduced pressure of about 6.7 kPa. The plasma CVD method uses TEO by plasma discharge at about 13.56 MHz or 150 kHz.
This is performed using a gas source such as S, O ₂ , and He. Optical CVD
The methods are ArF (193 nm), KrF (249 nm),
It is performed by a photoreaction mainly using light energy of ultraviolet light, such as an excimer laser using XeCl (308 nm) or XeF (350 nm), a high-pressure mercury lamp, or a mercury-xenon lamp. Liquid phase CVD method, using e.g., RF discharge by the excited _{O 2} and TMS the (tetramethylsilane) -4
Perform at 0 ° C.

In this CVD, for example, a reducing gas such as H ₂ , an inert gas such as He, Ne, Ar, Kr, and Xe;
₂ , in a gas such as N ₂ , HCl, CO or CO ₂ ,
Alternatively, the treatment is performed in a mixed gas of two or more kinds selected from these.

The flattening of the annealed buried insulating material is performed by CMP (chemical mechanical polishing).

The buried insulating material in the semiconductor device of the present invention includes a silicon oxide film. As the organic silicon material, TEOS (tetraethyl _{orthosilicate: Si (OC 2 H 5)} 4), in particular, 03-TE
OS, LP-TEOS, P-TEOS; TMOS (tetramethoxysilane: Si (OC ₂ H ₅ ) ₄ ); TPOS
(Tetrapropoxysilane: Si (OC ₃ H ₇ ) ₄ );
DADBS (diacetoxy-di-tert-butoxy _{silane: C 4 H 9 O) 2} Si- (OCOCH 3) 2); HT
O (High Temperature Oxide); LTO (Low Temperat)
ure Oxie); PSG (Phospho-Silicate Glass), BP
SG (Boro-Phospho-Silicate Glass) and the like are exemplified. In particular, when TEOS and O ₃ are reacted, an insulating film can be formed at a low temperature of 450 ° C. or less, and the step coverage of the buried oxide film is good.

The width of the groove may be such that no void is formed when a CVD oxide film is buried in the groove. This depends on the film type, the degree of integration of the semiconductor device, and the like. For example, in LPTEOS, the thickness is 0.5 μm or more. The depth of the groove is 1 μm or less, for example, 0.3 to 0.7 μm in the case of a DRAM.

A method of manufacturing a semiconductor device according to the present invention
The present invention can be applied to both the mold and the bipolar mold, and is not particularly limited.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A series of STI forming steps in a method of manufacturing a semiconductor device according to the present invention will be described with reference to the following examples.

A semiconductor substrate 1, which is a Si wafer, is thermally oxidized to form a buffer oxide film 2. Next, STI C
A first SiN film 3 acting as a stopper on an element region at the time of MP is formed by CVD. Further, the first S
First C serving as a mask at the time of STI RIE on iN film 3
A VD oxide film 4 is deposited. (FIG. 1 (a)) Further, a photoresist is applied on the mask material, and an opening is formed in the portion of the resist to be the STI region by photolithography. Using the patterned resist as a mask, openings 5 (minimum width 0.5 μm) are formed in the first CVD oxide film 4, the first SiN film 3, and the buffer oxide film 2 by RIE. RIE may be performed, for example, by applying a mixed gas of CF ₄ and CHF ₃ at a pressure of 2 Pa and applying a high frequency power of 13.56 MHz at 500 W / cm ² . After that, the resist is stripped. Next, using the opening 5 as a window, Si RIE
Thereby, a shallow groove 6 having a depth of about 0.7 μm is formed in Si in the STI region. At this time, the RIE atmosphere gas is, for example, a mixture of HBr and NF ₃ . (FIG. 1B) After the formation of the shallow groove, the first CVD oxide film 4 serving as a mask for Si RIE is removed by wet etching using buffered hydrofluoric acid or the like. Next, in order to alleviate the stress applied to the corner of the shallow groove 6, light dry chemical dry etching (CDE) is performed to round the corner. After the rounding process, shallow grooves 6
In order to protect the side wall portion of the trench, thermal oxidation is performed to form a thermal oxide film 7 on the bottom and the side wall of the shallow groove 6. (Figure 1
(C) After forming the side wall thermal oxide film 7, a second CVD oxide film 8 is deposited as an STI filling material. (FIG. 1D) Next, a second SiN film 9 is deposited as a stopper on the STI during STI CMP, that is, on the field. Further, a photoresist 10 is applied on the second SiN film 9, and an opening 11 is formed in the protrusion 12 on the element region by photolithography. (FIG. 2 (e))
Next, the second SiN film 9 is opened by RIE, and then the photoresist 10 is removed. (FIG. 2 (f)) Next, before removing and flattening the protrusions 12, the embedded CVD oxide film 8 is densified at 1000 ° C./N ₂ atmosphere for densification.
Anneal for 0 minutes. After the annealing, the protrusions 12 are removed and planarized by CMP using the first SiN film 3 and the second SiN film 9 as stoppers. (FIG. 2G) After the planarization, the first SiN film 3 and the second Si
The N film 9 is removed by, for example, CDE to complete the formation of the STI. (FIG. 2 (h)) Thereafter, although illustration is omitted,
In the element formation region, ie, the SDG region, for example, MOS
A transistor is formed. The MOS transistor may be formed by a standard MOS process in which a drain region is formed in a self-aligned manner using a polysilicon gate.

In this embodiment, annealing is performed in the state shown in FIG. 2 (e).
1D, that is, immediately after depositing the STI buried CVD oxide film 8, and immediately before the state of FIG. 1G, that is, immediately before the planarization is performed.
All the heat treatments that have an effect of making the composition of the buried CVD oxide film 8 dense at a temperature of not less than ° C.

After the planarization is completed, a heat treatment is performed to
Compared to the case where the composition of the VD oxide film 8 is made dense, the embedded CVD oxide film 8 is formed by the heat treatment defined in the present invention.
When the composition is made denser, the thermal stress generated during the heat treatment is smaller, and thus the generation of crystal defects due to the thermal stress can be suppressed.

[0036]

According to the method of manufacturing a semiconductor device of the present invention, by performing a heat treatment, the quality of the buried oxide film can be densified, and the reduction of the film generated in the subsequent etching step can be suppressed. In addition, heat treatment reduces thermal stress and suppresses generation of crystal defects. As a result, it is possible to suppress the occurrence of leakage current due to thermal stress and crystal defects, and the characteristics of the semiconductor device are significantly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a sectional view showing one step of a method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Buffer oxide film 3 ... 1st SiN film 4 ... 1st CVD oxide film 5 ... Opening 6 ... Shallow groove 7 ... Thermal oxide film 8 ... second CVD oxide film 9 ... second SiN film 10 ... photoresist 11 ... opening 12 ... projection

Claims (12)

[Claims] (A) forming a groove in the surface of a semiconductor substrate; (B) embedding an insulating material in the groove; (C) laminating an insulating film on the insulating material; D) a step of removing the insulating film on the insulating material while leaving a part thereof; (E) a heat treatment of the insulating material from which the insulating film has been removed; and (F) a flattening of the heat-treated insulating material. And a method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the temperature of the heat treatment is 950 ° C. or higher. 3. The method according to claim 1, wherein the insulating material is an oxide film. 4. The method according to claim 1, wherein the insulating film is a nitride film. 5. A step of (A) sequentially depositing and patterning a first insulating material and a first insulating film on a surface of a semiconductor substrate to form a groove, and (B) a second insulating material in the groove. Embedding; (C) laminating a second insulating film on the second insulating material; and (D) removing the second insulating film on the second insulating material while leaving a part thereof. (G) a step of heat-treating the second insulating material from which the second insulating film has been removed; (F) a step of flattening the heat-treated second insulating material; A) removing the first and second insulating films. 6. The method according to claim 5, wherein the temperature of the heat treatment is 950 ° C. or higher. 7. The method according to claim 5, wherein the insulating material is an oxide film. 8. The method according to claim 5, wherein the insulating film is a nitride film. 9. A step of forming a groove in a surface of a semiconductor substrate, a step of embedding an insulating material in the groove, and a step of laminating an insulating film on the insulating material. D) a step of removing the insulating film on the insulating material while leaving a part thereof; (E) a heat treatment of the insulating material from which the insulating film has been removed; and (F) a flattening of the heat-treated insulating material. A device isolation method. 10. The device isolation method according to claim 9, wherein the temperature of the heat treatment is 950 ° C. or higher. 11. The element isolation method according to claim 9, wherein said insulating material is an oxide film. 12. The device isolation method according to claim 9, wherein said insulating film is a nitride film.