KR0185479B1 - Method for forming isolation film of semiconductor device - Google Patents
Method for forming isolation film of semiconductor device Download PDFInfo
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- KR0185479B1 KR0185479B1 KR1019950055925A KR19950055925A KR0185479B1 KR 0185479 B1 KR0185479 B1 KR 0185479B1 KR 1019950055925 A KR1019950055925 A KR 1019950055925A KR 19950055925 A KR19950055925 A KR 19950055925A KR 0185479 B1 KR0185479 B1 KR 0185479B1
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- film
- trench
- forming
- nitride film
- pad
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000002955 isolation Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000001301 oxygen Substances 0.000 claims abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 210000003323 beak Anatomy 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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Abstract
본 발명은 반도체 소자 제조공정 중 활성영역간의 절연, 분리를 위한 소자분리막 형성방법에 관한 것으로, 반도체기판에 패드산화막, 질화막을 형성하는 제 1 단계, 소자분리영역의 상기 질화막, 패드막을 식각하는 제 2 단계, 상기 질화막, 패드막을 마스크로한 식각공정을 통해 상기 반도체기판에 트렌치를 형성하되, 소정각도로 경사기게 형성하는 제 3 단계, 상기 트렌치 영역에 산소를 이온주입하여 산화막을 형성하는 제 4 단계, 상기 제 1 단계 내지 제 4 단계에 의한 구조의 전체 상부에 열산화(HTO)막을 형성하되, 상기 트렌치가 완전히 매립되도록 하는 제 5 단계, 상기 질화막을 식각종단점으로하여 CMP(Chemical Mechanical Polishing)하여 평탄화하는 제 6 단계 및 상기 질화막, 패드막을 제기하는 제 7 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of forming a device isolation film for insulation and separation between active regions in a semiconductor device manufacturing process, the method comprising: forming a pad oxide film and a nitride film on a semiconductor substrate; and etching the nitride film and the pad film of the device isolation region. A second step of forming a trench in the semiconductor substrate through an etching process using the nitride film and the pad film as a mask, and inclined at a predetermined angle, and a fourth step of forming an oxide film by ion implanting oxygen into the trench region A fifth step of forming a thermal oxidation (HTO) film on the entire structure of the structure according to the first step to the fourth step, wherein the trench is completely buried, CMP (Chemical Mechanical Polishing) by using the nitride film as an etching end point A sixth step of flattening and a seventh step of raising the nitride film and the pad film.
Description
제1a도 내지 제1f도는 본 발명의 일 실시예에 따른 소자분리막 형성과정을 나타내는 공정 단면도,1A to 1F are cross-sectional views illustrating a process of forming a device isolation film according to an embodiment of the present invention;
제2a도 내지 제2e도는 본 발명의 다른 실시예에 따른 소자분리막 형성과정을 나타내는 공정 단면도.2A through 2E are cross-sectional views illustrating a process of forming an isolation layer in accordance with another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 21 : 실리콘기판 2, 22 : 패드막1, 21: silicon substrate 2, 22: pad film
3, 23 : 질화막 4, 24 : 감광막패턴3, 23: nitride film 4, 24: photoresist pattern
5, 25 : 산화막 6, 26, 27 : 고온열산화(HTO)막5, 25: oxide film 6, 26, 27: high temperature thermal oxidation (HTO) film
27' : 열산화막 스페이서27 ': thermal oxide spacer
본 발명은 반도체 소자 제조공정 중 활성영역간의 절연, 분리를 위한 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming an isolation film for insulation and separation between active regions in a semiconductor device manufacturing process.
일반적으로, 소자분리기술로는 로코스(LOCOS), 폴리버퍼드-로코스(PB-LOCOS), 트렌치 등 다양한 기술이 실시 또는 제안되고 있다.In general, various technologies such as LOCOS, polybuffered LOCOS, and trenches have been implemented or proposed as device isolation technologies.
그러나, 통상의 로코스나 폴리버퍼드-로코스 기술은, 새부리형상(Bird's Beak)이 여전히 있고, 고접적소자에서 p+폴리실리콘을 채택한 경우, 보론(Boron)의 침투를 막기 위한 게이트 옥시나이트라이드 형성시 특히 N2O 어닐링에 의해 게이트 산화막이 얇아지는 현상(로코스 가장자리에 축적된 니트로젠 때문에)이 발성암으로 인해 제품의 전기적 특성을 저하시진다.However, conventional Locos or polybuffered-Lokose techniques still have gated beaks and, when p + polysilicon is employed in high-integration devices, gate oxynitrides to prevent Boron penetration The formation of the gate oxide thinning (due to nitrogen accumulated at the edge of the locose), especially by the formation of N 2 O annealing, degrades the electrical properties of the product due to the phonous rocks.
또한, 소자분리막이 두껍게 형성되기 때문에 평탄화(Planarization)가 어렵고, 공정 여유도(Process Margin)가 적다.In addition, since the device isolation layer is formed thick, planarization is difficult and process margin is low.
게다가, 활성영역의 증가가 어려워 활성영역을 넓히기 위해서는 많은 공정이 추가되고, 그에 따른 불량발생 가능성이 높다.In addition, it is difficult to increase the active area, so that many processes are added to widen the active area, and thus a high probability of defects is generated.
또한, 빛을 이용한 마스크 작업만으로는 소자분리막의 폭이 최소 0.4마이크로미터 정도밖에 디파인(define)할 수가 없어, 고접적 소자 제조에 적용이 곤란하다.In addition, only a mask operation using light can define a width of the device isolation film to be at least about 0.4 micrometer, which makes it difficult to apply a high-integral device.
한편, 트렌치를 이용하는 기술은 반용성 이온 식각(Reactive Ion Etching)으로 인한 손상(damage)이 않고, 이를 제거하기 위해 열산화 및 어닐링시 부피팽창 및 스트레스로 인한 결함발생 가능성이 있다.On the other hand, the technique using the trench is not damaged due to the reactive ion etching (Reactive Ion Etching), there is a possibility of defects due to volume expansion and stress during thermal oxidation and annealing to remove it.
상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 새부리형상의 유발을 방지하여 유효 활성영역 면적을 최대한 활용할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is an object of the present invention to provide a method for forming a device isolation layer of a semiconductor device that can maximize the effective active area area by preventing the beak shape.
또한, 본 발명은 평탄화가 용이하며, 이후의 포토리소그래피공정 등의 공정 여유도를 증가시키는 반도체 소자의 소자분리막 형성방법을 제공한을 다른 목적으로 한다.In addition, another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device which is easy to planarize and increases a process margin of a subsequent photolithography process.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자 제조공정 중 활성영역간의 절연, 분리를 위한 소자분리막 형성방법에 있어서, 반도체기판에 패드산화막, 질화막을 형성하는 제 1 단계, 소자분리영역의 상기 질화막, 패드막을 식각하는 제 2 단계, 상기 질화막, 패드막을 마스크로한식각공정을 통해 상기 반도체기판에 트렌치를 형성하되, 소정각도로 경사지게 형성하는 제 3 단계, 상기 트렌치 영역에 산소를 이온주입하여 산화막을 형성하는 제 4 단계, 상기 제 1 단계 내지 제 4 단계에 의한 구조의 전체 상부에 열산화(HTO)막을 형성하되, 상기 트렌치가 완전히 매립되도록 하는 제 5 단계, 상기 질화막을 식각종단접으로하여 CMP(Chemical Mechanical Polishing) 공정을 실시하여 평탄화하는 제 6단계 및 상기 질화막, 패드막을 제거하는 제 7 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a device isolation film for insulation and separation between active regions in a semiconductor device manufacturing process, the method comprising: forming a pad oxide film and a nitride film on a semiconductor substrate; A second step of etching the pad film, a third step of forming a trench in the semiconductor substrate through the etching process using the nitride film and the pad film as a mask, the inclined at a predetermined angle, ion implanted oxygen into the trench region to form an oxide film In the fourth step to form a thermal oxidation (HTO) film on the entire structure of the first to fourth steps, the fifth step to completely fill the trench, the nitride film is etched and terminated by CMP ( Chemical Mechanical Polishing) process, including the sixth step of planarization and the seventh step of removing the nitride film and the pad film. Characterized in that eojineun.
또한 본 발명은 반도체 소자 제조공정 중 활성영역간의 절연, 분리를 위한 소자분리막 형성방법에 있어서, 반도체기판에 패드산화막, 질화막을 형성한 다음, 소자분리영역의 상기 질화막, 패드막을 식각하는 제 1 단계, 상기 질화막, 패드산화막을 식각마스크로 하여 상기 반도체기판에 제1 트렌치를 형성하는 제 2 단계, 상기 상기 트렌치 측벽에 열산화막 스페이서를 형성하는 제 3 단계, 상기 열산화막 스페이서 및 질화막을 식각마스크로 하여 상기 반도체기판에 제 2 트렌치를 형성하되, 소정각도로 경사지게 형성하는 제 4 단계, 상기 트렌치 영역에 산소를 이온주입하여 산화막을 형성하는 제 5 단계, 상기 제 1 단계 내지 제 5 단계에 의한 구조의 전체 상부에 열산화(HTO)막을 형성하되, 상기 트렌치가 완전히 매립되도록 하는 제 6 단계, 상기 질화막을 식각종단점으로하여 CMP 공정을 실시하여 평탄한화하는 제 7 단계 및 상기 질화막, 패드막을 제거하는 제 8 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention also provides a method for forming a device isolation film for insulation and separation between active regions in a semiconductor device manufacturing process, the method comprising: forming a pad oxide film and a nitride film on a semiconductor substrate, and then etching the nitride film and the pad film in the device isolation region. A second step of forming a first trench in the semiconductor substrate using the nitride film and a pad oxide film as an etching mask, a third step of forming a thermal oxide spacer on the sidewalls of the trench, and using the thermal oxide spacer and the nitride film as an etching mask. To form a second trench in the semiconductor substrate, but inclined at a predetermined angle; a fifth step of forming an oxide film by implanting oxygen into the trench region; and a structure according to the first to fifth steps. A sixth step of forming a thermal oxidation (HTO) film on the entire upper portion of the trench to completely fill the trench; Due to various disadvantages characterized by comprising a first step and the eighth step of removing the nitride film, the pad film 7 to a flat screen by carrying out a CMP process.
이하, 첨부된 도면 제 1a 도 내지 제 1f 도 및 제 2a 도 내지 제 2e도를 참조하여 본 발명의 실시예를 상술한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings 1A to 1F and 2A to 2E.
제 1a 도 내지 제 1f 도는 본 발명의 일 실시예에 따른 소자분리막형성과정을 나타내는 공정 단면도로서, 먼저, 제 1a 도에 도시된 바와같이 실리콘기판(1)에 열산화 공정에 의한 SiO2패드막(2)과 저압화학기상층착(LPCVD)법에 의한 질화막(3)을 형성하고, 소자의 접적도에 따른 소자분리 간격을 최소 0.4마이크로미터 이상으로 디파인된 감광막패턴(4)을 형성한다.1A to 1F are cross-sectional views illustrating a process of forming a device isolation film according to an embodiment of the present invention. First, as shown in FIG. 1A, a SiO 2 pad film is formed by a thermal oxidation process on a silicon substrate 1. (2) and the nitride film (3) by the low pressure chemical vapor deposition (LPCVD) method is formed, and the photosensitive film pattern (4) having a device separation interval of at least 0.4 micrometer or more according to the device deposition degree is formed.
이어서, 제 1b 도에서 상기 감광막패턴(4)을 식각마스크로 하여 하부의 상기 질화막(3), 패드막(2)을 식각한 다음, 상기 감광막패턴(4)을 제거한다. 계속해서, 경사 60°의 트렌치를 최대깊이 0.4마이크로미터로 얕게 형성한다.Subsequently, in FIG. 1B, the nitride film 3 and the pad film 2 are etched using the photoresist pattern 4 as an etch mask, and then the photoresist pattern 4 is removed. Subsequently, a trench with an inclination of 60 ° is shallowly formed with a maximum depth of 0.4 micrometer.
계속해서, 산소를 1015내지 1017/㎠의 도즈로 이온주입한 다음, 1000℃ 이상의 고온에서 열처리하여 산소이온주입영역을 SiO2로 결합되로록하여 제 1c 도에 도시된 바와같이 500 내지 1000Å의 SiO2산화막(5)이 형성되도록 한다.Subsequently, oxygen is ion implanted at a dose of 10 15 to 10 17 / cm 2, and then heat treated at a high temperature of 1000 ° C. or higher to bond the oxygen ion implantation region to SiO 2 , as shown in FIG. 1C. An SiO 2 oxide film 5 of 1000 Å is formed.
제 1d 도에서 저압화학기상증착(LPCVD)법으로 SiH4와 N2O 가스를 이용하여 750 내지 850℃의 온도에서 고온열산화(HTO)막(6)을 증착하되, 상기 트렌치가 완전히 매립되도록 5000Å 이상 증착한다.In FIG. 1d, a high temperature thermal oxidation (HTO) film 6 is deposited at a temperature of 750 to 850 ° C. using SiH 4 and N 2 O gas by low pressure chemical vapor deposition (LPCVD), and the trench is completely buried. It deposits more than 5000Å.
다음으로, 제 1e 도에서 활성영역의 상기 질화막(3)을 식각종단점으로하여 CMP 공정으로 평탄화한다.Next, in FIG. 1E, the nitride film 3 of the active region is planarized by the CMP process with the etching end point.
끝으로, 제 1f 도에 도시된 바와같이 상기 질화막(3), 패드막(2)을 등방성 습식식각용액에서 제거하여 소자분리막 형성공정을 완료한다.Finally, as shown in FIG. 1F, the nitride film 3 and the pad film 2 are removed from the isotropic wet etching solution to complete the device isolation film forming process.
한편, 제 2a 도 내지 제 2e 도는 본 발명의 다른 실시예에 따른 소자분리막 형성과정을 나타내는 공정 단면도로서, 먼저, 제 2a 도에 도시된 바와 같이 실리콘기판(21)에 열산화 공정에 의한 SiO2패드막(22)과 저압화화기상증착(LPCVD)법에 의한 질화막(23)을 형성하고, 소자의 접적도에 따른 소자분리 간격을 최소 0.4마이크로미터 이상으로 디파인된 감광막패턴(24)을 형성한 후, 상기 감광막패턴(24)을 식각마스크로 하여 하부의 상기 질화막(23), 패드막(22)을 식각한다.2A through 2E are cross-sectional views illustrating a process of forming a device isolation film according to another exemplary embodiment of the present invention. First, as illustrated in FIG. 2A, SiO 2 may be formed on a silicon substrate 21 by a thermal oxidation process. The pad film 22 and the nitride film 23 formed by the low pressure vapor deposition (LPCVD) method are formed, and the photosensitive film pattern 24 having the device isolation interval of at least 0.4 micrometer or more according to the device adhesion degree is formed. Subsequently, the nitride layer 23 and the pad layer 22 in the lower portion are etched using the photoresist pattern 24 as an etch mask.
계속해서, 제 2b 도에서 상기 감광막패턴(24)을 제거한 다음, 플라즈마에 의한 전식식각으로 상기 실리콘기판(21)에 트렌치를 형성하되, 깊이는 1000 내지 2000Å 정도로 매우 얇게 형성한다.Subsequently, after removing the photoresist pattern 24 from FIG. 2B, a trench is formed in the silicon substrate 21 by electroetching by plasma, but the thickness is very thin, about 1000 to 2000 microns.
이어서, 저압화화기상증착(LPCVD)법으로 SiH4와 N2O 가스를 이용하여 750 내지 850℃의 온도에서 고온열산화(HTO)막(27)을 증착하되, 1000 내지 3000Å 두께로 증착한다. 이때, 두께는 스페이서 폭을 조절하기 위해 상기 범위내에서 필요한 두께를 결정한다.Subsequently, a high temperature thermal oxidation (HTO) film 27 is deposited at a temperature of 750 to 850 ° C. using SiH 4 and N 2 O gas by low pressure vapor deposition (LPCVD). At this time, the thickness determines the thickness required within the above range to adjust the spacer width.
다음으로, 제 2c 도에서 상기 고온열산화막(27)을 블랭킷 건식식각하여 상기 트렌치에 열산화막 스페이서(27)를 폭이 0.1 내지 0.3마이크로미터로 되도록 형성한다.Next, in FIG. 2C, the high temperature thermal oxide film 27 is blanket-etched to form a thermal oxide spacer 27 in the trench so as to have a width of 0.1 to 0.3 micrometer.
계속해서, 상기 열산화막 스페이서(27) 및 질화막(23)을 식각마스크로하여 다시 상기 실리콘기판(21)에 1000 내지 3000Å 깊이의 트렌치를 형성한다. 이때, 트렌치 폭은 상기 1차로 형성된 소자분리 폭과 스페이서폭에 의해 최소 0.1마이크로미터까지 디파인 가능하다. 또한, 상기 트렌치는 측벽이 50 내지 60°의 경사를 갖도록 형성한다.Subsequently, a trench having a depth of 1000 to 3000 Å is formed again on the silicon substrate 21 by using the thermal oxide spacer 27 and the nitride film 23 as an etching mask. In this case, the trench width may be defined to a minimum of 0.1 micrometer by the device isolation width and the spacer width formed primarily. In addition, the trench is formed so that the side wall has a slope of 50 to 60 °.
이후의 공정은 상기 제 1c 도 내기 제 1f 도의 공정 과정과 동일한것으로, 제 2d 도는 산소를 1015내지 1017/㎠의 도즈로 이온주입한 다음, 900℃ 이상의 고온에서 열처리하여 산소이온주입영역을 SiO2로 결합되도록 하여 500 내지 1000Å의 SiO2산화막(25)이 형성되도록 한 후 저압화화기상증착(LPCVD)법으로 SiH4와 N2O 가스를 이용하여 750 내지 850℃의 온도에서 고온열산화(HTO)막(26)을 증착하되, 상기 트렌치가 완전히 매립되도록 7000Å 이상 증착한 상태를 나타낸다.The subsequent process is the same as the process of FIGS. 1c to 1f, the 2d or ion ion implanted in a dose of 10 15 to 10 17 / ㎠, and then heat treated at a high temperature of 900 ℃ or more oxygen ion implantation region after allowing 500 to 1000Å of SiO 2 oxide film 25 is formed to be coupled to a SiO 2 lower pressure hwahwa vapor deposition (LPCVD) process with a high thermal oxidation at a temperature of 750 to 850 ℃ using SiH 4 and N 2 O gases While depositing the (HTO) film 26, the trench is 7000 or more so as to completely fill the trench.
끝으로, 제 2e 도는 활성영역의 상기 질화막(23)을 식각종단점으로하여 CMP 공정으로 평탄화한 후 상기 질화막(23), 패드막(22)을 등방성 습식식각용액에서 제거하여 소자분리막 형성공정을 완료한 상태를 나타낸다.Finally, the nitride film 23 of the active region 2e as the etching end point is planarized by a CMP process, and then the nitride film 23 and the pad film 22 are removed from the isotropic wet etching solution. Indicates completed state.
상기화 같이 이루어지는 본 발명은 다음과 같은 다양한 효과를 얻을 수 있다.The present invention made as described above can obtain various effects as follows.
첫째, 얕은 트렌치 또는 이중 트렌치 및 산소 이온주입공정을 통해 새부리형상이 없는 소자본리막을 형성함으로써 유효한 활성영역 면적을 최대한 활용할 수 있다.First, a shallow trench or double trench and an oxygen ion implantation process can be used to form a device main film without a beak shape to maximize the effective active area.
둘째, 단차(topology)가 거의 없도록 평판화함으로써 이후의 포토리소그래피 등의 공정시 공정마진이 증대된다.Second, the process margin is increased during the subsequent processes such as photolithography by flattening with little topology.
세째, 트렌치 식각시의 반응성 이온식각에 의한 손상도 제거함으로써 소자의 특성이 개선된다.Third, the characteristics of the device are improved by removing damage caused by reactive ion etching during trench etching.
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| KR100466199B1 (en) * | 1997-12-31 | 2005-05-17 | 주식회사 하이닉스반도체 | Device Separating Method of Semiconductor Device |
| KR100286902B1 (en) * | 1998-08-20 | 2001-05-02 | 황인길 | Shallow Trench Manufacturing Method for Isolation of Semiconductor Devices |
| KR100451499B1 (en) * | 1998-12-28 | 2004-12-13 | 주식회사 하이닉스반도체 | Device Separating Method of Semiconductor Device |
| KR100325620B1 (en) * | 1999-12-31 | 2002-02-25 | 황인길 | Method for forming shallow trench isolation |
| KR20030000132A (en) * | 2001-06-22 | 2003-01-06 | 주식회사 하이닉스반도체 | Forming method for field oxide of semiconductor device |
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