JPS59167029A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form a complete dielectric isolation structure by a method wherein a cavity part is formed on the bottom part of the vertical groove part selectively formed on the surface of a semiconductor substrate, an insulating film is filled in said groove, and an insulating film is formed inside the cavity part. CONSTITUTION:After an SiO2 film 12 has been selectively formed on a semiconductor substrate 11, a vertical groove 13 is formed by performing a vertical etching. Then, an SiO2 film 14 is formed in the groove 13. Subsequently, the SiO2 film located at the bottom part of the groove 13 is removed, and cavity parts 15 are formed at the bottom part of the groove 13 by performing an isotropic etching. As a result, an element forming region 16 is isolated by having the cavity parts 15 to come in contact with each other. Then, an SiO2 film 17 is filled in the groove 13 and, at the same time, an SiO2 film 18 is formed on the surface of the cavity part. Subsequently, when the film 12 is removed, the element isolation region is completed. As a result, an interelement isolation region of excellent crystallization can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region between elements of a semiconductor device.

(bl Prior Art and Problems Conventionally, in semiconductor integrated circuits (ICs), isolation regions between devices have been formed to electrically insulate individual semiconductor devices. be.

Among them, the PN junction isolation method has been used for the longest time, but it has drawbacks such as generation of parasitic capacitance and poor dielectric strength, so recently the dielectric isolation method has been used more commonly. However, the dielectric separation method also involves epitaxially growing N-type N2 on a P-type semiconductor substrate 1, as illustrated in FIG.
There are many methods in which only the side surfaces are separated by an insulating film 3, and complete dielectric separation is not achieved.

Therefore, as shown in FIG. 2, a complete dielectric isolation method has been proposed in which a semiconductor region 5 is provided on a semiconductor substrate 1, the bottom surface of which is also insulated by an insulating film 4. Complete dielectric isolation not only has the advantage of improving dielectric strength and eliminating parasitic capacitance, but also has the advantage of improving operating characteristics by creating complementary transistors in the vertical direction.

A method for forming such dielectric isolation is to provide a semiconductor substrate 1 with an uneven portion in advance, deposit a polycrystalline semiconductor layer thereon via an insulating film, and form a semiconductor region 5 by forming a single crystal by laser annealing or the like. This method is often used. However, this method does not necessarily provide good crystallinity.

In addition, as another dielectric isolation formation method, a single crystal substrate is provided with uneven portions, a polycrystalline semiconductor layer is deposited thereon via an insulating film, and this polycrystalline semiconductor layer is used as the semiconductor substrate 1. There is a method of polishing and removing the single crystal substrate from the back side to form the semiconductor region 5, but this method requires a large number of polishing steps and still has problems with accuracy.

fcl OBJECT OF THE INVENTION The present invention proposes a method for forming an isolation region between elements, which has the above-mentioned complete dielectric isolation structure and has good crystallinity in the element formation region.

(d) Structure of the Invention The purpose is to selectively form vertical grooves on the surface of a semiconductor substrate by vertical etching, form an insulating film on the surface of the vertical grooves, and then form an insulating film on the bottom surface of the vertical grooves. and forming a cavity at the bottom of the vertical groove by isotropic etching, and then filling the inner surface of the vertical groove with an insulating film and forming an insulating film inside the cavity. This is achieved by a method of manufacturing a semiconductor device that forms a semiconductor element region whose peripheral side surfaces and bottom surface are surrounded by an insulating film.

(e) Examples of the invention Examples will be described in detail below with reference to nine drawings.

3 to 7 are cross-sectional views in the order of steps of an embodiment according to the present invention. First, as shown in FIG. After forming a silicon dioxide (SiCh) film 12, vertical etching is performed using a Freon (CF4) based etching gas or active ion etching (RIE) to form a vertical groove 13. Next, as shown in FIG. 4, a 5i02 film 14 having a thickness of 1000 wafers is formed in the vertical groove 13.

Next, as shown in FIG. 5, the 5i02 film on the bottom surface of the vertical groove 13 was removed by vertical etching by RIE again.
Further, as shown in FIG. 6, a cavity 15 is formed at the bottom of the vertical groove 13 by isotropic etching by plasma ion etching.
form. By doing so, the cavities come into contact with each other as shown in the figure, and the element forming region 16 can be isolated.

Next, as shown in FIG. 7, high-temperature oxidation is performed to fill the vertical groove 13 with the 5i02 film 17, and at the same time, form the 5i02 film 18 on the surface inside the cavity 15.

In this case, it is preferable to fill the cavity 15 with the 5i02 film, but since the area is wider than the vertical groove 13, the cavity often remains.

After that, the element isolation region is completed by removing the 5i02 film 12 on the surface. However, if the above-mentioned formation method is used to form the vertical grooves 13 all around one element region at once, there is a risk that the element region will cave in. There is. Therefore, as shown in the plan view of FIG. 8, only the four corners 20 of the rectangular element region are not formed in the initial forming step, but are formed by repeating the above steps in the next step. FIG. 9 shows a cross-sectional structural diagram of the element isolation region thus completed.

(fl Effects of the Invention As can be seen from the description of the embodiments above, according to the present invention, a semiconductor substrate with good crystallinity can be formed with dielectric separation. It's a method.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of conventional device isolation methods;
7 to 7 are step-by-step cross-sectional views of the device isolation method according to the present invention, FIG. 8 is a plan view during the formation process, and FIG. 9 is a completed cross-sectional view. In the figure, 1.11 is a semiconductor substrate, 2, 5.16 is an element region, 3.4 is an insulating film, 12. 14. Reference numerals 17 and 18 indicate a silicon dioxide film, 13 a vertical groove, and 15 a cavity. Figure 1 Figure 2 Figure 3 Figure 5 Figure 7

Claims (1)

[Claims] Selectively forming vertical grooves on the semiconductor substrate surface by vertical etching, forming an insulating film on the surface inside the vertical grooves, then removing the insulating film at the bottom of the vertical grooves, and further etching by isotropic etching. The method includes a step of forming a cavity at the bottom of the vertical groove, and a step of filling the inner surface of the vertical groove with an insulating film and forming an insulating film inside the cavity, so that the peripheral side surfaces and the bottom are surrounded by the insulating film. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor element region including a semiconductor element region.