JP3141621B2 - Semiconductor substrate with dielectric isolation structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate having a dielectric isolation structure applied to a monolithic IC circuit and the like.

[0002]

2. Description of the Related Art A plurality of active elements are mounted on a single semiconductor substrate.
In a monolithic IC circuit in which passive elements are integrally formed, various techniques, such as a trench filling isolation method and a dielectric isolation method, as well as a PN junction isolation method, are used to separate element regions (islands) from each other. Isolation methods are known. In particular, the dielectric isolation method has an extremely small isolation capacity and a large isolation withstand voltage, a latch-up prevention effect,
In addition, they are widely used because they can achieve high integration density.

Further, as a semiconductor substrate having a dielectric isolation structure (hereinafter referred to as a “dielectric isolation substrate”), two silicon substrates are laminated with a silicon oxide film interposed therebetween, and an element region is formed on one surface thereof. A trench having a rectangular cross section which reaches the silicon oxide film around the periphery of the trench is formed by trench etching, an oxide film is formed on the inner side surface of the trench, and then a polysilicon ( There is known a configuration in which polycrystalline silicon is buried, and the polysilicon deposited on the substrate surface is removed by etching back, polishing, or the like, and planarized.

Next, a general method of manufacturing the dielectric isolation substrate will be described with reference to FIG. In FIG. 3A, 1 is a single crystal silicon substrate for forming a semiconductor element, 2 is a silicon substrate as a support substrate, and 3 is a silicon oxide film (SIO ₂ ) embedded between the silicon substrates 1 and 2. is there. First, a silicon oxide film 3 is formed on the back surface of the silicon substrate 1 by thermal oxidation. Subsequently, a silicon substrate 2 serving as a support substrate is superimposed on the silicon substrate 1 via the silicon oxide film 3 and further subjected to a heat treatment to perform SOI (Silicon on I
After forming the wafer 4, an etching mask layer (for example, silicon dioxide or silicon nitride) 5 is formed on the surface of the silicon substrate 1, and an isolation groove forming region is designed on the mask layer so as to surround the periphery of the element region. Open the window.

Next, as shown in FIG. 3 (b), a trench having a rectangular cross section reaching the silicon oxide film 3 is formed by performing trench etching such as reactive ion etching from a window opening of the etching mask layer 5. Then, a silicon oxide film 7 is formed on the inner wall of the isolation groove 6 by thermal oxidation as shown in FIG. Next, as shown in FIG.
After a polysilicon layer 8 is deposited on the wafer 4 from the surface side of the silicon substrate 1 by a low-pressure CVD method or the like and filled in the separation groove 6, the surface side of the silicon substrate 1 is subsequently etched back. While removing the polysilicon layer 8 on the surface, the silicon oxide film on the substrate surface is further removed by hydrofluoric acid cleaning. As a result, as shown in FIG. 3E, an element region (island) 9 separated by the silicon oxide films 3 and 7 and the polysilicon layer 8 is formed on the silicon substrate 1. In the dielectric isolation substrate, elements such as transistors and diodes are formed for each element region 8, and the elements are interconnected to form a monolithic IC circuit.

[0006]

By the way, in manufacturing the above-mentioned dielectric isolation substrate, when the polysilicon layer 8 is buried in the isolation groove 6 in the conventional configuration, it is necessary to completely fill the entire peripheral area thereof. Has the problem that polysilicon must be deposited more than expected. Next, this will be described with reference to FIGS. That is, the pressure reduction C is applied to the separation groove 6 formed in the silicon substrate 1 of the SOI wafer 4 in FIG.
When the polysilicon layer 8 is filled by the VD method, the polysilicon layer 8 is deposited at a uniform growth rate on the surface of the silicon substrate 1 and the side wall surface of the separation groove 6. Note that w in the figure
1 to w4 schematically represent the growth of the polysilicon layer 8 over time. Here, assuming that the groove width of the separation groove 6 is W and the groove depth is D, the separation groove 6 is completely filled ideally when the deposition thickness of the polysilicon layer 8 becomes W / 2. In addition, the deposited layer on the substrate surface side becomes flat.

However, actually, in order to flatten the polysilicon layer 8 over the entire surface of the substrate, an extra deposition thickness exceeding W / 2 is required, for the following reasons. That is, in the conventional dielectric isolation substrate, the element region 9
Is formed in a square pattern combining linear grooves as shown in FIGS. 5A and 5B.
Corner of the isolation groove 6 in (a), and the intersections of the grooves in (b), the diagonal groove width W _C of the separation groove 6 is 1.4 times approximately than the groove width W of the other linear portion Become. For this, C
In the process of depositing the polysilicon layer 8 by the VD method, if the thickness of the deposited layer is simply set to W / 2, the corners and the intersections of the above-mentioned separation grooves 6 cannot be completely filled, and To completely fill the entire circumference of the groove 6, W /
It is necessary to deposit extra polysilicon beyond the deposition thickness of 2. In addition, this extra deposition of polysilicon increases the amount of material used and also affects the etch-back process performed as a post-process, making it difficult to planarize the substrate, and thus increasing the manufacturing cost. It can also be a factor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to improve a formation pattern of an isolation groove so that a minimum deposition thickness required when polysilicon is embedded in the isolation groove by a CVD method. Accordingly, it is an object of the present invention to provide a dielectric isolation substrate capable of completely filling the isolation grooves.

[0009]

In order to achieve the above-mentioned object, in the dielectric isolation substrate of the present invention, the isolation grooves formed between the element regions are formed to have the same groove width over the entire peripheral area. Shall be. And, as a specific configuration,
The corner portion of the separation groove is formed by an arc-shaped groove pattern in which the inner and outer circumferences of the groove are concentric.

In the above structure, the separation groove is formed independently for each element region, and a dummy region is formed between the element regions separated by the separation groove .

[0011]

According to the above structure, in the process of depositing polysilicon in the separation groove by the CVD method and filling the groove, when the deposition thickness reaches half the groove width, the separation including the corner portion is performed. The entire circumference of the trench is completely filled with the polysilicon layer, and the polysilicon layer deposited on the surface of the silicon substrate is also flattened, so that the isolation trench is filled with polysilicon properly and sufficiently. In particular, by forming isolation grooves independently for each element region, and forming a dummy region between the element regions separated by the isolation groove,
The separation grooves can be prevented from intersecting with each other.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. The illustrated dielectric isolation substrate is manufactured by the manufacturing method described with reference to FIG. First, in FIG. 1, an isolation groove 6 trench-etched in the silicon substrate of the SOI wafer 4 around the periphery of the element region 8 is formed by connecting a linear groove and a corner groove exhibiting an arc-shaped pattern.
The groove width is designed to be the same groove width W in the entire peripheral area. That is, at the corner of the separation groove 6, the inner periphery (curvature radius r1) and the outer periphery (curvature radius r2) of the groove as viewed from the inside of the element region 9 are concentric circles, and the difference between the curvature radii r1 and r2. r2 -r1 is determined so as to have the same groove width W as the linear portion.

With this configuration, as described with reference to FIG. 3, in the process of depositing the polysilicon layer 8 by the CVD method and burying the isolation trench 6, the polysilicon layer 8 has a width corresponding to the trench width W as described with reference to FIG. When the deposition thickness of 8 reaches W / 2, the separation groove 6 is completely filled with no excess or shortage, and the polysilicon layer deposited on the surface of the silicon substrate also becomes flat.

FIG. 2 shows an applied embodiment obtained by developing the above-described embodiment. When the element regions 9 are arranged in a grid pattern on the SOI wafer 4, each element region 9 is formed. Separation grooves 6 are formed independently for each device, and dummy regions 10 are formed between the element regions 9 with the separation grooves 6 interposed therebetween. According to this separation groove pattern, it is possible to prevent the separation grooves from intersecting with each other, and it is possible to avoid the problem described above with reference to FIG.

[0015]

As described above, according to the present invention, the CV is applied to the isolation groove between the elements formed on the dielectric isolation substrate.
When the trench is filled with polysilicon by the method D, the entire peripheral area of the isolation trench can be completely and evenly filled with a minimum necessary deposition thickness. Therefore, it is possible to provide a semiconductor substrate having a dielectric isolation structure having a high practical value, such as a reduction in manufacturing cost as well as a rationalization of the step of embedding the isolation groove.

[Brief description of the drawings]

FIG. 1 is a partial plan view of a dielectric isolation substrate according to an embodiment of the present invention.

FIG. 2 is a partial plan view of a dielectric isolation substrate according to an application example of the present invention.

FIGS. 3A to 3E are explanatory views of a general method for manufacturing a dielectric isolation substrate, and FIGS. 3A to 3E are cross-sectional views of the dielectric isolation substrate shown in the order of the manufacturing process.

FIG. 4 is a diagram schematically showing a temporal growth of a deposition thickness when a trench is filled with polysilicon by a CVD method with respect to a separation trench of a dielectric isolation substrate.

5A and 5B are diagrams illustrating a pattern of a separation groove formed in a conventional dielectric separation substrate, wherein FIG. 5A is a plan view of a corner portion of the separation groove, and FIG. 5B is a partial plan view of an intersection of the separation groove.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 silicon substrate (supporting substrate) 3 silicon oxide film 4 SOI wafer 6 isolation groove 7 silicon oxide film on inner wall of groove 8 polysilicon 9 element region 10 dummy region

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-330765 (JP, A) JP-A-4-127148 (JP, A) JP-A-1-187944 (JP, A) JP-A-3- 62946 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/762 H01L 27/12

Claims (1)

(57) [Claims] 1. A semiconductor device comprising: a silicon oxide film sandwiched between two silicon substrates; and a separation groove having a rectangular cross section reaching the silicon oxide film surrounding one side of an element region on one surface thereof; An oxide film is formed on the inner surface of the groove, and polysilicon is deposited so as to completely fill the groove by a CVD method, and furthermore, the polysilicon deposited on the substrate surface is removed to provide a planarized dielectric isolation structure. In the semiconductor substrate, the separation groove is formed to have the same groove width over the entire circumference thereof, and the corner portion of the separation groove is formed such that the inner circumference and the outer circumference of the groove are concentric.
The groove is formed in an arc-shaped groove pattern.
Element regions formed independently of each other and separated by isolation grooves
A semiconductor substrate provided with a dielectric isolation structure , wherein a dummy region is formed between the semiconductor substrates.