JPH06334027A - Manufacture of semiconductor substrate with dielectric isolation structure - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a dielectric isolation substrate, in which polysilicon deposition on the surface region of the substrate is suppressed at the time of filling isolation grooves with polysilicon and a high- level surface flatness hardly requiring planarization by etch back, etc., is obtained. CONSTITUTION:In a dielectric isolation substrate in which isolation grooves 6 surrounding element regions 9 are etched after a silicon oxide film 5 is formed as an etching mask layer on the surface of a silicon substrate 1 and the grooves are filled with polysilicon by CVD method after an oxide film 7 is formed on the inner side faces of the isolation grooves, a phosphorus-doped polysilicon layer 10 for hindering the deposition of a polysilicon is previously formed on the surface region of the substrate other than the isolation grooves prior to filling the grooves with polysilicon. Thus, polysilicon 12 deposited on the substrate surface region other than the isolation grooves is suppressed at the time of filling the grooves.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to manufacturing of a semiconductor substrate having a dielectric isolation structure applied to a monolithic IC circuit or the like.

[0002]

2. Description of the Related Art A plurality of active elements on one semiconductor substrate,
In a monolithic IC circuit formed by integrating passive elements, various techniques such as a groove filling isolation method and a dielectric isolation method are used as techniques for isolating element regions (islands) from each other. Isolation methods are known. In particular, the dielectric isolation method has an extremely small isolation capacitance, a large isolation withstand voltage, and a latch-up prevention effect, as compared with the PN junction isolation method.
It is often used because of its high integration density.

As a semiconductor substrate having a dielectric isolation structure (hereinafter referred to as "dielectric isolation substrate"), an SOI (Silicon on Insulator) formed by bonding two silicon substrates with a silicon oxide film interposed therebetween. For wafer
A trench is formed on one surface of the trench to surround the periphery of the element region and reach the silicon oxide film, and an oxide film is formed on the trench inner side surface of the trench.
It is known that the isolation groove is filled with polysilicon (polycrystalline silicon) by the CVD method, and the polysilicon deposited on the surface of the substrate is removed by etching back, polishing, etc., and the entire substrate is flattened. .

Next, a general method of manufacturing the dielectric isolation substrate will be described with reference to FIGS. Figure 3 (a)
In the figure, 1 is a single crystal silicon substrate into which a semiconductor element is built, 2 is a silicon substrate as a supporting substrate, 3 is a silicon oxide film (SI) embedded between the silicon substrates 1 and 2.
O ₂ ). First, the silicon oxide film 3 is formed on the back surface side of the silicon substrate 1 by thermal oxidation. Subsequently, the silicon substrate 1 serving as a supporting substrate is superposed on the silicon substrate 1 with the silicon oxide film 3 interposed therebetween, and further heat-treated to obtain SO.
The I wafer 4 is formed. Subsequently, a silicon oxide film 5 serving as an etching mask layer is formed on the surface of the silicon substrate 1 with respect to the wafer 4, and further, with respect to the silicon oxide film 5,
A photoresist is applied, and then a photolithography method is used to open a window for an isolation groove forming region which is designed so as to surround a predetermined element region 9.

Next, as shown in FIG. 3B, isolation trenches 6 (for example, a trench width of 20 μm, a trench width of 20 μm, trenches are formed from the window opening of the etching mask layer to reach the silicon oxide film 3 by trench etching such as reactive ion etching. Depth of 50 μm), followed by normal well-known thermal oxidation, as shown in FIG.
As shown in (c), a thin silicon oxide film 7 having a thickness of about 1 μm is formed on the inner sidewall of the isolation trench 6.

Next, as shown in FIG. 3D, the SOI wafer 4
On the other hand, by the CVD method using silane as a source gas, polysilicon 8 is deposited from the surface side of the silicon substrate 1 to fill the separation groove 6. When the deposited thickness of the polysilicon 8 grows to 10 μm, the inside of the separation trench 6 is filled with the polysilicon 8 and at the same time, the polysilicon 8 of about 10 μm is deposited on the surface side region of the wafer 4. Like Subsequently, the entire surface area of the silicon substrate 1 is etched back by RIE (reactive ion etching) or polished to remove the polysilicon 8 deposited on the surface area of the substrate. As a result, as shown in FIG. 3E, element regions (islands) 9 separated by the silicon oxide films 3 and 7 and the polysilicon layer 8 are formed on the silicon substrate 1. In addition, on the dielectric isolation substrate, semiconductor elements such as transistors and diodes are formed in each element region 9, and wirings for interconnecting the elements are formed to form a monolithic IC circuit.

[0007]

The dielectric isolation substrate manufactured through the above steps has the following problems. That is, in the prior art, the polysilicon deposited on the surface of the substrate causes warping and distortion of the substrate, and the flattening of the separation groove is not always complete due to this warping, and even after etching back and polishing are performed. A step is likely to occur on the surface of the isolation groove portion filled with polysilicon. Therefore, in the subsequent wiring formation, the wiring that connects the elements to each other across the separation groove may be disconnected due to the step.

On the other hand, as a solution to the above-mentioned problem, Japanese Patent Laid-Open No. 58-199536 discloses a method in which the flatness of the polysilicon embedded in the isolation trench is increased to a level at which the wiring formed thereafter is not broken. It is disclosed.
That is, assuming that the groove width of the separation groove is W, the groove depth is D, and the film thickness of the groove filling material deposited on the surface of the substrate is H, 1.0 ≧ H / D ≧ 0.1 + 0. If the relationship of 625 (W / D) ² is established, it is said that the flatness at a level at which the wiring is not broken by the flattening by the etch back performed after the filling is obtained.

However, when the groove depth D of the separation groove is large and the W / D ratio is relatively large, and when D = 50 μm and W = 20 μm as specific numerical values, the above equation is given as follows. become that way. 1.0 ≧ H / 50 ≧ 0.2, therefore 50 ≧ H ≧ 10 That is, the layer thickness H of the groove filling material deposited on the surface of the substrate needs to be at least 10 μm or more. However, when the layer thickness of the groove filling material deposited on the substrate surface becomes large, the crystal grains become large when the groove filling material is polycrystalline silicon (polysilicon), and the single crystal silicon region and the polycrystalline silicon region are Due to the difference in thermal expansion of the wafer, a new problem such as warp is easily generated, which causes non-uniformity in the subsequent etch back, resulting in a high level of flatness that does not cause disconnection of the wiring. It is extremely difficult to obtain.

Further, such a problem is not limited to the above-mentioned specific numerical examples, and generally, a separation groove having a large groove depth D (when D becomes large, it becomes difficult to obtain a high aspect ratio D / W, and naturally, it becomes difficult. The W / D ratio becomes a relatively large value, and the lower limit value of H becomes large). The present invention has been made in view of the above points, and an object thereof is to solve the above problems and to obtain a high level surface flatness that hardly requires additional flattening treatment such as etch back. Another object of the present invention is to provide a method for manufacturing the dielectric isolation substrate.

[0011]

According to the present invention, the above-mentioned object is achieved by forming a suppression layer for inhibiting the deposition of polysilicon on the surface of the substrate other than the isolation groove, prior to the polysilicon filling step. It Here, the polysilicon that fills the isolation trench is non-doped polysilicon, and the non-doped polysilicon deposition suppressing layer formed in the substrate surface region is a phosphorus-doped polysilicon layer.

As a specific method of forming the non-doped polysilicon suppressing layer, a silicon oxide film serving as an etching mask for forming a separation groove is formed on the surface of a silicon substrate, and then the silicon oxide film is further formed. On the surface,
A method of forming a phosphorus-doped polysilicon layer that functions as a suppression layer by a CVD method using phosphine as a source gas, or a silicon oxide film is formed as an etching mask for forming a separation groove on the surface of a silicon substrate, and then the silicon oxide film is formed. There is a method in which a phosphoric acid aqueous solution is brought into contact with the surface of the film and further heat-treated to form a phosphorus-doped silicon oxide film layer which functions as a suppression layer.

[0013]

As in the above method, the present invention provides a phosphorus-doped polysilicon layer which suppresses the deposition of non-doped polysilicon on the surface of an etching mask layer of an isolation groove formed in advance on the surface of a semiconductor substrate. , Or a thin film of a phosphorus-doped silicon oxide film layer (phosphorus glass: PSG) is formed by coating, the deposition thickness of non-doped polysilicon deposited on the surface region of the substrate during the step of filling the separation groove by the CVD method. Is extremely reduced, and the fact that only the isolation trench is filled with polysilicon is utilized.

That is, comparing the case where the surface of the etching mask layer formed in the surface region of the wafer is non-doped polysilicon and the case where it is phosphorus-doped polysilicon with phosphine added, for example, CVD under the same growth conditions The growth rate of the groove filling material (non-doped polysilicon) on the substrate surface region by the method is GR _n when the surface of the etching mask layer is non-doped polysilicon, and the growth rate when it is phosphorus-doped polysilicon. _Let GR _d be GR _d / GR _n ≈0.05. That is, by making the surface of the etching mask layer non-doped polysilicon, the deposition thickness of the non-doped polysilicon that is the groove filling material becomes extremely small. The difference in the growth rate is that if the phosphine molecules adsorbed on the surface on the substrate side or the phosphorus on the surface and hydrogen in the air are bound, the substrate surface area will be increased during the subsequent groove filling process by the CVD method. Revealed by inhibiting the adsorption of silane molecules onto the. Regarding the difference in the growth rate and the mechanism thereof, as described in J. Electr,
rochem Soc, Vol131, No10, p2361-2368, October, 1984.

Therefore, prior to filling the isolation trench with non-doped polysilicon, the isolation trench previously formed on the substrate surface is prevented so as to prevent polysilicon from being deposited on the substrate surface region other than the trench. By depositing a phosphorus-doped polysilicon layer or a phosphorus-doped oxide film layer on the surface of the etching mask layer (silicon oxide film), almost all of the polysilicon is deposited in the surface region of the substrate. However, after the isolation trench is filled with polysilicon, the surface becomes a flat state to the extent that the surface flattening process such as etching back is hardly required. As a result, there is almost no warpage on the substrate, and it is possible to omit the surface flattening process such as etching back. Also, it is possible to prevent wiring disconnection problems caused by uneven steps in the separation groove during subsequent wiring formation. It can be avoided.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to those in FIG. 3 are designated by the same reference numerals. Example 1 FIGS. 1A to 1D show a manufacturing process of a dielectric isolation substrate. First, in FIG. 1A, an etching mask layer was formed on the surface of a silicon substrate 1 for an SOI wafer 4. A silicon oxide film 5 having a thickness of about 1 μm is formed, and a thin film functioning as a suppression layer that inhibits the deposition of non-doped polysilicon is further formed on the silicon oxide film 5 by a low pressure CVD method using phosphine as a source gas. A phosphorus-doped polysilicon layer 10 is formed. In this case, if the wafer 4 is left in the phosphine atmosphere for a while after the film is formed, a large amount of phosphine is adsorbed on the surface of the film, which is more effective. But,
Even if the phosphine is not adsorbed on the film surface at this time, if phosphorus is doped, the phosphorus on the surface and the hydrogen in the air are naturally bound in the subsequent steps. It will be effective. Next, as shown in FIG. 1B, a photoresist 11 is applied to the surface of the phosphorus-doped polysilicon layer 10, and a region for forming the isolation trench 6 surrounding the periphery of a predetermined device region is opened by a photolithography method. Etching mask (silicon oxide film 5,
After forming the phosphorus-doped polysilicon layer 10), the isolation trench 6 reaching the silicon oxide film 3 of the wafer 4 is trench-etched in the silicon substrate 1 through the window opening between the etching masks (5, 10). Subsequently, the photoresist 11 is entirely removed, and then, as shown in FIG. 1C, a silicon oxide film 7 is formed on the inner sidewall of the isolation trench 6. Next, when the non-doped polysilicon 12 is deposited from the front surface side of the wafer 4 by the CVD method, the non-doped polysilicon 12 is hardly deposited on the surface of the etching mask (5, 10), and the non-doped polysilicon 12 shown in FIG. Thus, only the isolation trench 6 is filled with the non-doped polysilicon 12, and in this state as it is, a relatively high level flatness of the substrate surface can be obtained.

As a result, after the isolation trench 6 is filled with the polysilicon 12, it is possible to omit the processing step of surface flattening by etching back, polishing, etc. as described in the manufacturing method of FIG. Therefore, after the phosphorus-doped polysilicon layer 10 on the surface of each region is removed by etching, it is possible to directly proceed to the process of forming the device in each device region 9 and the wiring forming process.

Embodiment 2 FIG. 2 shows a manufacturing method of a different embodiment of the present invention. In this embodiment, S
As shown in FIG. 2A, a silicon oxide film 5 serving as an etching mask layer is formed on the surface of the silicon substrate 1 on the OI wafer 4 as in the manufacturing method described with reference to FIG. 2), a window of the etching mask layer is opened, trenches of the isolation trench 6 are etched, and a silicon oxide film 7 is formed on the sidewall of the trench with respect to the isolation trench 6, and then the SOI wafer 4 is removed as shown in FIG. 2C. Silicon oxide film 5 upside down
Dip the surface of the solution in the liquid surface of the phosphoric acid aqueous solution 13, and
Heat treatment (annealing) is performed at 00 ° C. for about 30 minutes. As a result, as shown in FIG. 2D, the phosphorus-doped silicon oxide film (phosphorus glass) that functions as a non-doped polysilicon suppressing layer is thin on the surface of the silicon oxide film 5 in the surface region of the substrate excluding the isolation trench 6. Molded. As described above, the phosphorus on the surface of the phosphorus glass is immediately bound to hydrogen in the air. Then, in this state, the separation groove 6 is formed by the CVD method.
When undoped polysilicon 12 is deposited on FIG.
As shown in (e), the polysilicon 12 is hardly deposited on the surface region of the phosphoric acid-treated substrate, is embedded only in the separation groove 6, and a surface state with high flatness is obtained over the entire substrate. .

[0019]

As described above, according to the present invention, prior to filling the isolation trench formed in the dielectric isolation substrate with non-doped polysilicon by the CVD method, the substrate surface region other than the isolation trench is phosphorus-doped. By forming the suppression layer such as the polysilicon layer of the above, the phosphorus-doped silicon oxide film layer, etc., it becomes possible to prevent the non-doped polysilicon from being deposited on the surface region of the substrate in the next groove filling step, and the isolation layer is separated. After filling the trench with polysilicon, a relatively flat surface state can be obtained without performing a flattening process such as an etch back on the substrate surface as in the conventional method. As a result, it is possible to reduce or simplify the flattening step in manufacturing the substrate, and it is possible to prevent the disconnection of the wiring due to the step during the subsequent wiring formation.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a method for manufacturing a dielectric isolation substrate according to a first embodiment of the present invention, in which (a) to (d) are cross-sectional views of the dielectric isolation substrate shown in the order of manufacturing steps.

FIG. 2 is an explanatory diagram of a method for manufacturing a dielectric isolation substrate according to a second embodiment of the present invention, in which (a) to (e) are cross-sectional views of the dielectric isolation substrate shown in the order of manufacturing steps.

FIG. 3 is an explanatory diagram of a conventional method for manufacturing a dielectric isolation substrate, in which (a) to (e) are cross-sectional views of the dielectric isolation substrate shown in the order of manufacturing steps.

[Explanation of symbols]

 1 Silicon Substrate 2 Silicon Substrate (Supporting Substrate) 3 Silicon Oxide Film 4 SOI Wafer 5 Silicon Oxide Film (Etching Mask Layer) 6 Separation Groove 7 Silicon Oxide Film on Inner Side Wall 9 Element Area 10 Non-Doped Polysilicon Layer 12 Phosphorus-Doped Polysilicon 13 Phosphoric Acid Aqueous Solution 14 Phosphorus-Doped Silicon Oxide Film

Claims (4)

[Claims] 1. A semiconductor substrate in which two silicon substrates are bonded together with a silicon oxide film sandwiched between them, and a separation groove is formed on one surface of the semiconductor substrate so as to surround the element region and reach the silicon oxide film. After forming an oxide film on the inner side surface of the groove, the inside of the groove is filled with polysilicon by the CVD method,
Furthermore, in a method of manufacturing a semiconductor substrate having a dielectric isolation structure in which the polysilicon deposited on the surface of the substrate is removed and then the entire substrate is planarized, prior to filling with polysilicon, a polysilicon is formed in a substrate surface region other than the isolation trench. A method of manufacturing a semiconductor substrate having a dielectric isolation structure, characterized in that a suppression layer that inhibits deposition of silicon is formed by coating. 2. The manufacturing method according to claim 1, wherein the polysilicon with which the isolation groove is filled is non-doped polysilicon,
A method of manufacturing a semiconductor substrate having a dielectric isolation structure, wherein the non-doped polysilicon deposition suppressing layer on the substrate surface region is a phosphorus-doped polysilicon layer. 3. The manufacturing method according to claim 1, wherein after forming a silicon oxide film as an etching mask for forming a separation groove on the surface of the silicon substrate, phosphine is used as a raw material on the surface of the silicon oxide film. A method of manufacturing a semiconductor substrate having a dielectric isolation structure, wherein a phosphorus-doped polysilicon layer functioning as a suppression layer is formed by a CVD method using gas. 4. The manufacturing method according to claim 1, wherein after forming a silicon oxide film on the surface of the silicon substrate as an etching mask for forming a separation groove, a phosphoric acid aqueous solution is brought into contact with the surface of the silicon oxide film. A method for manufacturing a semiconductor substrate having a dielectric isolation structure, further comprising heat treatment to form a phosphorus-doped silicon oxide film layer functioning as a suppression layer.