KR100335264B1 - Method for manufacturing isolation layer in semiconductor device - Google Patents
Method for manufacturing isolation layer in semiconductor device Download PDFInfo
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- KR100335264B1 KR100335264B1 KR1019950066148A KR19950066148A KR100335264B1 KR 100335264 B1 KR100335264 B1 KR 100335264B1 KR 1019950066148 A KR1019950066148 A KR 1019950066148A KR 19950066148 A KR19950066148 A KR 19950066148A KR 100335264 B1 KR100335264 B1 KR 100335264B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 33
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 claims abstract 4
- 125000006850 spacer group Chemical group 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 제조 방법에 관한 것으로 특히, 트렌치 구조의 소자분리막 제조방법에 있어서, 질화막패턴과 패드산화막패턴의 측벽에 스페이서를 형성하고, 상기 전 구조를 플라즈마로 처리하고, 상기 스페이서의 기울기와 완만한 형상을 이용하여 반도체기판에 트렌치를 형성하므로써, 상기 구조의 전표면에 오존-TEOS(OZONE -Tetra Ethyl Ortho Silicate) 산화막을 매립할 때, 공극(void)의 생성을 방지하여 소자의 신뢰성을 향상할 수 있는 반도체소자의 소자분리막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device isolation film of a semiconductor device. In particular, in a device isolation film manufacturing method having a trench structure, spacers are formed on sidewalls of a nitride film pattern and a pad oxide film pattern, and the entire structure is treated with plasma. By forming the trench in the semiconductor substrate using the slope and the gentle shape of the device, when the OZONE-Tetra Ethyl Ortho Silicate oxide film is buried in the entire surface of the structure, voids are prevented from being generated. It relates to a device isolation film manufacturing method of a semiconductor device that can improve the reliability of the.
일반적으로 반도체소자는 트랜지스터나 캐패시터등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작을 서로 방해하지 않도록 활성영역들을 분리하는 소자분리영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region in which devices such as transistors and capacitors are formed, and an isolation region separating the active regions so as not to interfere with each other.
최근 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, with the trend toward higher integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.
이러한 소자분리영역의 제조방법으로는 질화막패턴을 마스크로하여 실리콘 반도체기판을 열산화시키는 통상의 로코스(local oxidation of silicon) 방법이나, 반도체기판에 트렌치를 형성하고 이를 절연물질로 메우는 트렌치(trench)분리등의 방법이 사용되고 있다.As a method of manufacturing the device isolation region, a conventional local oxidation of silicon method of thermally oxidizing a silicon semiconductor substrate using a nitride film pattern as a mask, or a trench for forming a trench in a semiconductor substrate and filling it with an insulating material The separation method is used.
제 1A 도 내지 제 ID 도는 종래의 실시예에 따른 반도체소자의 소자분리막 제조 공정도이다.1A to ID are process diagrams for fabricating an isolation layer of a semiconductor device according to a conventional embodiment.
제 1A 도를 참조하면, 반도체기판(1)의 상부에 패드산화막(2)과 제1 질화막(3)을 차례로 형성한다.Referring to FIG. 1A, a pad oxide film 2 and a first nitride film 3 are sequentially formed on the semiconductor substrate 1.
상기 반도체기판(T)에서 소자분리영역으로 예정되어 있는 부분상의 질화막(3)과 패드산화막(2)을 반도체기판(1)이 노출될 때까지 차례로 식각하여 제1 질화막(3)패턴과 패드산화막(2)패턴을 형성한다.The first nitride film 3 pattern and the pad oxide film are sequentially etched until the semiconductor substrate 1 is exposed by sequentially etching the nitride film 3 and the pad oxide film 2 on the portion of the semiconductor substrate T, which are intended as an isolation region. (2) A pattern is formed.
그 후, 상기 노출되어 있는 반도체기판(1)의 예정된 두께를 플라즈마 건식식각방법으로 제거하여 트렌치(5)를 형성한다.Thereafter, the predetermined thickness of the exposed semiconductor substrate 1 is removed by a plasma dry etching method to form the trench 5.
제 1B 도를 참조하면, 상기 트렌치(5)의 전 표면에 패드산화막(2)과 같은 두께의 열산화막(7)을 형성한다.Referring to FIG. 1B, a thermal oxide film 7 having the same thickness as the pad oxide film 2 is formed on the entire surface of the trench 5.
상기 열산화막(7)은 상기 트렌치(4) 형성시 상기 반도체기판(1)의 손상된 부분을 회복하는 역할을 한다.The thermal oxide film 7 serves to recover damaged portions of the semiconductor substrate 1 when the trench 4 is formed.
그 다음, 상기 전 구조를 플라즈마로 전처리하여 상기 전 구조의 표면에 손상을 가하므로써, 예정된 오존-TEOS막(8)의 증착을 용이하게 한다.The entire structure is then pretreated with plasma to damage the surface of the entire structure, thereby facilitating the deposition of the predetermined ozone-TEOS film 8.
제 1C 도를 참조하면, 상기 구조의 전 표면에 상기 트렌치(5)를 완전히 메우는 정도 이상의 두께로 절연재질, 예를들어 TEOS막(8)을 PE - CVD( Plasma Enhanced Chemical Vapor Deposition ) 공정으로 증착한다.,Referring to FIG. 1C, an insulating material, for example, a TEOS film 8 is deposited by a PE-CVD (Plasma Enhanced Chemical Vapor Deposition) process to a thickness that is at least about to completely fill the trench 5 on the entire surface of the structure. do.,
이때, 열산화막(7)과, 제1 질화막(3) 부위에서의 증착속도의 차이에 의하여 모서리 부위에 공극(voide, 7)이 형성된다.At this time, voids 7 are formed at the corners due to the difference in deposition rates at the thermal oxide film 7 and the first nitride film 3.
제 1D 도를 참조하면, 플라즈마를 이용한 건식식각으로 상기 TEOS막(8)을 식각한다.Referring to FIG. 1D, the TEOS film 8 is etched by dry etching using plasma.
그 다음, 상기 제1 질화막(1)패턴과, 패드산화막(2)패턴을 제거하고, 상기 TEOS막(8)을 반도체기판(1)이 노출될 때까지 식각한다.Next, the first nitride film 1 pattern and the pad oxide film 2 pattern are removed, and the TEOS film 8 is etched until the semiconductor substrate 1 is exposed.
그러나, 상기와 같은 종래의 소자분리막 제조 방법은 연속되는 질화막과 산화막 제거공정에 의하여 최종적으로 제 ID 도에 도시된 바와 같이 상기 TEOS막(8)의 가장자리가 활성영역보다 아래로 함몰되어 형성되므로 소자의 신뢰성을 해치는 문제점이 있다.However, in the conventional device isolation film fabrication method as described above, the edge of the TEOS film 8 is formed by recessing the active area below the active region as shown in FIG. ID by a continuous nitride film and oxide film removing process. There is a problem that impairs the reliability of the.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위한 것으로, 본 발명은 트렌치 구조의 소자분리막 제조방법에 있어서, 질화막패턴과 패드산화막패턴의 측벽에 스페이서를 형성하고, 상기 전 구조를 플라즈마로 처리하고, 상기 스페이서의 기울기와 완만한 형상을 이용하여 반도체 기판에 트렌치를 형성하므로써, 상기 구조의 전 표면에 오존-TEOS(OZONE - Tetra Ethyl Ortho Silicate) 산화막을 매립할 때, 공극(void)의 생성을 방지할 수 있는 반도체소자의 소자분리막 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to solve the above problems, and the present invention provides a method for manufacturing a device isolation film having a trench structure, forming spacers on sidewalls of a nitride film pattern and a pad oxide film pattern, and treating the entire structure with plasma. By forming a trench in the semiconductor substrate using the gradient and the gentle shape of the spacer, voids are generated when the ozone-TEOS (OZONE-Tetra Ethyl Ortho Silicate) oxide film is buried on the entire surface of the structure. It is an object of the present invention to provide a method for manufacturing a device isolation film of a semiconductor device that can be prevented.
상기 목적을 달성하기 위하여 본 발명의 반도체소자의 소자분리막 제조 방법은 반도체기판의 상부에 패드산화막과, 제1 질화막을 형성하는 단계다.In order to achieve the above object, a device isolation film manufacturing method of a semiconductor device of the present invention is a step of forming a pad oxide film and a first nitride film on an upper surface of a semiconductor substrate.
상기 반도체기판에서 소자분리영벽을 노출하는 제1 질화막패턴과, 패드산화막패턴을 형성하는 단계와,Forming a first nitride film pattern exposing the device isolation walls and a pad oxide film pattern on the semiconductor substrate;
상기 구조의 전 표면에 제2 질화막을 형성하는 단계와,Forming a second nitride film on the entire surface of the structure;
상기 제1 질화막패턴과 패드산화막패턴의 측벽에 제2 질화막스페이서를 형성하는 단계와,Forming a second nitride film spacer on sidewalls of the first nitride film pattern and the pad oxide film pattern;
노출되어 있는 반도체기판을 식각하여 트렌치를 형성하는 단계와,Etching the exposed semiconductor substrate to form a trench;
상기 트렌치가 형성된 부위의 반도체기판을 열산화하여 열산화막을 형성하는 단계와,Thermally oxidizing the semiconductor substrate at the portion where the trench is formed to form a thermal oxide film;
상기 전체 구조를 플라즈마로 처리하여 전체구조의 표면에 손상을 가하는 단계와Treating the entire structure with plasma to damage the surface of the entire structure;
상기 구조의 전 표면에 오존-TEOS막을 증착하는 단계와,Depositing an ozone-TEOS film on the entire surface of the structure;
상기 TEOS막, 제1 질화막패턴과, 제2 질화막스페이서 및 패드산화막을 식각하되, 반도체기판이 노출될 때까지 식각하는 단계를 포함하는 것을 특징으로 한다.And etching the TEOS layer, the first nitride layer pattern, the second nitride layer spacer, and the pad oxide layer, until the semiconductor substrate is exposed.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제 2A 도 내지 제 2G 도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도이다.2A through 2G are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with an embodiment of the present invention.
제 2A 도를 참조하면, 반도체기판(1)의 상부를 열산화하여 100 내지 300Å 두께의 패드산화막(2)을 형성하고, 상기 패드산화막(2)의 상부에 1000 ∼ 5000Å 두께의 제1 질화막(3)을 형성한다.Referring to FIG. 2A, a pad oxide film 2 having a thickness of 100 to 300 kPa is formed by thermally oxidizing an upper portion of the semiconductor substrate 1, and a first nitride film having a thickness of 1000 to 5000 kPa is formed on the pad oxide film 2. 3) form.
제 2B 도를 참조하면, 상기 반도체기판(1)에서 소자분리영역으로 예정되어 있는 부분상의 제1 질화막(3)과 패드산화막(2)을 반도체기판(1)이 노출될 때까지 차례로 식각하여 제1 질화막(3)패턴과 패드산화막(2)패턴을 형성한다.Referring to FIG. 2B, the first nitride film 3 and the pad oxide film 2 on the portion of the semiconductor substrate 1, which are intended to be an isolation region, are sequentially etched until the semiconductor substrate 1 is exposed. 1 pattern of nitride film 3 and pad oxide film 2 are formed.
제 2C 도를 참조하면, 상기 구조의 전 표면에 30 내지 300Å 두께의 제2 질화막(4)을 형성한다.Referring to FIG. 2C, a second nitride film 4 having a thickness of 30 to 300 Å is formed on the entire surface of the structure.
그 다음, 상기 제1 질화막(3)을 전면식각하여 상기 제1 질화막(3)패턴과 패드산화막(2)패턴의 측벽에 제2 질화막(4)스페이서를 형성한다.Next, the first nitride film 3 is etched entirely to form a second nitride film spacer 4 on the sidewalls of the first nitride film 3 pattern and the pad oxide film 2 pattern.
이때, 상기 제2 질화막(4)스페이서 대신에 산화막으로 스페이서를 형성할 수도 있다.In this case, a spacer may be formed of an oxide film instead of the second nitride film 4 spacer.
그 다음, 상기 노출되어 있는 반도체기판(1)의 1000 내지 4000Å 깊이를 플라즈마 건식식각하여 트렌치(5)를 형성한다.Next, the trench 5 is formed by plasma dry etching a depth of 1000 to 4000 microseconds of the exposed semiconductor substrate 1.
이때, 상기 트렌치(5)는 상기 제2 질화막스페이서에 의하여 기울어진 측벽으로 형성된다.In this case, the trench 5 is formed as a sidewall inclined by the second nitride film spacer.
제 2C도를 참고하면, 상기 트렌치(5)가 형성된 부위의 반도체기판(1)을 열산화하여 50 내지 300Å 두께의 열산화막(7)을 형성한다.Referring to FIG. 2C, a thermal oxide film 7 having a thickness of 50 to 300 Å is formed by thermally oxidizing the semiconductor substrate 1 in a portion where the trench 5 is formed.
상기 열산화막(7)은 상기 트렌치(5) 형성시 반도체기판(1)의 손상된 부분을 복구시키는 역할을 한다.The thermal oxide film 7 serves to recover damaged portions of the semiconductor substrate 1 when the trench 5 is formed.
그 다음, 상기 전 구조를 1 내지 4 Torr의 양력과, 300 내지 450℃ 온도에서 질소와 암모니아 분위기에서 플라즈마로 처리한다.Then, the entire structure is treated with plasma in a nitrogen and ammonia atmosphere at a lift of 1 to 4 Torr and a temperature of 300 to 450 ° C.
이때, 플라즈마로 전체구조를 처리하는 공정은 0.1 내지 0.5 KW의 고주파 전력 0.4 내지 0.8 KW의 저주파 전력에서, 질소의 유량은 3 내지 8 slm으로 하고, 암모니아의 유량은 2 내지 6 slm의 유량으로 하여 10 내지 30초간 진행한다.At this time, the process of processing the entire structure by plasma at a high frequency power of 0.4 to 0.8 KW of 0.1 to 0.5 KW, the flow rate of nitrogen is 3 to 8 slm, the flow rate of ammonia is 2 to 6 slm Proceed for 10 to 30 seconds.
제 2D 도를 참조하면, 상기 구조의 전 표면에 상기 트렌치(5)를 완전히 매우는 정도 이상의 두께로 절연재질, 예를들어 오존-TEOS막(8)을 증착한다.Referring to FIG. 2D, an insulating material, for example, an ozone-TEOS film 8, is deposited on the entire surface of the structure in a thickness that is at least about to completely enclose the trench 5.
이때, 상기 오존-TEOS막(8)은 상기 제1 질화막(3)패턴 상부 표면으로 부터 4000 내지 9000Å 두께로 형성한다.At this time, the ozone-TEOS film 8 is formed to a thickness of 4000 to 9000 Å from the upper surface of the first nitride film 3 pattern.
이때, 기울어진 형태의 스페이서와 완만한 형태의 모서리에 의하여 공극이 생성되지 않는다. 또한. 트렌치 측벽이 기울여져 있으므로 오존-TEOS막(8)의 매립이 용이하다.At this time, no gap is generated by the slanted spacer and the smooth edge. Also. Since the trench sidewalls are inclined, the ozone-TEOS film 8 is easily buried.
상기 제 2C 도에서 플라즈마로 상기 구조의 전 표면에 손상을 가하므로써, 오존-TEOS막(8)의 증착이 용이하다.In FIG. 2C, deposition of the ozone-TEOS film 8 is facilitated by damaging the entire surface of the structure with plasma.
참고로, 상기 오존-TEOS막(8), 제1 질화막(3)패턴과, 제2 질화막(4)스페이서 및 패드산화막(2)을 반도체기판(1)이 노출될 때까지 식각하며 소자분리막 제조 공정을 완료한다.For reference, the ozone-TEOS film 8, the first nitride film 3 pattern, the second nitride film 4 spacer and the pad oxide film 2 are etched until the semiconductor substrate 1 is exposed, thereby fabricating an isolation layer. Complete the process.
참고로, 상기 제2 질화막(4)스페이서 대신에 산화막스페이서를 형성할 경우, 산화막이 질화막과 증착특성이 다르긴 하지만 스페이서(4)와 반도체기판(1) 계면의 응력을 완화시키는 효과가 있다.For reference, in the case where the oxide spacer is formed instead of the second nitride film 4 spacer, the oxide film has a different deposition characteristic from the nitride film, but the stress of the interface between the spacer 4 and the semiconductor substrate 1 is relieved.
상술한 본 발명의 반도체소자의 소자분리막 제조방법은 트렌치 구조의 소자분리막 제조방법에 있어서, 질화막패턴과 패드산화막패턴의 측벽에 스페이서를 형성하고, 상기 전 구조를 플라즈마로 처리하고, 상기 스페이서의 기울기와 완만한 형상을 이용하여 반도체기판에 트렌치를 형성하므로써, 상기 구조의 전 표면에 오존-TEOS막을 매립할 때, 공극의 생성을 방지할 수 있는 반도체소자의 소자분리막 제조방법을 제공함에 그 목적이 있다.In the method of manufacturing a device isolation film of a semiconductor device of the present invention described above, in the method of manufacturing a device isolation film having a trench structure, spacers are formed on sidewalls of a nitride film pattern and a pad oxide film pattern, the entire structure is treated with plasma, and the inclination of the spacer is performed. The purpose of the present invention is to provide a method for manufacturing a device isolation film of a semiconductor device which can prevent the formation of voids when the ozone-TEOS film is buried in the entire surface of the structure by forming a trench in the semiconductor substrate using a smooth shape. have.
제1A도 내지 제1D도는 종래의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.1A to 1D are process diagrams for fabricating an isolation layer of a semiconductor device according to a conventional embodiment.
제2A도 내지 제2G도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.2A through 2G are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with an embodiment of the present invention.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
1 : 반도체기판 2 : 패드산화막1 semiconductor substrate 2 pad oxide film
3 : 제1 질화막 4 : 제2 질화막3: first nitride film 4: second nitride film
5 : 트렌치 7 : 열산화막5: trench 7: thermal oxide film
6 : 공극 8 : 오존-TEOS막6 voids 8: ozone-TEOS membrane
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19990066231A (en) * | 1998-01-23 | 1999-08-16 | 구본준 | Device isolation method of semiconductor device |
| KR100475049B1 (en) * | 1998-09-24 | 2005-06-17 | 삼성전자주식회사 | Trench element isolation method with thin film nitride liner |
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| KR100365740B1 (en) * | 1998-09-29 | 2003-04-23 | 주식회사 하이닉스반도체 | method of trench isolation using nitrogen diffusion |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19990066231A (en) * | 1998-01-23 | 1999-08-16 | 구본준 | Device isolation method of semiconductor device |
| KR100475049B1 (en) * | 1998-09-24 | 2005-06-17 | 삼성전자주식회사 | Trench element isolation method with thin film nitride liner |
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