KR100215699B1 - Method for isolating semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a device isolation layer of a semiconductor device, comprising: providing a semiconductor substrate having N wells and P wells and having a photoresist pattern formed thereon; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Sequentially forming a thermal oxide film and a high dielectric constant insulating film on the whole; Depositing and curing the SOG film to fill the trench; Etching the SOG film to expose the high dielectric constant insulating film; Forming a nitric oxide layer on the whole; Etching the nitride oxide film and the high dielectric constant insulating film to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate.

Description

A device isolation film formation method of a semiconductor device.

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device for separating between active regions of a semiconductor device.

In the manufacturing process of a semiconductor device, a device isolation process by oxidation or a trench is performed to isolate or insulate the device from the device, and in such a device isolation process, a thick oxide layer is provided between devices through oxidation. LOCOS (LOCal Oxidation Silicon) technology that separates them is mainly used.

However, the device isolation method using LOCOS technology has a problem in that the active area of the device is reduced due to the occurrence of bird's beak during the thermal oxidation process for forming the device isolation layer, which ultimately results in the semiconductor device. It acts as a cause of lowering the degree of integration and electrical properties.

Another conventional method for solving the above problem will be described with reference to FIGS. 1A to 1E.

Referring to FIG. 1A, an N well 2 and a P well 3 are formed in a semiconductor substrate 1 by a conventional ion implantation, and a photoresist pattern on the N well 2 and the P well 3 is formed, respectively. 4) is formed.

Referring to FIG. 1B, a trench 5 having a predetermined depth is formed in the semiconductor substrate 1 by an etching process using the photoresist pattern 4 as an etching mask.

Referring to FIG. 1C, the SOG film 7 is removed so that the photoresist pattern 4 is removed, the thermal oxide film 6 is formed over the entire top, and then the trench 5 is buried over the thermal oxide film 6. Is deposited and cured.

Referring to FIG. 1D, the SOG film 7 and the thermal oxide film 6 in the remaining regions except for the trench 5 region are removed by chemical mechanical polishing, whereby the semiconductor substrate 1 is removed. Exposed.

Referring to FIG. 1E, the gate oxide film 8 is formed on the exposed semiconductor substrate 1, the gate electrode 9 is formed on the gate oxide film 8, and the semiconductor substrate under the gate oxide film 8 is formed. 1) A source / drain junction region 10 is formed in the region by impurity ion implantation using the gate electrode 9 as an ion implantation mask.

However, in the prior art as described above, an SOG film is used to fill the trench, which degrades the characteristics of the gate oxide film due to decomposition of organic matter contained in the SOG film during the thermal process for forming the gate oxide film. There was this.

Accordingly, the present invention forms an insulating film having a high dielectric constant on the inner wall of the trench and surrounds the SOG film by the insulating film, thereby preventing deterioration of the characteristics of the gate oxide film caused by the SOG film, thereby improving the insulating properties of the semiconductor device. An object of the present invention is to provide a method for forming a device isolation film of a semiconductor device.

1A to 1E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views for explaining a device isolation film forming method of a semiconductor device according to the present invention.

3A to 3G are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with a second embodiment of the present invention.

4A to 4G are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with a third embodiment of the present invention.

Explanation of symbols for main parts of the drawings

11, 31, 51: semiconductor substrate 12, 32, 52: N well

13, 33, 53: P-well 14, 34, 56: photosensitive film pattern

15, 35, 57: trench 16, 58: thermal oxide film

17: Ta ₂ O ₅ film 18, 37, 59: SOG film

19, 38: nitride oxide film 20, 39, 61: gate oxide film

21, 40, 62: gate electrodes 22, 41, 63: source / drain electrodes

36: first nitric oxide film 38: second nitric oxide film

54: pad oxide film 55: polysilicon film

58 ': modified nitric oxide film 60: plasma assisted nitric oxide film

The above object is provided with a semiconductor substrate having N wells and P wells, each having a photoresist pattern formed thereon; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Sequentially forming a thermal oxide film and a high dielectric constant insulating film on the whole; Depositing and curing the SOG film to fill the trench; Etching the SOG film to expose the high dielectric constant insulating film; Forming a nitric oxide film on the entire upper portion; Etching the nitride oxide film and the high dielectric constant film to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate.

In addition, the above object is provided with an N well and a P well, the step of providing a semiconductor substrate having a photosensitive film pattern formed thereon; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Forming a first nitric oxide film over the entire surface; Depositing and curing the SOG film to fill the trench; Etching the SOG film to expose the first nitric oxide film; Forming a second nitric oxide film over the entire surface; Etching the first and second nitric oxide films to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate.

In addition, the above object is to provide a semiconductor substrate having N well and P well; Sequentially forming a pad oxide film, a polysilicon film, and a photoresist pattern on the entire top; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Forming a thermal oxide film over the entire surface; Depositing and curing the SOG film to fill the trench; Implanting impurities over the entire top; Etching the SOG film to expose the polysilicon film; Removing the polysilicon film and the pad oxide film; Forming a plasma assisted nitric oxide film over the entire surface; High temperature heat treatment; Etching the plasma assisted nitric oxide layer to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate.

According to the present invention, by blocking the exposure of the SOG film with the insulating film having a high dielectric constant, it is possible to prevent the deterioration of the characteristics of the gate oxide film due to decomposition of organic matter in the SOG film.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to FIGS. 2A to 2G.

Referring to FIG. 2A, N wells 12 and P wells 13 are formed in the semiconductor substrate 11 by known ion implantation methods, and photoresist patterns 14 are formed on the N wells 12 and P wells 13, respectively. ) Is formed.

Referring to FIG. 2B, the semiconductor substrate 11 is etched by an etching process using the photoresist pattern 14 as an etch mask, thereby forming a trench 15 having a depth of about 3,000 to 10,000 m.

Referring to FIG. 2C, the photosensitive film pattern 14 is removed, a thermal oxide film 16 having a thickness of about 100 to 300 Å is formed on the entire upper portion, and Ta (OCH ₂ CH ₃ ) ₅ and the upper portion of the thermal oxide film 16 are formed. A Ta ₂ O ₅ film 17 is formed using O ₂ gas having a high dielectric constant of about 100 to 300 GPa in a temperature range of about 400 to 600 ° C., and the Ta ₂ O ₅ film 17 is UV-O. ₃ and dry O ₂ . After looping, an SOG film 18 of about 3,000 to 6,000 microns thick is applied on the Ta ₂ O ₅ film l7 so that the trench 15 is completely buried, and the SOG film 18 is about 400 to 450 캜. And curing for about 1 hour in a nitrogen atmosphere.

Referring to FIG. 2D, a chemical mechanical polishing process is performed until the Ta ₂ O ₅ film 17 is exposed, thereby removing the SOG film 18 in the remaining region except for the trench l5. At this time, the Ta ₂ O ₅ film 17 serves as a polishing stop layer.

Referring to FIG. 2E, a nitride oxide film 19 having a thickness of about 300 to 1,000 Å is formed on the whole.

Referring to FIG. 2F, in order to expose the semiconductor substrate 11 between the trenches 15, the nitride oxide layer 19, the Ta ₂ O ₅ layer 17, and the thermal oxide layer 16 are formed on the active region by photolithography. Is removed.

Referring to FIG. 2G, the gate oxide film 20 is formed on the exposed semiconductor substrate 11, the gate electrode 21 is formed on the gate oxide film 20, and the semiconductor substrate under the gate oxide film 20 ( 11) A source / drain junction region 22 is formed in the region by impurity ion implantation using the gate electrode 2l as an ion implantation mask.

Another embodiment of the present invention will be described with reference to FIGS. 3A to 3G.

Referring to FIG. 3A, N wells 32 and P wells 33 are formed in the semiconductor substrate 31 by known ion implantation methods, and photoresist patterns 34 are formed on the N wells 12 and P wells 33, respectively. ) Is formed.

Referring to FIG. 3B, the semiconductor substrate 31 is etched by an etching process using the photoresist pattern 34 as an etching mask, thereby forming trenches 35 having a depth of about 3,000 to 10,000 Å.

Referring to FIG. 3C, the photoresist pattern 34 is removed, a first nitric oxide film 36 having a thickness of about 300 to 1,000 Å is formed on the entire upper portion, and then the first vagina is filled so that the trench 35 is completely buried. An SOG film 37 having a thickness of about 3,000 to 6,000 Å is applied onto the oxide film 36, and the SOG film 37 is cured for about 1 hour in a nitrogen atmosphere at about 400 to 450 캜.

Referring to FIG. 3D, a chemical mechanical polishing process is performed until the first nitric oxide film 36 is exposed, thereby removing the SOG film 37 in the remaining regions except for the trench 15. In this case, the first nitric oxide layer 36 serves as a polishing stop layer.

Referring to FIG. 3E, a second nitrification film 19 having a thickness of about 300 to 1,000 Å is formed on the entire upper portion.

Referring to FIG. 3F, in order to expose the semiconductor substrate 31 between the trenches 35, the second nitride oxide layer 38 and the first nitride oxide layer 36 on the active region are removed by photolithography.

Referring to FIG. 3G, the gate oxide film 39 is formed on the exposed semiconductor substrate 31, the gate electrode 40 is formed on the gate oxide film 39, and the semiconductor substrate under the gate oxide film 38 is formed. The source / drain junction region 41 is formed in the region 31 by impurity ion implantation using the gate electrode 40 as an ion implantation mask.

Another embodiment of the present invention will be described with reference to FIGS. 4A to 4G.

Referring to FIG. 4A, N wells 52 and P wells 53 are formed in the semiconductor substrate 51 by a known ion implantation method, and the pad oxide film 54 having a thickness of about 200 to 300 microseconds is formed on the entire upper surface thereof. The polysilicon film 55 and the photosensitive film pattern 56 having a thickness of 500 Å are sequentially formed.

Referring to FIG. 4B, the semiconductor substrate 51 is etched by an etching process using the photoresist pattern 56 as an etching mask, thereby forming trenches 57 having a depth of about 3,000 to 10,000 Å.

Referring to FIG. 4C, the photoresist pattern 56 is removed, a thermal oxide film 58 having a thickness of about 300 to 1,000 에 is formed on the entire upper portion, and a predetermined portion of the thermal oxide film 58 is completely embedded in the trench 57. A thick SOG film 59 is applied and cured. Then, nitrogen atoms are injected into the entire upper portion at about 1 × 10 ¹² to 1 × 10 ¹⁸ atoms / cm ³ and about 50 to 150 KeV. At this time, the ion-implanted nitrogen atoms are mainly present in the thermal oxide film 58, but some are present in the SOG film 59.

Referring to FIG. 4D, an etch back process is performed to expose the polysilicon film, thereby removing the SOG film 59 in the remaining region except for the trench 57. As shown in FIG.

4E, subsequently, an etch back process is performed, whereby the SOG film 59 is excessively etched slightly lower than the pad oxide film 54. As shown in FIG.

Referring to FIG. 4F, the polysilicon film 55 and the pad oxide film 54 are removed, respectively, and the plasma assisted nitride film 60 having a thickness of about 300 to 1,000 Å is formed on the entire top. In this case, the plasma assisted nitric oxide layer 60 is formed to have the same height h as the exposed semiconductor substrate 41. Then, a high temperature heat treatment of about 900 ° C. or higher is performed in an N ₂ atmosphere. As a result, the thermal oxide film 58 is changed into a nitrification film 58 to form a modified nitric oxide film 58 ', and the SOG film 59' is formed. Cures. Next, in order to expose the semiconductor substrate 51 between the trenches 57, the plasma assisted nitric oxide layer 60 on the active region is removed by photolithography.

Referring to FIG. 4G, the gate oxide layer 61 is formed on the exposed semiconductor substrate 51, the gate electrode 62 is formed on the gate oxide layer 61, and the semiconductor substrate under the gate oxide layer 61 is formed. A source / drain junction region 63 is formed in the region 51 by impurity ion implantation using the gate electrode 62 as an ion implantation mask.

As described above, the device isolation film forming method of the semiconductor device of the present invention can improve the insulation characteristics of the semiconductor device by forming a device isolation film of a triple film structure when forming a trench type device isolation film.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (24)

Providing a semiconductor substrate having N wells and P wells, each having a photoresist pattern formed thereon; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Sequentially forming a thermal oxide film and a high dielectric constant insulating film on the whole; Depositing and curing the SOG film to fill the trench; Etching the SOG film to expose the high dielectric constant insulating film; Forming a nitric oxide layer on the whole; Etching the nitride oxide film and the high dielectric constant insulating film to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate. The method of claim 1, wherein the high dielectric constant insulating film is a Ta ₂ O ₅ film. 3. The semiconductor of claim 2, wherein the Ta ₂ O ₅ film is formed to have a thickness of about 100 to 300 kPa in a temperature range of about 400 to 600 ° C. using Ta (OCH ₂ CH ₃ ) ₅ and O ₂ gases. A device isolation film formation method of a device. The method of claim 3, wherein the Ta ₂ O ₅ film is heat-treated with UV-O ₃ and dry O ₂ . The method of claim 1, wherein the thickness of the high dielectric constant insulating film is the same as that of the thermal oxide film. 6. The method of claim 5, wherein the high dielectric constant insulating film has a thickness of about 100 to 300 GPa. 6. The method of claim 5 wherein the SOG film is formed to a thickness of about 3,000 to 6,000 microns. The method of claim 7, wherein the SOG film is cured in a nitrogen atmosphere and at a temperature of about 400 to 450 ° C. for about 1 hour. The method of claim 1, wherein the nitride oxide film is formed to a thickness of about 300 to 1,000 Å. The method of claim 1, wherein the etching method of the nitric oxide film and the high dielectric constant insulating film to expose the semiconductor substrate region is a chemical mechanical polishing method. Providing a semiconductor substrate having N wells and P wells, each having a photoresist pattern formed thereon; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Forming a first nitric oxide film over the entire surface; Depositing and curing the SOG film to fill the trench; Etching the SOG film to expose the first nitric oxide film; Forming a second nitric oxide film over the entire surface; Etching the first and second nitric oxide films to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate. 12. The method of claim 11, wherein the SOG film is formed to a thickness of about 3,000 to 6,000 microns. The method of claim 12, wherein the SOG film is cured in a nitrogen atmosphere and at a temperature of about 400 to 450 ° C. for about 1 hour. 12. The method of claim 11, wherein the first and second nitric oxide layers are formed to a thickness of about 300 to 1,000 microns. 12. The method of claim 11, wherein the etching method of the first and second nitric oxide films for exposing the semiconductor substrate region is a chemical mechanical polishing method. Providing a semiconductor substrate having N wells and P wells; Sequentially forming a pad oxide film, a polysilicon film, and a photoresist pattern on the entire top; Performing an etching process using the photoresist pattern as an etching mask to form trenches in a predetermined region of the semiconductor substrate; Removing the photoresist pattern; Forming a thermal oxide film over the whole; Depositing and curing the SOG film to fill the trench; Implanting impurities into the entire upper portion; Etching the SOG film to expose the polysilicon film; Removing the polysilicon film and the pad oxide film; Forming a plasma assisted nitric oxide film over the entire surface; High temperature heat treatment; Etching the plasma assisted nitric oxide layer to expose the semiconductor substrate region between the trenches; And forming a gate oxide film, a gate electrode, and a source / drain electrode on the exposed semiconductor substrate. 17. The method of claim 16, wherein the pad oxide film is formed to a thickness of about 200 to 300 microns. 17. The method of claim 16, wherein the polysilicon film is formed to a thickness of about 200 to 500 microns. 17. The method of claim 16, wherein the impurity is nitrogen. 20. The method of claim 19, wherein the nitrogen atom is implanted at about 1 × 10 ¹² to 1 × 10 ¹⁸ atoms / cm ³ and about 50 to 150 KeV. 20. The method of claim 19, wherein the nitrogen atom is present in the thermal oxide film. 20. The method of claim 19, wherein the nitrogen atom is present in the SOG film. 17. The method of claim 16, wherein the plasma assisted nitric oxide film is formed to a thickness of about 300 to l, 000 kPa. The method of claim 16, wherein the high temperature heat treatment is performed at about 900 ° C. or higher in an N ₂ atmosphere.