CN210142652U - Shallow trench isolation structure and semiconductor device - Google Patents
Shallow trench isolation structure and semiconductor device Download PDFInfo
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- CN210142652U CN210142652U CN201921620570.5U CN201921620570U CN210142652U CN 210142652 U CN210142652 U CN 210142652U CN 201921620570 U CN201921620570 U CN 201921620570U CN 210142652 U CN210142652 U CN 210142652U
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Abstract
The utility model discloses a shallow trench isolation structure and semiconductor device, include: a substrate having a top; at least one groove is positioned on one side of the top of the substrate; the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape. According to the above, the utility model provides a technical scheme, the edge that the substrate corresponds the top of slot is the cambered surface for the edge that the substrate corresponds the top of slot does not have precipitous closed angle and more slick and sly, and then can improve shallow trench isolation structure's point-to-point discharge problem, improves shallow trench isolation structure's reliability.
Description
Technical Field
The utility model relates to a semiconductor device technical field, more specifically say, relate to a shallow trench isolation structure and semiconductor device.
Background
With the continuous development of semiconductor manufacturing processes, the requirements for device Isolation performance are higher and higher, and Shallow Trench Isolation (STI) technology is developed; namely, a shallow trench isolation structure is manufactured in the isolation device for isolation, and an insulator is filled in the shallow trench isolation structure to achieve the purpose of insulating the device to be isolated. In the manufacturing process of the semiconductor chip, the shallow trench isolation structure plays a very important role, and is widely applied to high-density semiconductor devices such as deep submicron devices, memories and the like due to the high-density isolation. Although the shallow trench isolation structure has many advantages, the reliability of the conventional shallow trench isolation structure needs to be improved.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a shallow trench isolation structure and semiconductor device has effectively solved the technical problem that prior art exists, has improved shallow trench isolation structure's point discharge problem, has improved shallow trench isolation structure's reliability.
In order to achieve the above purpose, the utility model provides a technical scheme as follows:
a shallow trench isolation structure comprising:
a substrate having a top;
at least one groove is positioned on one side of the top of the substrate;
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape.
Optionally, the shallow trench isolation structure further includes:
a fourth dielectric layer is along an inner wall of the first recess.
Optionally, the fourth dielectric layers adjacent to the trench are communicated with each other and cover the surface of the top side of the substrate.
Optionally, at the first groove, the shallow trench isolation structure further includes:
and the fifth dielectric layer is positioned in the inner wall groove of the fourth dielectric layer.
Optionally, the material of the fifth dielectric layer is the same as the material of the second dielectric layer.
Optionally, the shallow trench isolation structure further includes:
and the polycrystalline silicon layer is positioned on one side of the fourth dielectric layer, which is far away from the substrate, wherein the material of the fifth dielectric layer is the same as that of the polycrystalline silicon layer.
Optionally, the top of the third dielectric layer has a recess, and the bottom of the recess of the third dielectric layer is lower than the top of the second dielectric layer.
Correspondingly, the utility model also provides a semiconductor device, semiconductor device includes:
a substrate having a top;
at least one groove is positioned on one side of the top of the substrate;
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape.
Optionally, the semiconductor device further includes:
a fourth dielectric layer is along an inner wall of the first recess.
Optionally, the fourth dielectric layers adjacent to the trench are communicated with each other and cover the surface of the top side of the substrate.
Optionally, at the first groove, the semiconductor device further includes:
and the fifth dielectric layer is positioned in the inner wall groove of the fourth dielectric layer.
Optionally, the material of the fifth dielectric layer is the same as the material of the second dielectric layer.
Optionally, the semiconductor device further includes:
and the polycrystalline silicon layer is positioned on one side of the fourth dielectric layer, which is far away from the substrate, wherein the material of the fifth dielectric layer is the same as that of the polycrystalline silicon layer.
Optionally, the polysilicon layer extends to cover the top of the second dielectric layer and a part of the top of the third dielectric layer.
Optionally, a surface of the polysilicon layer corresponding to the trench is lower than a surface corresponding to the top of the substrate.
Optionally, the polysilicon layers adjacent to the trench are communicated with each other and cover the top corresponding region of the substrate.
Optionally, the top of the third dielectric layer has a recess, and the bottom of the recess of the third dielectric layer is lower than the top of the second dielectric layer.
Optionally, a stacked structure of at least a first circuit layer, a second circuit layer and a hard mask layer stacked in sequence is located on a surface of one side of the semiconductor device, where the trench is located, and the stacked structure has a hollow-out region exposing at least a portion of the top of the third dielectric layer.
Optionally, the surface of the first circuit layer corresponding to the groove is lower than the surface corresponding to the top of the substrate;
and the surface of one side of the hard mask layer, which is far away from the substrate, is coplanar.
Compared with the prior art, the utility model provides a technical scheme has following advantage at least:
the utility model provides a shallow trench isolation structure and semiconductor device, include: a substrate having a top; at least one groove is positioned on one side of the top of the substrate; the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape. According to the above, the utility model provides a technical scheme, the edge that the substrate corresponds the top of slot is the cambered surface for the edge that the substrate corresponds the top of slot does not have precipitous closed angle and more slick and sly, and then can improve shallow trench isolation structure's point-to-point discharge problem, improves shallow trench isolation structure's reliability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shallow trench isolation structure according to an embodiment of the present disclosure;
fig. 2 is a schematic structural view of another shallow trench isolation structure provided in the present embodiment;
fig. 3 is a schematic structural diagram of another shallow trench isolation structure provided in the present embodiment;
fig. 4 is a schematic structural diagram of another shallow trench isolation structure provided in the present embodiment;
fig. 5 is a schematic structural diagram of another shallow trench isolation structure provided in the present embodiment;
fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As described in the background, shallow trench isolation structures play a significant role in the fabrication of semiconductor chips, and are widely used in high-density semiconductor devices such as deep submicron devices and memories due to their high-density isolation. Although the shallow trench isolation structure has many advantages, the reliability of the conventional shallow trench isolation structure needs to be improved.
Based on this, the embodiment of the application provides a shallow trench isolation structure and a semiconductor device, which effectively solve the technical problems existing in the prior art, improve the point discharge problem of the shallow trench isolation structure, and improve the reliability of the shallow trench isolation structure. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 8.
Referring to fig. 1, a schematic structural diagram of a shallow trench isolation structure provided in an embodiment of the present application is shown, where the shallow trench isolation structure includes:
a substrate 100 having a top;
at least one trench 110 located on a top side of the substrate 100;
a first dielectric layer 210, a second dielectric layer 220 and a third dielectric layer 230 are sequentially arranged along the inner wall of the groove 110, wherein the top of the first dielectric layer 210 is lower than the top of the second dielectric layer 220 and the top of the substrate 100, so that a first groove 211 is formed between the second dielectric layer 220 and the substrate 100, and the edge corner of the substrate 100 corresponding to the top of the groove 110 is an arc surface 120.
In an embodiment of the application, when the shallow trench isolation structure is manufactured, a first dielectric layer and a second dielectric layer with flush tops can be formed, and then the top of the first dielectric layer is etched to form a first groove; and the edge angle of the top of the groove corresponding to the substrate can be additionally etched while the first dielectric layer is etched, so that the first groove and the cambered surface structure of the edge angle of the top of the groove corresponding to the substrate are formed simultaneously, the manufacturing process can be simplified, and the manufacturing cost is reduced.
It should be noted that the arc structure of the edge angle of the substrate corresponding to the top of the trench is not limited to the above manufacturing process, and in other embodiments of the present application, the arc structures of the first groove and the edge angle of the substrate corresponding to the top of the trench may also be manufactured separately.
In an embodiment of the present application, the top of the first dielectric layer 210, the second dielectric layer 220, and the third dielectric layer 230 provided herein are lower than the top of the substrate 100, and the present application is not particularly limited thereto.
According to the technical scheme, the edge of the substrate corresponding to the top of the groove is an arc surface, so that the edge of the substrate corresponding to the top of the groove is free of steep sharp corners and is smooth, the point discharge problem of the shallow trench isolation structure at the edge of the top of the substrate can be improved, and the reliability of the shallow trench isolation structure is improved.
Optionally, the substrate provided in this embodiment of the present application may be a silicon substrate, the first dielectric layer may be an oxide dielectric layer, the second dielectric layer may be a nitride dielectric layer, and the third dielectric layer may be an oxide dielectric layer, which is not particularly limited in this application.
Referring to fig. 2, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, where the shallow trench isolation structure provided in the embodiment of the present application further includes:
along the inner walls of the first recess 211 is a fourth dielectric layer 240.
It can be understood that, in the shallow trench isolation structure provided in the embodiment of the present application, the fourth dielectric layer is further formed along the inner wall of the first groove, and the first groove is located at the edge corner of the top of the trench corresponding to the substrate, so that an overlapping region is formed at the edge corner of the top of the trench corresponding to the fourth dielectric layer and the edge corner of the top of the trench corresponding to the substrate, so that the fourth node layer at least covers part of the edge corner of the top of the trench corresponding to the substrate, thereby further improving the problem of tip discharge of the shallow trench isolation structure at the edge of the top of the substrate, and improving the reliability of the shallow trench.
Further, referring to fig. 3, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, wherein the fourth dielectric layers 240 adjacent to the trenches 110 are connected and cover the surface of the top side of the substrate 100.
In an embodiment of the present application, the material of the fourth dielectric layer provided in the present application may be a gate oxide layer, and the present application is not particularly limited; in other embodiments of the present application, the fourth dielectric layer may also be polysilicon.
It can be understood that, when the fourth dielectric layer is manufactured in the first groove, the surface of one side of the top of the substrate between the adjacent grooves is covered by the fourth dielectric layer, and further, the surface of one side of the top of the substrate is not required to be covered by independently manufacturing the dielectric layer again, so that the manufacturing process of the shallow trench isolation structure is simplified, and the manufacturing cost is reduced.
It should be noted that, in other embodiments of the present application, the fourth dielectric layer and the dielectric layer on the top surface of the substrate may be separately manufactured, and the present application is not particularly limited, and a specific process design is required according to practical applications.
Referring to fig. 4, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, where at the first groove 211, the shallow trench isolation structure further includes:
and a fifth dielectric layer 250 positioned in the inner wall recess of the fourth dielectric layer 240.
In an embodiment of the present application, a material of the fifth dielectric layer and a material of the second dielectric layer provided in the present application may be the same, and the present application is not limited thereto.
Alternatively, referring to fig. 5, a schematic structural diagram of another shallow trench isolation structure provided in an embodiment of the present application is shown, where the shallow trench isolation structure further includes:
and the polysilicon layer 300 is positioned on the side of the fourth dielectric layer 240, which faces away from the substrate, wherein the material of the fifth dielectric layer 250 is the same as that of the polysilicon layer 300.
It can be understood that the shallow trench isolation structure provided in the embodiment of the present application includes a polysilicon layer located on a side of the fourth dielectric layer away from the substrate, wherein the polysilicon layer has a hollow area corresponding to the third dielectric layer to expose a top portion of the third dielectric layer. The fifth dielectric layer and the polysilicon layer provided by the embodiment of the application are made of the same material, and the inner wall groove of the fourth dielectric layer can be filled to obtain the fifth dielectric layer while the polysilicon layer is manufactured, so that the fifth dielectric layer and the polysilicon layer are manufactured simultaneously, the manufacturing process of the shallow trench isolation structure is simplified, and the manufacturing cost is reduced.
It should be noted that, in other embodiments of the present application, when the material of the fifth dielectric layer is the same as that of the polysilicon layer, the fifth dielectric layer and the polysilicon layer may also be separately manufactured, and the present application is not limited specifically.
In an embodiment of the present application, as shown in fig. 1 to 5, a top of the third dielectric layer 230 provided in the embodiment of the present application has a recess, and a bottom of the recess of the third dielectric layer 230 is lower than a top of the second dielectric layer 220.
Correspondingly, the embodiment of the present application further provides a semiconductor device, and the semiconductor device provided in the embodiment of the present application may be a semiconductor memory or the like, and the present application is not particularly limited thereto. Specifically, referring to fig. 1, the semiconductor device provided in the embodiment of the present application includes the shallow trench isolation structure provided in any one of the above embodiments, and the semiconductor device provided in the embodiment of the present application includes:
a substrate 100 having a top;
at least one trench 110 located on a top side of the substrate 100;
a first dielectric layer 210, a second dielectric layer 220 and a third dielectric layer 230 are sequentially arranged along the inner wall of the groove 110, wherein the top of the first dielectric layer 210 is lower than the top of the second dielectric layer 220 and the top of the substrate 100, so that a first groove 211 is formed between the second dielectric layer 220 and the substrate 100, and the edge corner of the substrate 100 corresponding to the top of the groove 110 is an arc surface 120.
In an embodiment of the present application, when manufacturing a shallow trench isolation structure in a semiconductor device, a first dielectric layer and a second dielectric layer with flush tops may be formed, and then, the top of the first dielectric layer is etched to form a first groove; and the edge angle of the top of the groove corresponding to the substrate can be additionally etched while the first dielectric layer is etched, so that the first groove and the cambered surface structure of the edge angle of the top of the groove corresponding to the substrate are formed simultaneously, the manufacturing process can be simplified, and the manufacturing cost is reduced.
It should be noted that the arc structure of the edge angle of the substrate corresponding to the top of the trench is not limited to the above manufacturing process, and in other embodiments of the present application, the arc structures of the first groove and the edge angle of the substrate corresponding to the top of the trench may also be manufactured separately.
In an embodiment of the present application, the top of the first dielectric layer 210, the second dielectric layer 220, and the third dielectric layer 230 provided herein are lower than the top of the substrate 100, and the present application is not particularly limited thereto.
According to the technical scheme provided by the embodiment of the application, the edge of the substrate corresponding to the top of the groove is an arc surface, so that the edge of the substrate corresponding to the top of the groove is free of steep sharp corners and is smooth, the point discharge problem of the shallow trench isolation structure in the semiconductor device at the edge of the top of the substrate can be improved, and the reliability of the shallow trench isolation structure is improved.
Optionally, the substrate provided in this embodiment of the present application may be a silicon substrate, the first dielectric layer may be an oxide dielectric layer, the second dielectric layer may be a nitride dielectric layer, and the third dielectric layer may be an oxide dielectric layer, which is not particularly limited in this application.
Referring to fig. 2, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, where the semiconductor device provided in the embodiment of the present application further includes:
along the inner walls of the first recess 211 is a fourth dielectric layer 240.
It can be understood that, in the shallow trench isolation structure in the semiconductor device provided in the embodiment of the present application, the fourth dielectric layer is further formed along the inner wall of the first groove, and because the first groove is located at the edge corner of the top of the trench corresponding to the substrate, an overlapping region is formed at the edge corner of the top of the trench corresponding to the fourth dielectric layer and the substrate, so that the fourth node layer at least partially covers the edge corner of the top of the trench corresponding to the substrate, thereby further improving the problem of tip discharge of the shallow trench isolation structure at the top edge of the substrate, and improving the reliability of the shallow trench isolation structure.
Further, referring to fig. 3, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, wherein the fourth dielectric layers 240 adjacent to the trenches 110 are connected and cover the surface of the top side of the substrate 100.
In an embodiment of the present application, the material of the fourth dielectric layer provided in the present application may be a gate oxide layer, and the present application is not particularly limited; in other embodiments of the present application, the fourth dielectric layer may also be polysilicon.
It can be understood that, when the fourth dielectric layer is manufactured in the first groove, the surface of one side of the top of the substrate between the adjacent grooves is covered by the fourth dielectric layer, and further, the surface of one side of the top of the substrate is not required to be covered by independently manufacturing the dielectric layer again, so that the manufacturing process of the shallow trench isolation structure in the semiconductor device is simplified, and the manufacturing cost is reduced.
It should be noted that, in other embodiments of the present application, the fourth dielectric layer and the dielectric layer on the top surface of the substrate may be separately manufactured, and the present application is not particularly limited, and a specific process design is required according to practical applications.
Referring to fig. 4, a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application is shown, wherein at the first recess 211, the semiconductor device further includes:
and a fifth dielectric layer 250 positioned in the inner wall recess of the fourth dielectric layer 240.
As can be seen from the shallow trench isolation structure in the semiconductor device shown in fig. 4, the material of the fifth dielectric layer and the material of the second dielectric layer provided in the present application may be the same; alternatively, the fifth dielectric layer may also be made of other materials, specifically referring to fig. 5, which is a schematic structural diagram of another shallow trench isolation structure provided in the embodiment of the present application, wherein the semiconductor device further includes:
and the polysilicon layer 300 is positioned on the side of the fourth dielectric layer 240, which faces away from the substrate, wherein the material of the fifth dielectric layer 250 is the same as that of the polysilicon layer 300.
It can be understood that the shallow trench isolation structure in the semiconductor device provided in the embodiment of the present application includes a polysilicon layer located on a side of the fourth dielectric layer facing away from the substrate, wherein the polysilicon layer provided in the embodiment of the present application may extend to cover the top of the second dielectric layer and the top of the third dielectric layer. That is, the polysilicon layer provided in the embodiment of the present application covers the top of the second dielectric layer, and the polysilicon layer has a hollow area corresponding to the third dielectric layer to cover a portion of the top of the third dielectric layer and to expose another portion of the top of the third dielectric layer (the exposed portion may correspond to the central area of the third dielectric layer). The fifth dielectric layer and the polysilicon layer provided by the embodiment of the application are made of the same material, and the inner wall groove of the fourth dielectric layer can be filled to obtain the fifth dielectric layer while the polysilicon layer is manufactured, so that the fifth dielectric layer and the polysilicon layer are manufactured simultaneously, the manufacturing process of the shallow trench isolation structure is simplified, and the manufacturing cost is reduced.
In an embodiment of the present application, the polysilicon layer provided by the present application may be a layer structure with a uniform thickness, that is, as shown in fig. 5, the surface of the polysilicon layer 300 provided by the embodiment of the present application corresponding to the trench 110 is lower than the surface corresponding to the top of the substrate 100.
It should be noted that, in other embodiments of the present application, when the material of the fifth dielectric layer is the same as that of the polysilicon layer, the fifth dielectric layer and the polysilicon layer may also be separately manufactured, and the present application is not limited specifically.
In an embodiment of the present application, the position of the shallow trench isolation structure in the semiconductor device is not specifically limited, where the position of the shallow trench isolation structure in the semiconductor device is different, and the corresponding structure at the position of the shallow trench isolation structure is also different. That is, the surface of the semiconductor device on the side having the trench provided by the embodiment of the present application has a functional film layer, and the functional film layer may be a stacked structure; that is, the functional film layer may be located on a surface of the fourth dielectric layer facing away from the substrate, and the functional film layer may also be located on a surface of the polysilicon layer facing away from the substrate, which is not limited in this application. Specifically, in the technical solution provided in the embodiment of the present application, the semiconductor device may have a stacked structure of a first circuit layer, a second circuit layer, and a hard mask layer, which may be at least sequentially stacked on a surface of one side of the trench, where the stacked structure has a hollow area exposing at least a portion of a top of the third dielectric layer.
The technical solution provided by the present application is specifically described below with the functional film layer located on the surface of the polysilicon layer on the side away from the substrate. As shown in fig. 6, which is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure, when a polysilicon layer 300 is disposed on a side of the fourth dielectric layer 240 of the shallow trench isolation structure away from the substrate, a functional film 400 is further formed on the side of the polysilicon layer 300 away from the substrate 100, wherein a hollow area is formed at a position of the functional film 400 corresponding to the third dielectric layer 230.
It is understood that, as shown in fig. 6, the fourth dielectric layer 240 of the adjacent trench 110 provided in the embodiment of the present application may communicate with and cover the surface of the top side of the substrate 100, and the polysilicon layer 300 of the adjacent trench 110 provided in the embodiment of the present application communicates with and covers the corresponding region of the top of the substrate 100. That is, the polysilicon layer 300 provided in the embodiment of the present application may cover the fourth dielectric layer 240 and extend to cover the top of the third dielectric layer 230 in the adjacent trench 110, and the polysilicon layer 300 has a hollow area corresponding to the third dielectric layer 230. And, the functional film 400 provided in the embodiment of the present application is located on a side of the polysilicon layer 300 away from the substrate 100, wherein the functional film 400 may cover the polysilicon layer 300, and the functional film 400 has a hollow area corresponding to the third dielectric layer 230, that is, the functional film 400 may cross two adjacent trenches 110 to connect the two adjacent trenches 110. In an embodiment of the present application, the shallow trench isolation structures provided in the present application are located at different positions in the semiconductor device, and the structures of the functional film layers are different. The side, away from the substrate, of the polycrystalline silicon layer provided in the embodiment of the present application is provided with at least a first circuit layer, a second circuit layer and a hard mask layer which are sequentially stacked, wherein the first circuit layer, the second circuit layer and the hard mask layer have hollow areas which are the same as the polycrystalline silicon layer. That is, as shown in fig. 7, a schematic structural diagram of another semiconductor device provided in the embodiment of the present application is provided, wherein the functional film layer provided in the embodiment of the present application may at least include a first line layer 410, a second line layer 420, and a hard mask layer 430, which are sequentially stacked from a polysilicon layer 300. The first circuit layer 410 provided in the embodiment of the present disclosure may be made of, but not limited to, titanium or titanium nitride, the second circuit layer 420 may be made of metal (e.g., tungsten), and the hard mask layer 430 may be made of, but not limited to, nitride.
In an embodiment of the present application, a surface of the first circuit layer passing through the present application corresponding to the trench is lower than a surface corresponding to the top of the substrate; and the surface of one side of the hard mask layer, which is far away from the substrate, is coplanar.
It can be understood that, as shown in fig. 7, the polysilicon layer 300 provided in the embodiment of the present application has a uniform thickness, and since the first dielectric layer 210, the second dielectric layer 220 and the third dielectric layer 230 have a lower top than the top of the substrate 100 at the trench 110, the surface of the polysilicon layer 300 facing away from the substrate 100 is not planar, so that the surface of the polysilicon layer 300 facing away from the substrate 100 has a lower surface shape at the trench 110 than at the top of the substrate 100. And, since the first circuit layer 410 and the second circuit layer 420 may also be a layer structure with uniform thickness, the surface of the first circuit layer 410 and the second circuit layer 420 facing away from the substrate 100 may also be a structure with a lower surface at the trench 110 than the surface at the top of the substrate 100. And, the hard mask layer 430 provided by the embodiment of the present application may be a flat layer, and a surface of the flat layer facing away from the substrate 100 is coplanar, which is not limited in particular to the present application.
As shown in fig. 8, a schematic structural diagram of another semiconductor device provided in this embodiment of the present invention is provided, wherein the semiconductor device provided in this embodiment of the present invention may further be directly filled on a side of the fourth dielectric layer 240 away from the substrate 100 to obtain a filling layer 500, wherein a material of the filling layer 500 provided in this embodiment of the present invention includes, but is not limited to, an oxide.
It should be noted that the semiconductor device structures shown in fig. 6 to 8 are only some of the corresponding structures where the present application is applicable to the shallow trench isolation structure, and the present application is not particularly limited thereto, and the semiconductor device structures need to be specifically designed according to the type of the semiconductor device and the position of the shallow trench isolation structure in the semiconductor device.
In an embodiment of the present application, as shown in fig. 1 to 8, a top of the third dielectric layer 230 provided in the embodiment of the present application has a recess, and a bottom of the recess of the third dielectric layer 230 is lower than a top of the second dielectric layer 220.
The embodiment of the application provides a shallow trench isolation structure and a semiconductor device, comprising: a substrate having a top; at least one groove is positioned on one side of the top of the substrate; the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape. According to the technical scheme, the edge of the substrate corresponding to the top of the groove is in the arc surface, so that the edge of the substrate corresponding to the top of the groove is free of steep sharp corners and is smooth, the point discharge problem of the shallow groove isolation structure can be improved, and the reliability of the shallow groove isolation structure is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (19)
1. A shallow trench isolation structure, comprising:
a substrate having a top;
at least one groove is positioned on one side of the top of the substrate;
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape.
2. The shallow trench isolation structure of claim 1 further comprising:
a fourth dielectric layer is along an inner wall of the first recess.
3. The shallow trench isolation structure of claim 2 wherein the fourth dielectric layers adjacent to the trenches communicate and cover the top side surface of the substrate.
4. The shallow trench isolation structure of claim 2 or 3, further comprising, at the first recess:
and the fifth dielectric layer is positioned in the inner wall groove of the fourth dielectric layer.
5. The shallow trench isolation structure of claim 4 wherein the material of the fifth dielectric layer is the same as the material of the second dielectric layer.
6. The shallow trench isolation structure of claim 4, further comprising:
and the polycrystalline silicon layer is positioned on one side of the fourth dielectric layer, which is far away from the substrate, wherein the material of the fifth dielectric layer is the same as that of the polycrystalline silicon layer.
7. The shallow trench isolation structure of claim 1 wherein the top of the third dielectric layer has a recess and the bottom of the recess of the third dielectric layer is lower than the top of the second dielectric layer.
8. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate having a top;
at least one groove is positioned on one side of the top of the substrate;
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged along the inner wall of the groove, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the top of the substrate, a first groove is formed between the second dielectric layer and the substrate, and the edge angle of the substrate corresponding to the top of the groove is in an arc surface shape.
9. The semiconductor device according to claim 8, further comprising:
a fourth dielectric layer is along an inner wall of the first recess.
10. The semiconductor device of claim 9, wherein the fourth dielectric layers adjacent to the trenches communicate and cover a top-side surface of the substrate.
11. The semiconductor device according to claim 9, further comprising, at the first groove:
and the fifth dielectric layer is positioned in the inner wall groove of the fourth dielectric layer.
12. The semiconductor device according to claim 11, wherein a material of the fifth dielectric layer is the same as a material of the second dielectric layer.
13. The semiconductor device according to claim 11, further comprising:
and the polycrystalline silicon layer is positioned on one side of the fourth dielectric layer, which is far away from the substrate, wherein the material of the fifth dielectric layer is the same as that of the polycrystalline silicon layer.
14. The semiconductor device of claim 13, wherein the polysilicon layer extends over a top portion of the second dielectric layer and a portion of a top portion of the third dielectric layer.
15. The semiconductor device of claim 14, wherein a surface of the polysilicon layer corresponding to the trench is lower than a surface corresponding to a top of the substrate.
16. The semiconductor device of claim 14, wherein the polysilicon layers at adjacent trenches communicate and overlie a top corresponding region of the substrate.
17. The semiconductor device of claim 14, wherein the top of the third dielectric layer has a recess, and the bottom of the recess of the third dielectric layer is lower than the top of the second dielectric layer.
18. The semiconductor device according to any one of claims 9 to 17, wherein a stacked structure of at least a first circuit layer, a second circuit layer, and a hard mask layer stacked in this order is provided on a surface of the semiconductor device on the side having the trench, and the stacked structure has a hollow region where at least a part of a top of the third dielectric layer is exposed.
19. The semiconductor device according to claim 18, wherein a surface of the first wiring layer corresponding to the trench is lower than a surface corresponding to a top of the substrate;
and the surface of one side of the hard mask layer, which is far away from the substrate, is coplanar.
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| CN201921620570.5U CN210142652U (en) | 2019-09-26 | 2019-09-26 | Shallow trench isolation structure and semiconductor device |
| US16/696,765 US11069774B2 (en) | 2019-09-26 | 2019-11-26 | Shallow trench isolation structure and semiconductor device with the same |
| US17/349,906 US11824087B2 (en) | 2019-09-26 | 2021-06-16 | Shallow trench isolation structure and semiconductor device with the same |
| US18/380,616 US20240047519A1 (en) | 2019-09-26 | 2023-10-16 | Shallow trench isolation structure and semiconductor device with the same |
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| CN110518062A (en) * | 2019-09-26 | 2019-11-29 | 福建省晋华集成电路有限公司 | A kind of fleet plough groove isolation structure and semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110518062A (en) * | 2019-09-26 | 2019-11-29 | 福建省晋华集成电路有限公司 | A kind of fleet plough groove isolation structure and semiconductor devices |
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