TWI753670B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.

Description

semiconductor device

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor device and a manufacturing method thereof.

Recently, various three-dimensional (3D) memory devices have been provided as the demand for more superior memory devices has gradually increased. However, in order for such a 3D memory device to achieve higher storage capacity and higher performance, there is still a need to provide an improved 3D memory device and a manufacturing method thereof.

The present invention relates to a semiconductor device. Compared with the comparative example in which the channel layer is disposed outside the first conductive column and the second conductive column and surrounds the first conductive column and the second conductive column, because the channel layer of the semiconductor device of the present application is disposed between the first conductive column and the second conductive column There can be a shorter channel length between the second conductive pillars, which can not only improve the performance of the semiconductor device, but also increase the density of the chip.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes first and second conductive pillars, a channel layer, and a memory structure. The first conductive column and a second conductive column respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive column and the second conductive column, and the channel layer is coupled to the first conductive column and the second conductive column. The memory structure surrounds the first conductive column, the second conductive column and the channel layer.

According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes first and second conductive pillars, a channel layer, and a memory structure. The first conductive column and a second conductive column respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is coupled to the first conductive column and the second conductive column. The memory structure surrounds the first conductive column, the second conductive column and the channel layer. The conductive layer includes a first bottom conductive layer, and the first bottom conductive layer is disposed under the first conductive column and the second conductive column.

According to yet another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a stack is formed on a substrate. The stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. Thereafter, a plurality of memory strings are formed. The memory strings pass through the stack along a first direction, and each memory string includes first and second conductive pillars, a channel layer, and a memory structure. The first conductive column and a second conductive column respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive column and the second conductive column, and the channel layer is coupled to the first conductive column and the second conductive column. The memory structure surrounds the first conductive column, the second conductive column and the channel layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

FIG. 1A shows a top view of a semiconductor device 100 according to an embodiment of the present invention, corresponding to the plane of the line B-B' in FIG. 1B (ie, corresponding to the plane formed by the X-axis and the Y-axis). Fig. 1B shows a cross-sectional view along the line A-A' in Fig. 1A (that is, corresponding to the plane formed by the X-axis and the Z-axis). In this embodiment, the X axis, the Y axis and the Z axis are perpendicular to each other, but the present invention is not limited to this, as long as the X axis, the Y axis and the Z axis are staggered with each other.

Please refer to FIGS. 1A and 1B simultaneously, the semiconductor device 100 includes a stack ST and a plurality of memory strings MS. The trenches 138 may divide the stack ST into a plurality of sub-stacks (not shown). The semiconductor device 100 is formed on a substrate 101 . The stack ST includes a plurality of conductive layers CL and a plurality of insulating layers IL that are alternately stacked. The memory strings MS pass through the stacks ST along a first direction, respectively. The first direction is, for example, the direction of the Z axis. In detail, the conductive layer CL includes a first bottom conductive layer 105 , a second bottom conductive layer 112 and a plurality of upper conductive layers 116 sequentially stacked on the substrate 101 . The insulating layer IL includes a first bottom insulating layer 103 , a second bottom insulating layer 107 , a third bottom insulating layer 110 and a plurality of upper insulating layers 114 sequentially stacked on the substrate 101 .

Each memory string MS includes a first conductive column 118 a and a second conductive column 118 b , a channel layer 120 , an insulating column 124 , and a memory structure 122 . The first conductive pillars 118a and the second conductive pillars 118b respectively extend along the first direction and are electrically isolated from each other. The insulating pillars 124 may include a second oxide layer 146 and an oxide material 148 . The channel layer 120 and the insulating column 124 extend along the first direction and pass through the first bottom conductive layer 105 , the second bottom insulating layer 107 , the second bottom conductive layer 112 , the third bottom insulating layer 110 and other layers of the stack ST . The channel layer 120 is disposed between the first conductive pillars 118a and the second conductive pillars 118b, as shown in FIG. 1A. In FIG. 1B, the channel layer 120 extends between the insulating column 124 and the first conductive column 118a and between the insulating column 124 and the second conductive column 118b. The channel layer 120 is coupled to the first conductive pillar 118a and the second conductive pillar 118b. In addition, the channel layer 120 has an annular cross-section formed along a second direction (eg, the X-axis direction) and a third direction (eg, the Y-axis direction), as shown in FIG. 1A . For example, the second direction and the third direction are perpendicular to the first direction (though the present invention is not limited thereto). In detail, the channel layer 120 has an annular inner surface 120n and an annular outer surface 120t, and the first conductive pillars 118a and the second conductive pillars 118b are coupled to the annular outer surface 120t. The insulating pillar 124 is connected to the annular inner surface 120n of the channel layer 120 . In other words, the first conductive pillars 118 a and the second conductive pillars 118 b are disposed outside the channel layer 120 and not disposed inside the channel layer 120 . In this embodiment, the cross section of the channel layer 120 is circular, however, the present invention is not limited to this, and the cross section of the channel layer 120 may be oval or other suitable shapes.

In FIG. 1A , the first conductive column 118 a is coupled to the first position C1 of the channel layer 120 , and the second conductive column 118 b is coupled to the second position C2 of the channel layer 120 . The first position C1 and the second position C2 are opposed to each other along the second direction, for example. On the extension line between the first position C1 and the second position C2 (for example, passing through the center point of the insulating column 124 ), the channel layer 120 forms a first width W1 (for example, the maximum width), which is formed by the first conductive The widths formed by the pillars 118a to the second conductive pillars 118b are a second width W2 (eg, a maximum width), and the second width W2 is greater than the first width W1. In some embodiments, the first width W1 formed by the channel layer 120 may be referred to as the channel length. Compared with the comparative example in which the channel layer surrounds the first conductive column and the second conductive column, since the channel layer 120 is disposed between the first conductive column 118a and the second conductive column 118b in the embodiment of the present application, the channel layer 120 The volume occupied is small, and the length of the formed channel can be short, so the density of the chip can be increased, and the semiconductor device can achieve better performance. The first conductive column 118a and the second conductive column 118a are respectively in contact with the channel layer 120 to form two contact areas, and the size of the contact areas can be adjusted according to requirements. In some embodiments, the first conductive pillar 118a and the second conductive pillar 118b contact opposite sides of the channel layer 120 along the second direction.

In FIG. 1B , the first bottom conductive layer 105 is disposed under the first conductive pillars 118 a and the second conductive pillars 118 b , and the first bottom conductive layer 105 surrounds a bottom portion of the channel layer 120 . The conductive layer CL located on the first bottom conductive layer 105 (ie, the second bottom conductive layer 112 and the upper conductive layer 116 ) surrounds the first conductive column 118 a and the second conductive column 118 b. In the first direction, the first bottom conductive layer 105 overlaps the first conductive pillars 118a and the second conductive pillars 118b. The first bottom conductive layer 105 surrounds the bottom of the channel layer 120 . In the second direction, the length L1 of the first bottom conductive layer 105 is greater than the length L2 of the second bottom conductive layer 112 disposed on the first bottom conductive layer 105 . In the second direction, the length L1 of the first bottom conductive layer 105 is greater than the length L3 of the upper conductive layer 116 . The first bottom insulating layer 103 is disposed between the substrate 101 and the first bottom conductive layer 105, the second bottom insulating layer 107 is disposed between the first bottom conductive layer 105 and the first conductive pillar 118a, and the first bottom conductive layer 105 and the between the second conductive pillars 118b. In FIG. 1B , a bottom surface of the bottom structure 18 a of the first conductive pillar 118 a is substantially coplanar with a bottom surface of the second bottom conductive layer 112 .

In FIG. 1A , the memory structure 122 surrounds a portion of the first conductive pillar 118 a , a portion of the second conductive pillar 118 b , and a portion of the channel layer 120 . In the cross section of the second direction and the third direction, the memory structure 122 is conformal to the first conductive pillar 118a, the second conductive pillar 118b and the channel layer 120, as shown in FIG. 1A. In FIG. 1B, a part of the memory structure 122 extends along the first direction (eg, the Z direction), and a part of the memory structure 122 extends along the second direction (eg, the X direction), so that the memory structure 122 surrounds The second bottom conductive layer 112 and the upper conductive layer 116 . The insulating pillar 124 is located in the central region of the memory string MS. The channel layer 120 surrounds the insulating pillars 124 , that is, the channel layer 120 extends between the insulating pillars 124 and the first conductive pillars 118 a and between the insulating pillars 124 and the second conductive pillars 118 b along the first direction.

In some embodiments, the substrate 101 is, for example, a dielectric layer (eg, a silicon oxide layer). The insulating layer IL can be, for example, a silicon oxide layer, and the silicon oxide layer, for example, includes silicon dioxide. The material of the insulating pillar 124 is, for example, oxide, and the insulating pillar 124 may include a second oxide layer 146 and an oxide material 148 , wherein the materials of the second oxide layer 146 and the oxide material 148 may be the same as each other, for example, both are dioxide silicon. The conductive layer CL can be formed of a conductive material, such as polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _X ), cobalt silicide (CoSi _X ) or other suitable materials. s material. In this embodiment, the material of the first bottom conductive layer 105 is different from the material of the conductive layer CL above the first bottom conductive layer 105 (ie, the second bottom conductive layer 112 and the upper conductive layer 116 ). The material of a bottom conductive layer 105 is P-type doped polysilicon, and the material of the second bottom conductive layer 112 and the upper conductive layer 116 is tungsten, although the invention is not limited to this. In some embodiments, the material of the first bottom conductive layer 105 may be the same as the material of the second bottom conductive layer 112 and the upper conductive layer 116 .

In this embodiment, the memory structure 122 includes a charge storage material, such as a charge storage material formed of an oxide layer, a nitride layer, and an oxide layer, but the invention is not limited thereto. The material of the channel layer 120 is, for example, undoped polysilicon, but the invention is not limited thereto. The material of the first conductive pillar 118a and the second conductive pillar 118b is, for example, N-type doped polysilicon, but the invention is not limited thereto.

In this embodiment, only 7 insulating layers IL and 6 conductive layers CL are illustrated, but the invention is not limited to this, the number of insulating layers IL may be greater than 7, and the number of conductive layers CL may be greater than 6 , the number and configuration of the insulating layer IL and the conductive layer CL can be adjusted as required.

As shown in FIG. 1B, in some embodiments, the intersections of the first conductive pillars 118a, the second conductive pillars 118b, the conductive layer 120 and each of the memory structures 122 and the upper conductive layer 116 may form a memory cell. A plurality of memory cells arranged in the first direction form a memory string MS. The upper conductive layer 116 can be used as a gate electrode, and the first conductive column 118a and the second conductive column 118b can be used as a source electrode or a drain electrode.

In this embodiment, there may be residual oxide between the bottom structure 18a of the first conductive pillar 118a and the channel layer 120 and between the bottom structure 18b of the second conductive pillar 118b and the channel layer 120 . The second bottom conductive layer 112 can serve as a dummy gate. In addition, a voltage of 0V or less (eg, a negative voltage) can be applied to the second bottom conductive layer 112 to prevent leakage current from occurring. However, the present invention is not limited thereto, and in some embodiments, there may be no oxide between the first conductive pillar 118a and the channel layer 120 and between the second conductive pillar 118b and the channel layer 120 .

In some embodiments, the first bottom conductive layer 105 can be used as a dummy gate, and a voltage of 0 V or less (eg, a negative voltage) can be applied to the first bottom conductive layer 105 to prevent leakage current in the channel layer 120 .

In some embodiments, the semiconductor device 100 of the present invention can be applied to 3D AND flash memory, 3D NOR memory, or other suitable memories.

2A to 12B are schematic diagrams illustrating a manufacturing process of the semiconductor device 100 according to an embodiment of the present invention. Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A show the planes formed by the X-axis and the Y-axis. Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, Figures 9B, 10B, 11B and 12B illustrate the plane formed by the X and Z axes. Specifically, Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A correspond to Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, and 11B, respectively. and the plane along the line BB' in Fig. 12B, Figs. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B and 12B respectively show the planes 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A and 12A are cross-sectional views taken along the line AA'.

Fig. 2A shows a top view after forming the initial structure P, which corresponds to the plane connected by the line B-B' in Fig. 2B.

2A and 2B, a substrate 101 is provided, and a first bottom insulating layer 103, a first bottom conductive layer 105, a second bottom insulating layer 107, a first bottom insulating layer 103, a first bottom conductive layer 105, a second bottom insulating layer 107, A bottom sacrificial layer 109 and a third bottom insulating layer 110 are formed to form an initial structure P. The deposition process is, for example, a chemical vapor deposition process.

Referring to FIGS. 3A and 3B, a plurality of first openings 132 passing through the third bottom insulating layer 110 and the bottom sacrificial layer 109 are formed along a first direction (eg, the Z direction) by an etching process. The bottom of each first opening 132 exposes a portion of the upper surface of the second bottom insulating layer 107 . Thereafter, the first openings 132 are filled with conductive material by a deposition process to form a plurality of bottom structures 18a and 18b of the first conductive pillars 118a and the second conductive pillars 118b (shown in FIGS. 1A and 1B ). In some embodiments, the bottom structures 18a and 18b and the bottom sacrificial layer 109 have the same thickness. The material of the bottom structures 18a and 18b is, for example, N-type doped polysilicon, but the invention is not limited thereto. In some embodiments, after the conductive material is filled into the first opening 132, an etch back process can be used to remove part of the conductive material to form the bottom structures 18a and 18b, wherein the bottom structures 18a and 18b and the third bottom There may be some recesses between the insulating layers 110 .

In some embodiments, after the original third bottom insulating layer 110 having the recesses is removed, a third bottom insulating layer 110 may be re-deposited on the bottom sacrificial layer 109 and the bottom structures 18a and 18b. In some embodiments, insulating material may be filled in the recess of the third bottom insulating layer 110 . In some embodiments, the third bottom insulating layer 110 can have a flat upper surface by a chemical mechanical polishing (CMP) process. However, the present invention is not limited to this.

Referring to FIGS. 4A and 4B , a stacked structure LS is formed on the third bottom insulating layer 110 , wherein the stacked structure LS includes a plurality of upper sacrificial layers 111 and a plurality of upper insulating layers 114 stacked alternately. The upper sacrificial layer 111 and the upper insulating layer 114 may be formed by deposition processes, respectively. In some embodiments, the material of the upper sacrificial layer 111 is nitride, such as silicon nitride; the material of the upper insulating layer 114 is oxide, such as silicon dioxide, but the invention is not limited thereto.

Referring to FIGS. 5A and 5B, after the step of forming the stacked structure LS, a plurality of second openings 134 are formed by an etching process (eg, dry etching), wherein the second openings 134 pass through the stacked structure LS, the first Three bottom insulating layers 110 , bottom sacrificial layers 109 , second bottom insulating layers 107 and first bottom conductive layers 105 . The second opening 134 is located between the bottom structure 18a of the first conductive pillar 118a and the bottom structure 18b of the second conductive pillar 118b. The first bottom conductive layer 105 can serve as an etch stop layer. In some embodiments, the first bottom conductive layer 105 may be exposed through a deep etching process, and then a breakthrough etching step may be used to pass through the first bottom conductive layer 105 and remove part of the first bottom conductive layer 105 . the bottom insulating layer 103 so that the bottom of the second opening 134 is in the first bottom insulating layer 103 . The second opening 134 may be used to define where the channel layer 120 (shown in FIGS. 6A and 6B ) is formed.

Thereafter, referring to FIGS. 6A and 6B , a first oxide layer 142 , a channel layer 120 and a second oxide layer 146 are sequentially formed on the sidewalls of the second opening 134 . A portion of the first bottom insulating layer 103 is exposed. In this embodiment, the material of the first oxide layer 142 and the second oxide layer 146 is, for example, silicon dioxide, and the material of the channel layer 120 is, for example, undoped polysilicon, but the invention is not limited thereto.

Referring to FIGS. 7A and 7B, the oxide material 148 is filled in the second opening 134 and on the stacked structure LS. For example, the oxide material 148 may be the same material as the second oxide layer 146 (eg, silicon dioxide). The oxide material 148 in the second opening 134 and the second oxide layer 146 may together form an insulating pillar 124, as shown in FIG. 1A.

Referring to FIGS. 8A and 8B , a plurality of third openings 136 are formed through the stacked structure LS and the third bottom insulating layer 110 and the bottom structures 18 a and 18 b are exposed through the third openings 136 . Bottom structures 18a and 18b can serve as etch stop layers.

Referring to FIGS. 9A and 9B , a portion of the stacked structure LS and the third bottom insulating layer 110 are removed through the third opening 136 . The first oxide layer 142 is also removed to expose the channel layer 120 over the bottom structures 18a and 18b.

Referring to FIGS. 10A and 10B , the conductive material is filled in the third opening 136 to form the first conductive column 118 a and the second conductive column 118 b. The first conductive pillar 118a and the second conductive pillar 118b contact the bottom structure 18a and the bottom structure 18b, respectively. In this embodiment, the material of the first conductive pillar 118a and the second conductive pillar 118b is, for example, N-type doped polysilicon, but the present invention is not limited thereto.

Referring to FIGS. 11A and 11B, after the insulating material is formed on the first conductive pillars 118a and the second conductive pillars 118b, a plurality of trenches 138 are formed. The trench 138 passes through the stacked structure LS, the third bottom insulating layer 110, the bottom sacrificial layer 112, the second bottom insulating layer 107, the first bottom conductive layer 105 and the first bottom insulating layer 103 along the first direction, and the trench The grooves 138 extend along a second direction (eg, the X direction), and the second direction is staggered with the first direction (eg, perpendicular to each other). As described above in relation to Figures 1A and 1B, trenches 138 may divide a later-formed stack ST into a plurality of sub-stacks (not shown). A later-formed stack ST includes a plurality of conductive layers CL and a plurality of insulating layers IL that are alternately stacked. The memory strings MS pass through the stacks ST formed later along the first direction, respectively. The memory string MS in FIGS. 1A and 1B is in one block of the memory array, or in a sub-block divided by the trenches 138 .

Referring to FIGS. 12A and 12B , the upper sacrificial layer 111 and the bottom sacrificial layer 109 are removed through the trench 138 by an etching process to form a plurality of fourth openings 140 between the insulating layers IL.

Thereafter, the positions where the upper sacrificial layer 111 and the bottom sacrificial layer 109 are removed (that is, in the fourth opening 140 ) are filled with memory material and conductive material to form a plurality of memory structures 122 and a plurality of upper conductive materials, respectively. layer 116 and the second bottom conductive layer 112, wherein the top conductive layer 116 and the second bottom conductive layer 112 correspond to the positions where the top sacrificial layer 111 and the bottom sacrificial layer 109 are removed, respectively. The memory structure 122 is formed on the sidewall of the fourth opening 140 . The memory structure 122 extends along the first direction and the second direction, so that the memory structure 122 surrounds each of the upper conductive layer 116 and the second bottom conductive layer 112, respectively, and forms a semiconductor device as shown in FIGS. 1A and 1B 100. The memory structure 122 also surrounds a portion of the channel layer 120, as shown in FIG. 1A.

In the subsequent process, a plurality of input lines and a plurality of output lines (not shown) may be formed on the semiconductor device 100, and the input lines and the output lines may be electrically connected to the first conductive pillar 118a and the second conductive pillar 118b, respectively.

According to an embodiment of the present invention, a semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes first and second conductive pillars, a channel layer, and a memory structure. The first conductive column and a second conductive column respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive column and the second conductive column, and the channel layer is coupled to the first conductive column and the second conductive column. The memory structure surrounds the first conductive column, the second conductive column and the channel layer.

Compared with the comparative example in which the channel layer is disposed outside the first conductive column and the second conductive column and surrounds the first conductive column and the second conductive column, because the channel layer of the semiconductor device of the present application is disposed between the first conductive column and the second conductive column Between the second conductive pillars, the length of the channel can be greatly shortened, so the size of the memory cells can be reduced, so that the memory cells can be stacked more closely. Therefore, the semiconductor device of the present invention can improve the performance of the semiconductor device on the one hand, and increase the density of the wafer on the other hand.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

18a, 18b: Bottom structure 100: Semiconductor Devices 101: Substrate 103: first bottom insulating layer 105: the first bottom conductive layer 107: Second bottom insulating layer 109: Bottom sacrificial layer 112: Bottom sacrificial layer 110: The third bottom insulating layer 111: Upper sacrificial layer 116: Upper conductive layer 114: Insulation layer 116: Upper conductive layer 118a: the first conductive column 118b: second conductive column 120: channel layer 120n: annular inner surface 120t: annular outer surface 122: Memory structure 124: Insulation column 132: The first opening 134: Second Opening 136: The third opening 138: Groove 140: Fourth opening 146: Second oxide layer 148: oxide material A,A',B,B': Hatch line endpoints C1: First position C2: Second position CL: Conductive layer IL: insulating layer L1, L2: length LS: Laminated structure MS: Memory Serial ST: stack W1: first width W2: Second width

FIG. 1A shows a top view of a semiconductor device according to an embodiment of the present invention; Fig. 1B shows a cross-sectional view along the line A-A' of Fig. 1A; and 2A to 12B are schematic diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

100: Semiconductor Devices

116: Upper conductive layer

118a: the first conductive column

118b: second conductive column

120: channel layer

120n: annular inner surface

120t: annular outer surface

122: Memory structure

124: Insulation column

138: Groove

146: Second oxide layer

148: oxide material

A,A': Endpoint of hatch line

C1: First position

C2: Second position

W1: first width

W2: Second width

Claims (10)

A semiconductor device, comprising: a stack formed on a substrate, the stack including a plurality of conductive layers and a plurality of insulating layers alternately stacked; and A plurality of memory strings pass through the stack along a first direction, and each of the memory strings includes: a first conductive column and a second conductive column respectively extending along the first direction and electrically isolated from each other; a channel layer extending along the first direction, wherein the channel layer is disposed between the first conductive column and the second conductive column, and the channel layer is coupled to the first conductive column and the second conductive column ;as well as A memory structure surrounds the first conductive column, the second conductive column and the channel layer. The semiconductor device of claim 1, wherein: The channel layer has an annular cross section formed along a second direction and a third direction, the second direction and the third direction are perpendicular to the first direction, the channel layer has an annular inner surface and an annular A shape outer surface, the first conductive column and the second conductive column are coupled to the annular outer surface. The semiconductor device of claim 2, wherein each of the memory strings includes an insulating pillar located in a central region, and the insulating pillar is connected to the annular inner surface of the channel layer. The semiconductor device of claim 1, wherein each of the memory strings includes an insulating pillar located in a central region, and the channel layer extends between the insulating pillar and the first conductive pillar along the first direction and between the insulating column and the second conductive column. The semiconductor device of claim 1, wherein the first conductive column is coupled to a first position of the channel layer, the second conductive column is coupled to a second position of the channel layer, and the first position is The second positions are opposite to each other along a second direction, the second direction is staggered with the first direction, On the extension line between the first position and the second position, the channel layer forms a first width, the width formed from the first conductive column to the second conductive column is a second width, and the The second width is greater than the first width. A semiconductor device, comprising: a stack formed on a substrate, the stack including a plurality of conductive layers and a plurality of insulating layers alternately stacked; and A plurality of memory strings pass through the stack along a first direction, and each of the memory strings includes: a first conductive column and a second conductive column respectively extending along the first direction and electrically isolated from each other; a channel layer extending along the first direction, wherein the channel layer is coupled to the first conductive column and the second conductive column; and a memory structure surrounding the first conductive column, the second conductive column and the channel layer; Wherein, the conductive layers include a first bottom conductive layer, and the first bottom conductive layer is disposed under the first conductive column and the second conductive column. The semiconductor device of claim 6, wherein, in the first direction, the first bottom conductive layer overlaps the first conductive column and the second conductive column. The semiconductor device of claim 6, wherein the channel layer passes through the first bottom conductive layer. The semiconductor device of claim 6, wherein the material of the first bottom conductive layer is different from the material of the conductive layers disposed on the first bottom conductive layer. The semiconductor device of claim 6, wherein the first conductive column, the channel layer and the second conductive column are arranged along a second direction different from the first direction, and the first conductive column and the first conductive column are arranged along a second direction different from the first direction. Two conductive pillars contact opposite sides of the channel layer along the second direction.

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