CN217361632U - Storage capacitor - Google Patents

Abstract

The utility model provides a storage capacitor, include: the cross-sectional structure comprises a semiconductor substrate, an insulating layer positioned on the semiconductor substrate, a first dielectric layer on the insulating layer, a first conducting layer on the first dielectric layer, a second dielectric layer on the first conducting layer and a second conducting layer on the second dielectric layer, wherein the first conducting layer and the second conducting layer positioned at the bottom and the side wall form a U-shaped folding area; a third dielectric layer on the second conductive layer and a third conductive layer on the third dielectric layer, the third conductive layer being electrically connected to the first conductive layer through the first plate contact via, the third conductive layer being electrically connected to the second conductive layer through the second plate contact via; on the planar structure, no other conductive layer is disposed around the first conductive layer contacted by the first plate contact via, and no other conductive layer is disposed around the second conductive layer contacted by the second plate contact via. The storage capacitor can provide a self-aligned plate contact through hole structure, and the performance of the storage capacitor is improved.

Description

Storage capacitor

Technical Field

The utility model relates to a semiconductor manufacturing technology field especially relates to a storage capacitor.

Background

The unit cell of the storage capacitor generally includes a storage capacitor and a MOS transistor. The increase in the storage density thereof requires more memory cells to be integrated per unit area and more information to be stored per unit memory cell. With the improvement of the integration level and the performance requirement of the semiconductor technology, the chip area is continuously reduced, and the process requirement is higher and higher in order to integrate more memory cells on a unit area.

When the integration of semiconductor devices is increased, the requirement on the positioning accuracy of the position of the plate contact through hole connected to one layer to other layers is high, but the positioning accuracy of the plate contact hole is not high at present, which may cause the plate contact through hole structure to simultaneously contact with more than two metal electrode plates, resulting in short circuit, thereby affecting the performance of the container.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a novel storage capacitor for provide self-aligning board contact through-hole structure, promote storage capacitor's performance.

To achieve the above object, the present invention provides a storage capacitor, including: the cross-sectional structure comprises a semiconductor substrate, an insulating layer positioned on the semiconductor substrate, a first dielectric layer on the insulating layer, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer and a second conductive layer on the second dielectric layer, wherein the first conductive layer and the second conductive layer positioned at the bottom and the side wall form a U-shaped folding area; a third dielectric layer on the second conductive layer and a third conductive layer on the third dielectric layer, the third conductive layer being electrically connected to the first conductive layer through the first plate contact via, the third conductive layer being electrically connected to the second conductive layer through the second plate contact via; on the planar structure, no other conductive layer is arranged around the first conductive layer contacted by the first plate contact through hole, and no other conductive layer is arranged around the second conductive layer contacted by the second plate contact through hole.

The utility model provides a storage capacitor's beneficial effect lies in: because of different conducting layers are adjacent, so if the positioning accuracy of board contact hole is not high, may cause board contact through-hole structure and the simultaneous emergence contact of more than two metal electrode boards, take place the short circuit, thereby influence the performance of container, so this embodiment cuts off near board contact hole's different conducting layers when semiconductor technology design, no other conducting layers set up around the conducting layer that contact through-hole contacted promptly, in order to avoid board contact through-hole structure and the simultaneous emergence contact of more than two metal electrode boards, thereby realize the storage capacitor of board contact through-hole structure that has the self-alignment effect, promote storage capacitor's performance.

In a possible implementation manner, the conductive patterns of the first conductive layer and the second conductive layer are both honeycomb-shaped, and the patterns of the first conductive layer and the second conductive layer are both honeycomb-shaped, so that the area of a chip can be fully utilized, compared with the existing circular pattern, the capacity of the storage capacitor is large, and the capacity of the storage capacitor is improved on the premise of ensuring the performance of the storage capacitor. And a calibration area is reserved in the conductive patterns of the first conductive layer and the second conductive layer. For example, a honeycomb pattern is provided in the reserved alignment area to facilitate optical alignment.

In another possible implementation manner, the first mask layer, the second mask layer, the third mask layer, the fourth mask layer, and the fifth mask layer in the storage capacitor are all made of silicon nitride.

In a possible implementation manner, the first mask layer, the second mask layer, the third mask layer, the fourth mask layer, and the fifth mask layer are all made of silicon nitride.

In one possible embodiment, the method further comprises: the material of the insulating layer is at least one of materials with dielectric constants larger than 3.9.

In a possible embodiment, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.

In one possible embodiment, the materials of the first conductive layer, the second conductive layer and the third conductive layer are copper, aluminum or tungsten.

Drawings

Fig. 1 is a schematic diagram of a cross-sectional structure of a storage capacitor according to the present invention;

fig. 2 is a schematic plan view of a storage capacitor according to the present invention;

fig. 3 is a schematic cross-sectional view of another storage capacitor provided by the present invention;

fig. 4 is a schematic plan view of a storage capacitor according to the present invention;

fig. 5 is a schematic diagram illustrating a comparison between a circular pattern and a honeycomb pattern provided by the present invention;

fig. 6 is a schematic layout diagram of a honeycomb pattern and optical marks provided by the present invention;

fig. 7 is a flow chart of a method for manufacturing a storage capacitor according to the present invention;

fig. 8 is a schematic illustration of an intermediate structure of some embodiments of the present invention;

fig. 9 is a schematic illustration of an intermediate structure of further embodiments of the present invention;

fig. 10A to 10G are schematic views of intermediate structures in further embodiments of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions in the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but not the exclusion of other elements or items.

Fig. 1 shows a cross-sectional structure diagram of a storage capacitor provided by the present invention, including: a semiconductor substrate 100, which is sequentially located on an insulating layer (not shown in fig. 1) on the semiconductor substrate, a first dielectric layer (not shown in fig. 1) on the insulating layer, a first conductive layer 103 on the first dielectric layer, a second dielectric layer 104 on the first conductive layer, and a second conductive layer 105 on the second dielectric layer, wherein the first conductive layer 103 and the second conductive layer 105 located at the bottom and the side wall form a U-shaped folding region; a third dielectric layer 106 on the second conductive layer 105 and a third conductive layer 107 on the third dielectric layer 106, wherein the third conductive layer 107 is electrically connected to the first conductive layer 103 through a first plate contact via a, and the third conductive layer 107 is electrically connected to the second conductive layer 105 through a second plate contact via b.

It is to be noted that, as shown in fig. 2 (a), the neck portion of the conductive layer at a-a ' is cut off by grinding or process design on the planar structure, as shown in fig. 2 (B), no other conductive layer is provided around the conductive layer contacted by the board contact via 10 at the cross section a-a ', and as shown in fig. 2 (c), another conductive layer is provided around the conductive layer contacted by the board contact via 10 at the cross section B-B '. As described above, even if the positioning accuracy of the plate contact hole 10 is inaccurate and the plate contact hole 10 is displaced, as shown in fig. 3, the second conductive layer 105 is not provided around the first conductive layer 103 which the first plate contact through hole a contacts, and thus, a short circuit does not occur and the performance of the container is not affected.

As shown in fig. 4, the patterns of the first conductive layer 103 and the second conductive layer 105 are honeycomb-shaped in a planar structure. Generally, the pattern formed by etching is generally circular, and in the present embodiment, a honeycomb pattern is formed by adding an optical alignment process during etching. As can be seen from fig. 5, the chip areas of fig. 5 (a) and 5 (b) are equal, but the area of the margin region shown in fig. 5 (a) is much larger than that of fig. 5 (b), and thus it can be seen that the honeycomb pattern can more fully utilize the chip area than the circular pattern of the conductive pattern.

It is understood that, in order to increase the etching accuracy of the honeycomb pattern, the present embodiment may set optical marks at four corners of the honeycomb pattern, as shown in fig. 6, and each of the four corners of each hexagon is respectively set with an optical mark, and the optical marks are used for optical calibration.

The formation process of the capacitor memory is described below with reference to the manufacturing process of the capacitor memory, fig. 7 shows a flow chart of the manufacturing method of the capacitor memory, and fig. 8 shows a cross-sectional view of a staged intermediate structure of each process preparation stage in this example.

Referring to fig. 7, a method for manufacturing a storage capacitor according to an embodiment of the present invention includes the following steps:

s7501, a semiconductor substrate 100 is provided.

Exemplarily, as shown in (a) of fig. 8, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the semiconductor substrate 100 may also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate.

S7502, forming a first mask layer 6201 on the semiconductor substrate 100.

Illustratively, as shown in fig. 8 (a), the first mask layer 6201 may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

S7503, etching the first mask layer 6201 to form a first trench 01.

Illustratively, as shown in (b) of fig. 8, the first trench 01 may be formed as shown by coating a photoresist on the first mask layer 6201 and then performing a patterned etch. The photoresist used for this step may be a relatively inexpensive photoresist.

S7504, forming a second mask layer 6202 on the bottom and the sidewall of the first trench 01 and above the first mask layer 6201, so as to form a second trench 02, where the width and the depth of the second trench 02 are both smaller than those of the first trench 01.

Illustratively, as shown in fig. 8 (c), the second trench 02 may be formed by removing the photoresist coated on the first mask layer 6201 and then depositing a layer of polysilicon, which may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride. The photoresist used for this step can still be a relatively inexpensive photoresist.

S7505, removing the second mask layer 6202 over the first mask layer, the first mask layer 6201, and the second mask layer 6202 located at the bottom of the second trench 02.

Illustratively, after one etching, the second mask layer 6202 over the first mask layer 6201 and the second mask layer 6202 at the bottom of the second trench 02 are removed, and then the structures of the remaining first mask layer 6201 and second mask layer 6202 are shown in fig. 8 (d). After that, the remaining first mask layer 6201 is removed by further etching, and the structure of the remaining second mask layer 6202 is shown in (e) of fig. 8.

S7506, a third mask layer 6203 on the remaining second mask layer 6202, a fourth mask layer 6204 on the third mask layer 6203, and a fifth mask layer 6205 on the fourth mask layer 6204 are sequentially formed.

Illustratively, as shown in (a) of fig. 9, a third mask layer 6203 is formed on a semiconductor substrate, and thereafter, further, as shown in (b) of fig. 9, a fourth mask layer 6204 is formed on a surface of the third mask layer 6203; thereafter, as shown in fig. 9 (c), a fifth mask layer 6205 is formed on the surface of the fourth mask layer 6204. The third mask layer 6203, the fourth mask layer 6204, or the fifth mask layer 6205 may be polysilicon, which may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

S7507, grinding and thinning the fourth mask layer 6204 and the fifth mask layer 6205 to expose the second mask layer 6202.

Illustratively, the intermediate structure shown in fig. 9 (c) is ground down to expose the second mask layer 6202, as shown in fig. 9 (d).

S7508, removing the second mask layer 6202 and a portion of the fourth mask layer 6203, forming a third trench 03 and a U-shaped opening at the boundary.

Illustratively, the third trench 03 as shown in (e) of fig. 9 is formed by removing all of the second mask layer 6202 shown in (d) of fig. 9, and a portion of the fourth mask layer 6203, by wet etching or dry etching.

S7509, etching the semiconductor substrate 100 by using the third mask layer 6203 around the third trench 03, the part of the fourth mask layer 6204, and the fifth mask layer 6205 as a barrier layer, and forming a fourth trench 04 in the semiconductor substrate 100.

Illustratively, the third trench 03 shown in (e) of fig. 9 is patterned and etched with the third mask layer 6203, the fourth mask layer 6204, and the fifth mask layer 6205 around the third trench 03 as a barrier layer, so as to etch a portion of the semiconductor substrate 100, thereby forming a fourth trench 04 in the semiconductor substrate 100, as shown in (f) of fig. 9. As can be seen from the figure, the fourth trench 04 has a narrower trench width, which helps to increase the surface area of the capacitor and increase the capacitance of the storage capacitor.

S7510, removing the third mask layer 6203, the fourth mask layer 6204, and the fifth mask layer 6205 as a barrier layer above the fourth trench 04.

For example, the intermediate structure after removing the third mask layer 6203, the fourth mask layer 6204, and the fifth mask layer 6205 as the barrier layer over the fourth trench 04 is shown in (g) of fig. 9.

S7511, forming an insulating layer 101 on the sidewalls of the fourth trench 04, the bottom of the fourth trench 04, the U-shaped opening, and the semiconductor substrate 100.

Optionally, the material of the insulating layer 101 is at least one of materials having a dielectric constant greater than 3.9. Optionally, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide. The insulating layer is used for isolating the conducting layer from the semiconductor substrate and avoiding electric leakage.

S7512, forming a first dielectric layer 102 on the insulating layer 101.

It is noted that the cross-sectional views of the intermediate structures in fig. 10A to 10G are not shown in the insulating layer 101 and the first dielectric layer 102. For ease of understanding, fig. 10A illustrates a partial enlarged view of the U-shaped opening position, in which the insulating layer 101 and the first dielectric layer 102 are illustrated.

S7513, forming a first conductive layer 103 on the first dielectric layer.

Illustratively, as shown in fig. 10A, a first conductive layer 301 is formed on the first dielectric layer by deposition.

S7514, forming a second dielectric layer 104 on the first conductive layer.

Illustratively, as shown in fig. 10B, a second dielectric layer 104 is formed on the first conductive layer 103.

S7515, forming a second conductive layer 105 on the second dielectric layer 104.

Illustratively, as shown in fig. 10C, a second conductive layer 105 is formed on the second dielectric layer 104.

Optionally, the method further includes the following steps: forming a third dielectric layer 106 on the second conductive layer 105, and performing planarization treatment; and etching the third dielectric layer 106 to form a through hole so as to expose the first conductive layer 103 and the second conductive layer 105. And filling a third conducting layer 107 in the through hole, and etching the third conducting layer 107 to form the through hole so as to complete top metal interconnection.

Illustratively, a third dielectric layer 106 is formed on the second conductive layer 105, followed by planarization, resulting in the cross-sectional view of the intermediate structure shown in fig. 10D. As shown in fig. 10E, the third dielectric layer 106 is etched once to expose the first conductive layer 103 and the second conductive layer 105. The via hole is filled with a third conductive layer 107, as shown in fig. 10F. Before packaging the semiconductor structure, the third conductive layer 107 is etched by coating photoresist and patterning, so as to expose part of the third conductive layer 107, and complete the top metal interconnection, as shown in fig. 10G.

It can be seen that, in addition to completing the self-aligned boundary and expanding the two second trenches 02 shown in fig. 8 (c) to nine fourth trenches 04 in fig. 8A, the above manufacturing method can implement the fabrication of the multiple sidewall patterns, and can also save the number of times of photolithography and achieve the purpose of saving cost at the stage of electrically connecting the conductive layer by forming the conductive layer folding region at the U-shaped opening of the boundary.

In one possible embodiment, the material of the first conductive layer 103, the second conductive layer 105, or the third conductive layer 107 may be copper, aluminum, or tungsten.

It should be noted that, after the second conductive layer 105 is formed and before the third conductive layer 107 is formed, a greater number of dielectric layers and conductive layers may be deposited in the semiconductor structure, which is not shown in this embodiment.

In this embodiment, the manufacturing method can complete the etching with higher lithography precision under the production condition of using the common photoresist, and the finally manufactured trench has a narrower trench width, which is helpful for increasing the surface area of the capacitor and improving the capacity of the storage capacitor, and reduces the requirement on the lithography precision of the lithography machine on the premise of ensuring the performance of the storage capacitor, thereby reducing the process complexity and the production cost. In addition, a conducting layer folding area is formed at the U-shaped opening of the boundary, so that the photoetching times are saved at the stage of electrically connecting the conducting layer, and the aim of saving the cost is fulfilled.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the appended claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (6)

1. A storage capacitor is characterized by sequentially comprising a semiconductor substrate, an insulating layer positioned on the semiconductor substrate, a first dielectric layer on the insulating layer, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer and a second conductive layer on the second dielectric layer from bottom to top on a cross-sectional structure;

the first conducting layer and the second conducting layer positioned at the bottom and the side wall form a U-shaped folding area; a third dielectric layer on the second conductive layer and a third conductive layer on the third dielectric layer, the third conductive layer being electrically connected to the first conductive layer through the first plate contact via, the third conductive layer being electrically connected to the second conductive layer through the second plate contact via; on the planar structure, the second conductive layer is not disposed around the first conductive layer contacted by the first plate contact via, and the first conductive layer is not disposed around the second conductive layer contacted by the second plate contact via.

2. A storage capacitor according to claim 1, wherein the conductive patterns of the first conductive layer and the second conductive layer are each formed in a honeycomb shape.

3. A storage capacitor as claimed in claim 2, characterized in that a calibration area is reserved in the conductive pattern of the first and second conductive layers.

4. A storage capacitor as claimed in claim 1 or 2, further comprising:

the material of the insulating layer is at least one of materials with dielectric constants larger than 3.9.

5. A storage capacitor as claimed in any one of claims 1 to 3, wherein the material of the insulating layer comprises at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium oxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, titanium dioxide.

6. A storage capacitor as claimed in any one of claims 1 to 3, wherein the first, second and third conductive layers are all copper, aluminium or tungsten.

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