CN115867127B

CN115867127B - Semiconductor structure and preparation method thereof

Info

Publication number: CN115867127B
Application number: CN202310196754.8A
Authority: CN
Inventors: 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Xinqiao Storage Technology Co ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-06-02
Anticipated expiration: 2043-03-03
Also published as: CN115867127A

Abstract

The application relates to a semiconductor structure and a preparation method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a capacitor structure, and the capacitor structure comprises a capacitor electrode layer; forming a contact electrode on the capacitance electrode layer; forming a contact hole on the contact electrode; and forming a conductive structure in the contact hole. In the method for manufacturing the semiconductor structure, the contact electrode is formed on the capacitor electrode layer, and then the contact hole is formed on the contact electrode. The formation of the contact electrode can effectively prevent the capacitor electrode layer from being etched through in the process of etching the contact hole, so that the capacitor electrode layer can be effectively prevented from being damaged, and the risks of short circuit, electric leakage and the like between the capacitor electrode layers are reduced.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to integrated circuit technology, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

In conventional capacitor structures, the thickness of the capacitor electrode layer is typically relatively thin. In forming the contact hole in the capacitor electrode layer, it is necessary to etch the capacitor electrode layer. In the etching process, the thinner capacitor electrode layer is easily damaged due to over etching, so that the phenomena of short circuit and electric leakage occur.

Disclosure of Invention

Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same, which are directed to the problem that the thinner capacitor electrode layer in the conventional art is easily damaged due to over etching.

In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor structure, including:

providing a substrate, wherein the substrate comprises a capacitor structure, and the capacitor structure comprises a capacitor electrode layer;

forming a contact electrode on the capacitance electrode layer;

forming a contact hole on the contact electrode;

and forming a conductive structure in the contact hole.

In the method for manufacturing the semiconductor structure, the contact electrode is formed on the capacitor electrode layer, and then the contact hole is formed on the contact electrode. The formation of the contact electrode can effectively prevent the capacitor electrode layer from being etched through in the process of etching the contact hole, so that the capacitor electrode layer can be effectively prevented from being damaged, and the risks of short circuit, electric leakage and the like between the capacitor electrode layers are reduced.

In order to better prevent the damage to the capacitor electrode layer, the contact electrode may be thicker, so that etching stops on the contact electrode during the formation of the contact hole. For example, the thickness of the contact electrode may be set to 20nm to 50nm. At the same time, thicker contact electrodes also have lower contact resistance.

In one embodiment, the forming a contact electrode on the capacitive electrode layer includes:

etching the substrate to form a step with the bottom surface exposing the capacitance electrode layer;

forming a contact material layer on the top surface, the bottom surface and the side wall of the step;

and etching the contact material layer to form the contact electrode.

In one embodiment, the etching the contact material layer to form the contact electrode includes:

forming a mask layer on the contact material layer on the bottom surface of the step;

and etching the contact material layer based on the mask layer to form the contact electrode.

In one embodiment, forming a mask layer on the contact material layer on the bottom surface of the step includes:

forming a mask material layer on the surface of the contact material layer;

and carrying out anisotropic etching on the mask material layer, and removing the mask material layer outside the side wall of the contact material layer to form the mask layer.

forming a mask material layer on the surface of the contact material layer;

forming patterned photoresist on the surface of the mask material layer;

and forming the mask layer based on the patterned photoresist.

In one embodiment, the capacitor structure comprises a plurality of capacitor electrode layers and a capacitor dielectric layer between adjacent capacitor electrode layers, and the substrate comprises an insulating dielectric layer covering the capacitor structure;

etching the substrate to form a step with the bottom surface exposing the capacitance electrode layer, wherein the step comprises the following steps:

and etching the substrate to form a plurality of continuous steps exposing each capacitance electrode layer, wherein for the adjacent capacitance electrode layers, the bottom surface of the step exposing the upper capacitance electrode layer is the top surface of the step exposing the lower capacitance electrode layer.

In one embodiment, the etching the contact material layer based on the mask layer to form the contact electrode includes:

and etching the contact material layer and each capacitor electrode layer based on the mask layer and by taking the insulating medium layer and the capacitor medium layer as etching stop layers to form the contact electrode.

In one embodiment, the contact material layer on the step side wall is partially retained so that the contact electrode is stepped.

In one embodiment, the substrate is provided with a groove, the capacitance electrode layer comprises a capacitance part and a terminal part which are connected with each other, the capacitance part is arranged along the inner wall of the groove, and the terminal part is positioned outside the groove;

the forming a contact electrode on the capacitor electrode layer includes:

the contact electrode is formed on the terminal portion.

The present application also provides a semiconductor structure comprising:

a substrate comprising a capacitive structure, the capacitive structure comprising a capacitive electrode layer;

a contact electrode on the capacitive electrode layer;

and the conductive structure is positioned on the contact electrode.

In one embodiment, the substrate has a step exposing the capacitor electrode layer, and the contact electrode is located on the bottom surface of the step.

In one embodiment, the capacitor structure comprises a plurality of capacitor electrode layers and a capacitor dielectric layer between adjacent capacitor electrode layers, and the substrate comprises an insulating dielectric layer covering the capacitor structure,

the substrate has a plurality of successive steps exposing each capacitive electrode layer.

In one embodiment, the contact electrode is aligned with the capacitor electrode layer on which it is located on a side remote from the side wall of the step on which it is located.

In one embodiment, the contact electrode is stepped, and the thickness of the contact electrode on the side close to the side wall of the step where the contact electrode is located is smaller than that of the contact electrode on the side away from the side wall of the step where the contact electrode is located.

In one embodiment, the substrate is provided with a groove, the capacitor electrode layer comprises a capacitor part and a terminal part, the capacitor part and the terminal part are connected with each other, the capacitor part is arranged along the inner wall of the groove, the terminal part is positioned outside the groove, and the contact electrode is positioned on the terminal part.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 is a schematic cross-sectional view of a semiconductor structure obtained in step S100 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 3 is a schematic cross-sectional view of the structure obtained in step S210 in the method for fabricating a semiconductor structure according to an embodiment;

FIG. 4 is a schematic cross-sectional view of the structure obtained in step S220 in the method for fabricating a semiconductor structure according to one embodiment;

FIG. 5 is a schematic cross-sectional view of a semiconductor structure obtained in step S2311a according to an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of a semiconductor structure obtained in step S2312a in a method for fabricating a semiconductor structure according to an embodiment;

fig. 7 is a schematic cross-sectional structure of the structure obtained in step S232 in the method for manufacturing a semiconductor structure according to an embodiment;

FIG. 8 is a schematic cross-sectional view of the structure obtained in step S231 in the method for fabricating a semiconductor structure according to one embodiment;

FIG. 9 is a schematic cross-sectional view of the structure obtained in step S400 in the method for fabricating a semiconductor structure according to an embodiment;

fig. 10 is a schematic cross-sectional structure of the structure obtained in step S211 in the method for manufacturing a semiconductor structure according to an embodiment.

Reference numerals illustrate: 100-substrate, 200-capacitance electrode layer, 210-first capacitance electrode layer, 220-second capacitance electrode layer, 230-third capacitance electrode layer, 310-contact material layer, 320-contact electrode, 321-first contact electrode, 322-second contact electrode, 323-third contact electrode, 400-conductive structure, 510-first capacitance dielectric layer, 520-second capacitance dielectric layer, 600-insulating dielectric layer, 700-protective dielectric layer, 800-mask layer, 810-mask material layer, 910-first patterned photoresist, 920-second patterned photoresist, 930-third patterned photoresist.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

As to the background art, in the conventional capacitor structure, the thickness of the capacitor electrode layer is generally thinner, so that when a contact hole is formed on the capacitor electrode layer, the capacitor electrode layer is easily damaged due to over etching, and thus short circuit and electric leakage occur.

For example, in the conventional packaging process, various semiconductor chips (such as logic chips, memory chips, etc.) may be integrated into the same packaging structure, so that better performance and lower power consumption may be obtained. The interposer is applied in the packaging process, and can play a good connection function between the semiconductor chip and the packaging substrate.

Meanwhile, the interposer typically forms decoupling capacitors to improve circuit stability. Conventional decoupling capacitors are typically embedded deep trench capacitors, which typically require double sided capacitors to increase the capacitance density. A contact hole is typically formed in the capacitor electrode layer of the decoupling capacitor to connect the capacitor electrode layer to an external circuit. However, the conventional decoupling capacitor has a problem that the capacitor electrode layer is thin and is easily damaged during etching.

The semiconductor structure and the preparation method thereof provided by the embodiment of the invention can be applied to an interposer (such as a silicon interposer) structure but not limited to the application.

In one embodiment, referring to fig. 1 and 9, a method for fabricating a semiconductor structure is provided, including:

step S100, providing a substrate 100, wherein the substrate 100 comprises a capacitor structure, and the capacitor structure comprises a capacitor electrode layer 200;

step S200, forming a contact electrode 320 on the capacitor electrode layer 200;

step S300, forming a contact hole on the contact electrode 320;

in step S400, a conductive structure 400 is formed in the contact hole.

In step S100, referring to fig. 2, the base 100 may include a semiconductor substrate. For example, the semiconductor substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other group III/V or group II/VI substrates. Alternatively, the base 100 may comprise a semiconductor substrate such as a Si/SiGe substrate, a Si/SiC substrate, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator substrate, for example. The type of semiconductor substrate should therefore not limit the scope of protection of the present application.

Meanwhile, the substrate 100 includes a capacitor structure including a capacitor electrode layer 200.

As an example, the substrate 100 may have a trench therein, and the capacitor structure may be a trench capacitor. For example, the capacitor structure may be a deep trench capacitor. The depth of the deep trench may be 30 μm and the diameter of the deep trench may be 1 μm to 4 μm. For example, the deep trench has a diameter of 1.5 μm.

At this time, the protective dielectric layer 700 may be further formed on the semiconductor substrate of the base 100. Meanwhile, a trench extending from the protective dielectric layer 700 into the semiconductor substrate may be formed. The capacitor structure may extend from within the trench to outside the trench. The capacitor structure may also be covered with an insulating dielectric layer 600, where the insulating dielectric layer 600 isolates the capacitor structure from the outside.

Meanwhile, the capacitive electrode layer 200 may include a capacitive part and a terminal part at this time. The capacitor portion may be located within the trench of the substrate 100 and disposed along the inner wall of the trench. The terminal portion is connected to the capacitor portion, which may be located outside the trench. For example, the terminal portion may be located on an upper surface of the protective dielectric layer 700 outside the trench.

The number of the capacitive electrode layers 200 may be plural. At this time, one capacitance medium layer may be provided between two adjacent capacitance electrode layers 200. The material of the capacitive electrode layer 200 may be titanium nitride (TiN), and the thickness thereof may be 20nm. The material of the capacitive dielectric layer may include, but is not limited to, a high dielectric constant material. For example, the material of the capacitor dielectric layer includes zirconium oxide (ZrO), aluminum oxide (AlO), hafnium oxide (HfO). The thickness of the capacitive dielectric layer may be 80 a to 150 a. For example, the thickness of the capacitive dielectric layer may be 10nm.

In step S200, the contact electrode 320 is formed on the capacitor electrode layer 200, the contact material layer 310 may be formed on the capacitor electrode layer 200, and then the contact material layer 310 may be etched to form the contact electrode 320, or the contact electrode 320 may be formed directly (e.g. by sputtering), which is not limited herein.

As an example, the material of the contact electrode 320 may be selected from tungsten (W). The thickness of the contact electrode 320 may be 20nm to 50nm.

Meanwhile, as an example, when the capacitance structure is a trench capacitance, the contact electrode 320 may be formed on a terminal portion of the capacitance electrode layer 200.

In step S300, after the contact electrode 320 is formed, a plurality of re-wiring layers may be formed. An interlayer dielectric layer may be formed between the re-wiring layer and the contact electrode 320 and between adjacent re-wiring layers.

The contact hole may be formed between the re-wiring layer and the contact electrode 320 through one or several interlayer dielectric layers, etc. The diameter of the contact hole may be, for example, 0.2 μm to 0.4 μm.

In step S400, the contact hole is filled to form the conductive structure 400, so that the contact electrode 320 can be connected with the re-wiring layer to be connected through the conductive structure 400, so that the capacitor structure can be used as a decoupling capacitor.

In this embodiment, the contact electrode 320 is formed on the capacitive electrode layer 200, and then a contact hole is formed on the contact electrode 320. The formation of the contact electrode 320 can effectively prevent the capacitive electrode layer 200 from being etched through due to partial over etching caused by different etching depths in the process of etching to form the contact hole, so that damage to the capacitive electrode layer 200 can be effectively prevented, and the risks of short circuit, electric leakage and the like between the capacitive electrode layers 200 are reduced.

In order to better prevent the damage to the capacitive electrode layer 200, the contact electrode 320 may be provided to be thicker, so that etching stops on the contact electrode 320 during the formation of the contact hole. For example, the contact electrode 320 may be provided to have a thickness of 20nm to 50nm. At the same time, the thicker contact electrode 320 also has a lower contact resistance.

In one embodiment, step S200 includes:

step S210, etching the substrate 100 to form a step with the bottom surface exposing the capacitor electrode layer 200;

step S220, forming a contact material layer 310 on the top surface, the bottom surface and the sidewalls of the step;

in step S230, the contact material layer 310 is etched to form the contact electrode 320.

In step S210, referring to fig. 3, the substrate 100 may include a capacitor structure and an insulating dielectric layer 600 covering the capacitor structure. When the substrate 100 is etched, the insulating dielectric layer 600 may be etched first, thereby forming a step, the bottom surface of which exposes the capacitor electrode layer 200. A step includes a top surface, a bottom surface, and a sidewall.

As an example, the substrate 100 may be etched by dry etching, and the step morphology may be better maintained due to the anisotropic nature of the dry etching.

In step S220, referring to fig. 4, a contact material layer 310 is formed on the top surface, the bottom surface and the side walls of the step, the contact material layer 310 completely covers the step, and the thickness of the contact material layer 310 is relatively uniform at each position, so that the upper surface of the contact material layer is uniform with the shape of the upper surface of the etched substrate 100, and is in a step shape.

As an example, the material of the contact material layer 310 may be selected from tungsten (W), and the thickness of the contact material layer 310 may be 20nm to 50nm.

In step S230, the contact material layer 310 is etched to form a contact electrode 320. As an example, the contact material layer 310 may be etched using dry etching, and the contact material layer 310 may be removed and remain as needed, and the remaining portion forms the contact electrode 320 due to the anisotropic characteristic of the dry etching.

In one embodiment, referring to fig. 7, step S230 includes:

step S231, forming a mask layer 800 on the contact material layer 310 on the bottom surface of the step;

in step S232, the contact electrode 320 is formed by etching the contact material layer 310 based on the mask layer 800.

In step S231, a mask layer 800 is formed on the contact material layer 310 on the bottom surface of the step. Masking material layer 810 may be first formed on contact material layer 310 and then masking material layer 810 may be patterned to form masking layer 800.

In step S232, the contact material layer 310 is etched based on the mask layer 800, thereby forming the contact electrode 320.

In this embodiment, first, a mask layer 800 is formed on the contact material layer 310, and the contact electrode 320 is obtained by etching the contact material layer 310 through the mask layer 800. The formation of the mask layer 800 facilitates the etching of the contact electrode 320 to a predetermined topography size, which allows for a more controllable topography size of the contact electrode 320.

In other embodiments, instead of forming the mask layer 800, the contact material layer 310 may be directly etched (for example, with anisotropic dry etching), so that a portion of the contact material layer 310 located on the sidewall of the step remains, thereby forming the contact electrode 320.

In one embodiment, referring to fig. 5 and fig. 6, step S231 includes:

step S2311a, forming a mask material layer 810 on the surface of the contact material layer 310;

in step S2312a, the mask material layer 810 is anisotropically etched to remove the mask material layer 810 outside the sidewall of the contact material layer 310, so as to form the mask layer 800.

A masking material layer 810 may be formed on the contact material layer 310, and the masking material layer 810 completely covers the contact material layer 310. Then, the masking material layer 810 is subjected to non-masked anisotropic etching (e.g., dry etching), and the masking material layer 810 except for the sidewall of the contact material layer 310 is etched away due to the thickness T of the masking material layer 810 at the corner of the step ₁ Greater than the thickness T of the masking material layer 810 at the level of the step ₂ After a certain etching time, a part of the mask material layer 810 remains at the step corner, and the mask layer 800 is formed.

At this time, the mask layer 800 is located at the sidewall of the step formed by the contact material layer 310.

In this embodiment, the mask layer 800 is formed without photolithography, so that one photomask process can be saved. Of course, in other embodiments, the forming manner of the mask layer 800 is not limited thereto.

In one embodiment, referring to fig. 8, step S231 includes:

step S2311b, forming a mask material layer 810 on the surface of the contact material layer 310;

step S2312b, forming a patterned photoresist on the surface of the mask material layer 810;

in step S2313b, a mask layer 800 is formed based on the patterned photoresist.

A masking material layer 810 may be first formed on the contact material layer 310, the masking material layer 810 completely covering the contact material layer 310. Then, a patterned photoresist is formed on the surface of the mask material layer 810. Specifically, a photoresist may be coated on the surface of the mask material layer 810. The photoresist may be either positive or negative. Then, the photoresist is exposed and developed through a corresponding photomask to form a patterned photoresist. Thereafter, the mask material layer 810 is etched based on the patterned photoresist, forming a mask layer 800. When the selected photoresist is positive photoresist, the mask layer 800 is opposite to the shading area of the photomask; when the selected photoresist is negative photoresist, the mask layer 800 is opposite to the light-transmitting region of the mask (see fig. 8).

At this time, the mask layer 800 may also be located at a sidewall of the contact material layer 310. Of course, a space may be provided between the mask layer 800 and the sidewall of the contact material layer 310, which is not limited herein.

In one embodiment, step S210 includes:

in step S211, the substrate 100 is etched to form a plurality of continuous steps exposing each of the capacitor electrode layers 200, and for the adjacent capacitor electrode layers 200, the bottom surface of the step exposing the upper capacitor electrode layer 200 is the top surface of the step exposing the lower capacitor electrode layer 200.

At this time, the capacitive structure may include a plurality of capacitive electrode layers 200 and a capacitive dielectric layer between adjacent capacitive electrode layers 200. And the substrate 100 may include an insulating dielectric layer 600 covering the capacitor structure.

When the capacitor structure includes a plurality of capacitor electrode layers 200, the substrate 100 may be etched to gradually expose each capacitor electrode layer 200, and after each capacitor electrode layer 200 is exposed, a step is formed, and a plurality of capacitor electrode layers 200 are etched to form a plurality of continuous steps. For adjacent capacitance electrode layers 200, the bottom surface of the step exposing the upper capacitance electrode layer 200 is the top surface of the step exposing the lower capacitance electrode layer 200.

As an example, referring to fig. 10, the capacitor structure includes a first capacitor electrode layer 210, a first capacitor dielectric layer 510, a second capacitor electrode layer 220, a second capacitor dielectric layer 520, and a third capacitor electrode layer 230 that are stacked in order. The substrate 100 further includes an insulating dielectric layer 600 covering the capacitive structures. The insulating dielectric layer 600 is located on the upper surface of the third capacitor electrode layer 230.

When the substrate 100 is etched, a first patterned photoresist 910 may be formed on the insulating dielectric layer 600, and the insulating dielectric layer 600 is etched based on the first patterned photoresist 910 to form a first step, where the bottom surface of the first step exposes the third capacitor electrode layer 230. The first patterned photoresist 910 is then removed.

Next, a second patterned photoresist 920 is formed on the insulating dielectric layer 600 and the third capacitor electrode layer 230, and the third capacitor electrode layer 230 and the second capacitor dielectric layer 520 are etched based on the second patterned photoresist 920, so as to form a second step, wherein the top surface of the second step is the third capacitor electrode layer 230, and the bottom surface of the second step is the second capacitor electrode layer 220. The second patterned photoresist 920 is then removed.

Finally, a third patterned photoresist 930 is formed on the insulating dielectric layer 600, the third capacitive electrode layer 230, and the second capacitive electrode layer 220. At this time, the side of the second capacitive dielectric layer 520 is also covered by the third patterned photoresist 930. Based on the third patterned photoresist 930, the second capacitor electrode layer 220 and the first capacitor dielectric layer 510 are etched to form a third step, where the top surface of the third step is the second capacitor electrode layer 220 and the bottom surface is the first capacitor electrode layer 210. Then, the third patterned photoresist 930 is removed.

For the adjacent capacitive electrode layer 200, the bottom surface of the step exposing the upper capacitive electrode layer 200 is the top surface of the step exposing the lower capacitive electrode layer 200, e.g., the bottom surface of the first step exposing the third capacitive electrode layer 230 is the top surface of the second step exposing the second capacitive electrode layer 220. For another example, a bottom surface of the second step exposing the second capacitive electrode layer 220 is a top surface of the third step exposing the first capacitive electrode layer 210.

In other embodiments, the steps within the substrate 100 exposing the capacitive electrode layers 200 may also be located in different directions, so as to be discontinuous. For example, when the number of the capacitor electrode layers 200 is two, two steps of the etching substrate 100 exposing the capacitor electrode layers 200, respectively, may be located at both sides of the capacitor trench, respectively. For another example, when the number of the capacitor electrode layers 200 is three, the etching substrate 100 exposes three steps formed by the capacitor electrode layers 200, respectively, and the three steps may be located at left, right, and front sides of the capacitor trench, respectively. At this time, the top surface of each step is the upper surface of the insulating dielectric layer 600.

In one embodiment, step S232 includes:

in step S232a, the contact electrode 320 is formed by etching the contact material layer 310 and each capacitor electrode layer 200 based on the mask layer 800 and using the insulating dielectric layer 600 and the capacitor dielectric layer as etching stop layers.

The insulating dielectric layer 600 and the capacitor dielectric layer are used as etching stop layers, and the contact material layer 310 and the capacitor electrode layers 200 are etched based on the mask layer 800, so that a plurality of contact electrodes 320 separated from each other can be formed. After that, the contact electrode 320 is aligned with the capacitor electrode layer 200 where it is located, on the side away from the sidewall of the step where it is located.

As an example, the capacitor structure includes a first capacitor electrode layer 210, a first capacitor dielectric layer 510, a second capacitor electrode layer 220, a second capacitor dielectric layer 520, and a third capacitor electrode layer 230 that are sequentially stacked. And the third capacitive electrode layer 230 has an insulating dielectric layer 600 on its upper surface.

Step S211 etches the substrate 100 to form a plurality of continuous steps, which expose the plurality of capacitor electrode layers 200. Step S220 forms the contact material layer 310 on a plurality of consecutive steps. At this time, the first, second and third capacitive electrode layers 210, 220, 230 are all covered by the contact material layer 310. When the contact material layer 310 and the first capacitance electrode layer 210 are etched based on the mask layer 800, the first capacitance dielectric layer 510 may be used as an etching stop layer, thereby forming the first contact electrode 321. When the contact material layer 310 and the second capacitor electrode layer 220 are etched based on the mask layer 800, the second capacitor dielectric layer 520 may be used as an etch stop layer, thereby forming the second contact electrode 322. When the contact material layer 310 and the third capacitor electrode layer 230 are etched based on the mask layer 800, the insulating dielectric layer 600 may be used as an etch stop layer, thereby forming the third contact electrode 323.

After that, the first contact electrode 321 is aligned with the first capacitive electrode layer 210 where it is located on a side away from the step sidewall where the first contact electrode 320 is located. The second contact electrode 322 is aligned with the second capacitive electrode layer 220 where it is located on a side of the step sidewall remote from where the second contact electrode 322 is located. The third electrode is aligned with the third capacitive electrode layer 230 where it is located on a side of the step sidewall away from where the third contact electrode 323 is located. In other words, the orthographic projections of the first contact electrode 321, the second contact electrode 322, and the third contact electrode 323 do not exceed the orthographic projections of the first capacitive electrode layer 210, the second capacitive electrode layer 220, and the third capacitive electrode layer 230 where they are located.

In this embodiment, each of the capacitor electrode layers 200 is etched to prevent the adjacent two contact electrodes 320 from being shorted. In addition, the insulating dielectric layer 600 and each capacitance dielectric layer are used as etching stop layers, so that mutual independence between the contact electrodes 320 is ensured, and the short circuit between two adjacent contact electrodes 320 is further avoided.

In one embodiment, the contact material layer 310 at the sidewall of the step may be partially left so that the contact electrode 320 may have a step shape.

At this time, the thickness of the contact electrode 320 on the side close to the side wall of the step where the contact electrode is located is smaller than that on the side far from the side wall of the step where the contact electrode is located, in other words, the step shape of the contact electrode 320 is opposite to that of the step where the contact electrode is located, and the two steps face opposite. The contact area between the step-shaped contact electrode 320 and the capacitor electrode layer 200 increases, and the contact resistance between the two decreases.

For example, the capacitor structure includes a first capacitor electrode layer 210, a first capacitor dielectric layer 510, a second capacitor electrode layer 220, a second capacitor dielectric layer 520, and a third capacitor electrode layer 230 that are stacked in order. The third capacitive electrode layer 230 is covered with an insulating dielectric layer 600. After the substrate 100 is etched, a plurality of continuous steps are formed, and the plurality of steps expose the plurality of capacitive electrode layers 200, respectively. The contact electrodes 320 are formed on a plurality of consecutive steps, respectively. The first contact electrode 321 is located on the first capacitor electrode layer 210, and the contact material layer 310 on the side of the first contact electrode 321 near the side wall of the third step may be partially retained, so that the first contact electrode 321 has a step shape, where the step shape and the third step are disposed opposite to each other, and the steps face opposite to each other. The second contact electrode 322 is located on the second capacitor electrode layer 220, and the contact material layer 310 on the side of the second contact electrode 322 near the second step sidewall may be partially retained, so that the second contact electrode 322 has a step shape, where the step shape is opposite to the second step, and the steps are opposite to each other. The third contact electrode 323 is disposed on the third capacitor electrode layer 230, and the contact material layer 310 of the third contact electrode 323 on a side close to the sidewall of the first step may be partially retained, so that the third contact electrode 323 has a step shape disposed opposite to the first step, and the steps are opposite to each other.

In other embodiments, the contact electrode 320 may also be rectangular, in which case the contact material layer 310 on the sidewall of the step is completely etched away.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

With continued reference to fig. 9, in one embodiment there is also provided a semiconductor structure comprising: the substrate 100, the contact electrode 320, and the conductive structure 400.

The substrate 100 includes a capacitive structure including a capacitive electrode layer 200.

As an example, the substrate 100 may have a trench therein, and the capacitor structure may be a trench capacitor. At this time, the base 100 may include a semiconductor substrate and a protective dielectric layer 700 on the semiconductor substrate. Meanwhile, the trench may extend longitudinally from the protective dielectric layer 700 into the semiconductor substrate. The capacitor structure may extend laterally from within the trench to outside the trench. The capacitor structure may be covered with an insulating dielectric layer 600.

The capacitive electrode layer 200 may include a capacitive portion and a terminal portion. The capacitor portion may be located within the trench of the substrate 100 and disposed along the inner wall of the trench. The terminal portion is connected to the capacitor portion, which may be located outside the trench. For example, the terminal portion may be located on an upper surface of the protective dielectric layer 700 outside the trench.

The contact electrode 320 is positioned on the capacitive electrode layer 200 to contact the capacitive electrode layer 200. The material of the contact electrode 320 may be selected to be tungsten. When the capacitive electrode layer 200 includes a capacitive portion and a terminal portion, the contact electrode 320 may be formed on the terminal portion of the capacitive electrode layer 200 to be in contact with the terminal portion.

The conductive structure 400 is located on the contact electrode 320 so as to be connected to the upper layer wiring structure.

As an example, a plurality of re-wiring layers may be over the contact electrode 320. An interlayer dielectric layer may be formed between the re-wiring layer and the contact electrode 320 and between adjacent re-wiring layers.

The conductive structure 400 may be formed between the redistribution layer and the contact electrode 320 by penetrating one or more interlayer dielectric layers, and the contact electrode 320 is connected to the redistribution layer, so that the capacitor structure is used as a decoupling capacitor.

In forming the conductive structure 400, a contact hole may be formed on the contact electrode 320 first, and then the contact hole may be filled to form the conductive structure 400.

In one embodiment, referring to fig. 9, the substrate 100 may have a step exposing the capacitor electrode layer 200, and the contact electrode 320 is located at the bottom surface of the step.

In one embodiment, the number of capacitive electrode layers 200 may be plural. At this time, a capacitance dielectric layer is disposed between two adjacent capacitance electrode layers 200. The substrate 100 further includes an insulating dielectric layer 600, where the insulating dielectric layer 600 covers the capacitor structure to isolate the capacitor structure from the outside. At this time, the substrate 100 may have a plurality of continuous steps exposing the respective capacitive electrode layers 200.

As an example, the number of the capacitive electrode layers 200 may be three, and in this case, the number of the capacitive dielectric layers is two. The first capacitive electrode layer 210, the second capacitive electrode layer 220, and the first capacitive dielectric layer 510 may have a third step. The second capacitive electrode layer 220, the third capacitive electrode layer 230, and the second capacitive dielectric layer 520 may have a second step. The third capacitive electrode layer 230 and the insulating dielectric layer 600 may have a first step.

The top surface and the side wall of the first step may be an insulating dielectric layer 600, and the bottom surface of the first step may expose the top capacitive electrode layer 200, that is, the third capacitive electrode layer 230. The top surface of the second step may be the third capacitor electrode layer 230, the sidewall may be the third capacitor electrode layer 230 and the second capacitor dielectric layer 520, and the bottom surface may be the second capacitor electrode layer 220. The third step may have a top surface of the second capacitor electrode layer 220, a sidewall of the third step may be the second capacitor electrode and the first capacitor dielectric layer 510, and a bottom surface of the third step may be the first capacitor electrode layer 210.

In this embodiment, the steps are continuous, so that the process of forming the contact electrode 320 and the subsequent conductive structure 400 is simple, and the process efficiency is improved.

In other embodiments, the steps within the substrate 100 exposing the capacitive electrode layers 200 may also be located in different directions, so as to be discontinuous. For example, when the number of the capacitance electrode layers 200 is two, two steps may be located at both sides of the capacitance trench, respectively. For another example, when the number of the capacitance electrode layers 200 is three, three steps may be located at the left, right, and front sides of the capacitance trench, respectively. At this time, the top surface of each step is the upper surface of the insulating dielectric layer 600.

In one embodiment, the contact electrode 320 is aligned with the capacitive electrode layer 200 where it is located on a side away from the sidewall of the step where it is located.

In one embodiment, the contact electrode 320 is stepped and has a smaller thickness on a side closer to the sidewall of the step than on a side farther from the sidewall of the step. In other words, the contact electrode 320 has a step shape opposite to the step shape where the contact electrode is located, and the steps are opposite to each other.

In the present embodiment, the contact area between the stepped contact electrode 320 and the capacitor electrode layer 200 increases, and the contact resistance therebetween decreases.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a contact electrode on the capacitance electrode layer;

forming a contact electrode, and then forming a contact hole on the contact electrode;

forming a conductive structure in the contact hole;

after the contact electrode is formed, forming a rewiring layer, and forming an interlayer dielectric layer between the rewiring layer and the contact electrode;

the forming a contact hole on the contact electrode further includes: forming a contact hole penetrating through the interlayer dielectric layer;

after the conductive structure is formed in the contact hole, the conductive structure connects the contact electrode with the rewiring layer to be connected.

2. The method of claim 1, wherein forming a contact electrode on the capacitor electrode layer comprises:

and etching the contact material layer to form the contact electrode.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein etching the contact material layer to form the contact electrode comprises:

4. The method of manufacturing a semiconductor structure according to claim 3, wherein forming a mask layer on the contact material layer on the bottom surface of the step comprises:

forming a mask material layer on the surface of the contact material layer;

5. The method of manufacturing a semiconductor structure according to claim 3, wherein forming a mask layer on the contact material layer on the bottom surface of the step comprises:

forming a mask material layer on the surface of the contact material layer;

forming patterned photoresist on the surface of the mask material layer;

and forming the mask layer based on the patterned photoresist.

6. The method of manufacturing a semiconductor structure according to claim 3, wherein,

the capacitive structure comprises a plurality of capacitive electrode layers and a capacitive dielectric layer positioned between adjacent capacitive electrode layers, and the substrate comprises an insulating dielectric layer covering the capacitive structure;

7. The method for manufacturing a semiconductor structure according to claim 6, wherein etching the contact material layer based on the mask layer to form the contact electrode comprises:

8. The method of claim 7, wherein the contact material layer on the sidewall of the step is partially preserved such that the contact electrode is stepped.

9. The method of manufacturing a semiconductor structure according to any one of claims 1 to 8, wherein the substrate has a trench therein, the capacitor electrode layer includes a capacitor portion and a terminal portion connected to each other, the capacitor portion is disposed along an inner wall of the trench, and the terminal portion is located outside the trench;

the forming a contact electrode on the capacitor electrode layer includes:

the contact electrode is formed on the terminal portion.

10. A semiconductor structure, comprising:

a contact electrode on the capacitive electrode layer;

a conductive structure located on the contact electrode;

the semiconductor structure further comprises an interlayer dielectric layer, a contact hole and a rewiring layer, wherein the interlayer dielectric layer is positioned between the rewiring layer and the contact electrode and between the adjacent rewiring layers, the contact hole is positioned in the interlayer dielectric layer on the contact electrode and penetrates through the contact electrode, the conductive structure is positioned in the contact hole, and the rewiring layer is positioned above the conductive structure.

11. The semiconductor structure of claim 10, wherein the substrate has a step exposing the capacitive electrode layer, the contact electrode being located at a bottom surface of the step.

12. The semiconductor structure of claim 11, wherein,

the capacitor structure comprises a plurality of capacitor electrode layers and a capacitor dielectric layer positioned between the adjacent capacitor electrode layers, the substrate comprises an insulating dielectric layer covering the capacitor structure,

13. The semiconductor structure of claim 12, wherein the contact electrode is aligned with the capacitive electrode layer on which it is located on a side away from the step sidewall on which it is located.

14. The semiconductor structure of claim 13, wherein the contact electrode is stepped and has a smaller thickness on a side closer to the step sidewall than on a side farther from the step sidewall.

15. The semiconductor structure of any one of claims 10-14, wherein the substrate has a trench therein, the capacitive electrode layer includes interconnected capacitive portions disposed along inner walls of the trench and terminal portions located outside the trench, the contact electrode being located on the terminal portions.