CN112185888B - MIM capacitor and forming method thereof - Google Patents

MIM capacitor and forming method thereof Download PDF

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CN112185888B
CN112185888B CN202010958494.XA CN202010958494A CN112185888B CN 112185888 B CN112185888 B CN 112185888B CN 202010958494 A CN202010958494 A CN 202010958494A CN 112185888 B CN112185888 B CN 112185888B
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layer
etching
electrode layer
protective layer
capacitor dielectric
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CN112185888A (en
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马莉娜
姚道州
肖培
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1052—Formation of thin functional dielectric layers

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a forming method of an MIM capacitor and the MIM capacitor, wherein the method comprises the following steps: forming a protective layer on the exposed surfaces of the second electrode layer, the capacitor dielectric layer and the first electrode layer, wherein the second electrode layer is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the first electrode layer, and the first electrode layer, the capacitor dielectric layer and the second electrode layer form a first step-shaped structure; etching the protective layer for the first time, and thinning the protective layer; etching the protective layer for the second time, removing the protective layer on the second electrode layer and thinning the protective layer; and etching the protective layer for the third time to enable the outer edge of the section of the protective layer to be arc-shaped, and enabling the rest protective layer to form the side wall. According to the method, the side wall with the arc-shaped outer surface is formed on the peripheral sides of the upper electrode of the MIM capacitor and the capacitor dielectric layer to protect the capacitor dielectric layer, so that the probability that the capacitor dielectric layer is damaged by plasma in the subsequent etching process is reduced, and the reliability of the device is improved.

Description

MIM capacitor and forming method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a forming method and a device of an MIM capacitor.
Background
Capacitive elements are often used in integrated circuits such as radio frequency, monolithic microwave, etc. as electronic passive devices. Common capacitor elements include metal-oxide-semiconductor (MOS) capacitors, PN junction (positive negative junction) capacitors, metal-insulator-metal (MIM) capacitors, and the like.
The MIM capacitor can provide electrical characteristics superior to MOS capacitors and PN junction capacitors in some special applications, because the MOS capacitors and the PN junction capacitors are limited by their structures, and when operating, the electrodes easily generate a hole layer, which reduces the frequency characteristics, and the MIM capacitor can provide better frequency and temperature-related characteristics. In addition, MIM capacitors can be formed in the interlayer metal and metal interconnect processes during semiconductor fabrication, which also reduces the difficulty and complexity of integration with front-end processes in integrated circuit fabrication.
In the related art, in the manufacturing process of the MIM capacitor, after the capacitor dielectric layer is etched, an etch stop layer is formed, and after the etch stop layer is etched, because the capacitor dielectric layer has a thin thickness, the edge of the capacitor dielectric layer is easily damaged by plasma to a great extent in the etching process, and a defect (plasma Damage) is formed, so that the Time Dependent Dielectric Breakdown (TDDB) problem of the device is caused, and the reliability is poor.
Disclosure of Invention
The application provides a forming method of an MIM capacitor and the MIM capacitor, and can solve the problem that a capacitor dielectric layer of the MIM capacitor is damaged by plasma easily due to a manufacturing method of the MIM capacitor in the related technology, so that the reliability is poor.
In one aspect, an embodiment of the present application provides a method for forming an MIM capacitor, including:
forming a protective layer on exposed surfaces of a second electrode layer, a capacitor dielectric layer and a first electrode layer, wherein the second electrode layer is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the first electrode layer, the capacitor dielectric layer and the second electrode layer form a first step-shaped structure, the capacitor dielectric layer forms a second step-shaped structure, the second step-shaped structure comprises a high step part and a low step part, the high step part and the second electrode layer form an upper step of the first step-shaped structure, and the low step part and the first electrode layer form a lower step of the first step-shaped structure;
etching the protective layer for the first time, and thinning the protective layer;
etching the protective layer for the second time, removing the protective layer on the second electrode layer and thinning the protective layer;
and etching the protective layer for the third time to enable the outer edge of the cross section of the protective layer to be arc-shaped, and forming side walls on the periphery sides of the second electrode layer and the capacitor dielectric layer by the rest protective layer.
Optionally, the protective layer comprises a silicon nitride (SiN) layer.
Optionally, the flow rate of the reaction gas for the first etching is a first flow rate, the flow rate of the reaction gas for the second etching is a second flow rate, and the first flow rate is greater than the second flow rate;
the power of the second etching is first power, the power of the third etching is second power, and the second power is smaller than the first power;
the air pressure of the second etching is first air pressure, the power of the third etching is second air pressure, and the second air pressure is smaller than the first air pressure.
Optionally, the reaction gas for the first etching includes C x1 F y1 。
Optionally, the reaction gas for the second etching includes CH x2 F y2 。
Optionally, the first flow rate is 200 standard status milliliters per minute (SCCM) to 400 SCCM.
Optionally, the second flow rate is 30 to 60 SCCM.
Optionally, the first power is 1000 watts (W) to 1500 watts.
Optionally, the second power is 200 watts to 400 watts.
Optionally, the first gas pressure is 80 mTorr to 150 mTorr.
Optionally, the second gas pressure is 30 mtorr to 60 mtorr.
In another aspect, an embodiment of the present application provides a MIM capacitor, including:
a first electrode layer;
the capacitance dielectric layer is formed on the first electrode layer;
the second electrode layer is formed on the capacitance medium layer;
the capacitor comprises a first electrode layer, a capacitor dielectric layer, a second electrode layer and a side wall, wherein the first electrode layer, the capacitor dielectric layer and the second electrode layer form a first step-shaped structure, the capacitor dielectric layer and the second electrode layer form an upper step of the first step-shaped structure, the first electrode layer forms a lower step of the first step-shaped structure, the side wall is formed on the periphery of the upper step, and the outer surface of the side wall is arc-shaped.
Optionally, the sidewall spacer includes silicon nitride.
Optionally, the capacitor dielectric layer includes silicon nitride.
Optionally, the first electrode layer sequentially includes an aluminum layer, a titanium layer, and a first titanium nitride layer from bottom to top;
the second electrode layer includes a second titanium nitride layer.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the MIM capacitor, after the MIM capacitor thin film is etched, the protective layer is formed on the surface of the MIM capacitor, the protective layer is etched for three times, and the side wall with the arc-shaped outer surface is formed on the peripheral side of the upper electrode and the capacitor dielectric layer of the MIM capacitor to protect the capacitor dielectric layer, so that the probability that the capacitor dielectric layer is damaged by plasma in the subsequent etching process is reduced, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart of a method of forming a MIM capacitor according to an exemplary embodiment of the present application;
fig. 2 to 6 are schematic diagrams illustrating a process of forming a MIM capacitor according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for forming a MIM capacitor according to an exemplary embodiment of the present application is shown, the method including:
step 101, forming a protective layer on exposed surfaces of a second electrode layer, a capacitor dielectric layer and a first electrode layer, wherein the second electrode layer is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the first electrode layer, the capacitor dielectric layer and the second electrode layer form a first step-shaped structure, the capacitor dielectric layer forms a second step-shaped structure, the second step-shaped structure comprises a high step part and a low step part, the high step part and the second electrode layer form an upper step of the first step-shaped structure, and the low step part and the first electrode layer form a lower step of the first step-shaped structure.
Referring to fig. 2, a schematic cross-sectional view of the MIM capacitor multilayer film after etching before step 101 is shown; referring to fig. 3, a schematic cross-sectional view of the protective layer formed on the exposed surfaces of the second electrode layer, the capacitor dielectric layer and the first electrode layer is shown.
As shown in fig. 2, the MIM capacitor multilayer film sequentially includes, from bottom to top, a first electrode layer 210 (the first electrode layer 210 may be used as a lower electrode of a formed MIM capacitor), a capacitor dielectric layer 220 formed on the first electrode layer 210, and a second electrode layer 230 formed on the capacitor dielectric layer 220 (the second electrode layer 230 may be used as an upper electrode of a formed MIM capacitor), a target region (as shown by a dotted line in fig. 2) is etched until a target depth in the capacitor dielectric layer 220 of the target region is reached, the second electrode layer 230 and the capacitor dielectric layer 220 of the target region are etched away, the remaining first electrode layer 210, the capacitor dielectric layer 220, and the second electrode layer 230 form a first step structure, the remaining capacitor dielectric layer 220 forms a second step structure, the second step structure includes a high step portion and a low step portion, the high step portion and the second electrode layer 230 form an upper step of the first step structure, the low step portion and the first electrode layer 210 constitute a lower step of the first step-type structure.
Optionally, in this embodiment, the first electrode layer 210 includes, from bottom to top, an aluminum (Al) layer 211, a titanium (Ti) layer 212, and a first titanium nitride (TiN) layer 213 in sequence, and the second electrode layer 230 includes a second titanium nitride layer; optionally, the capacitor dielectric layer 220 comprises silicon nitride.
Optionally, in the present embodiment, the thickness of the titanium (Ti) layer 212 is 50 to 500 angstroms; optionally, the thickness of the first titanium nitride layer 213 is 200 angstroms
Figure BDA0002679467810000051
To 2000 angstroms; optionally, the thickness of the capacitor dielectric layer 220 is 50 angstroms to 1000 angstroms; optionally, the second titanium nitride layer has a thickness of 500 to 3000 angstroms.
Optionally, as shown in fig. 3, the protection layer 240 includes silicon nitride, and the protection layer 240 may be formed on the surface of the first step-type structure by Chemical Vapor Deposition (CVD). Optionally, in the embodiment of the present application, the thickness of the protection layer 240 is 500 angstroms to 2000 angstroms.
And 102, etching the protective layer for the first time, and thinning the protective layer.
Referring to fig. 4, a schematic cross-sectional view of a first etching of the protective layer is shown. As shown in fig. 4, the protective layer 240 is thinned by the first etching, and corners of the protective layer 240 are formed to have a shape with a certain curvature.
And 103, etching the protective layer for the second time, and thinning the protective layer while removing the protective layer on the second electrode layer.
Referring to fig. 5, a schematic cross-sectional view of a second etching of the protective layer is shown. As shown in fig. 5, the protective layer 240 on the second electrode layer 220 is removed, and the protective layer 240 in other regions is thinned.
And 104, etching the protective layer for the third time to enable the outer edge of the cross section of the protective layer to be arc-shaped, and forming a side wall on the periphery of the second electrode layer and the capacitor dielectric layer by the residual protective layer.
Referring to fig. 6, a schematic cross-sectional view of a third etching of the protective layer is shown. As shown in fig. 6, the protective layer 240 on the first electrode layer 210 is removed, and the remaining protective layer 230 forms a sidewall on the periphery of the second electrode layer 230 and the capacitor dielectric layer 220, wherein the outer edge of the cross section of the sidewall is arc-shaped. After the step 104, a predetermined region of the first electrode layer 210 is exposed, the capacitor dielectric layer 220 and the second electrode layer 230 constitute an upper step of a first step-type structure, and the first electrode layer 210 constitutes a lower step of the first step-type structure.
The applicant finds that when the protective layer is etched, the protective layer on the upper electrode and the lower electrode needs to be etched cleanly, and the protective layer is easy to be etched transversely, so that a side digging phenomenon (namely, the edge of the capacitor dielectric layer is sunken) can occur at a certain probability after etching, or the cross section of the formed side wall is an oblique angle, and the protective strength of the side wall with the shape on the capacitor dielectric layer is small.
In view of this, in the embodiment of the application, the protective layer is etched for three times, and the side wall with the arc-shaped outer surface is formed on the peripheral side of the upper electrode of the MIM capacitor and the capacitor dielectric layer, so that on the basis of protecting the capacitor dielectric layer, the protection strength of the side wall on the capacitor dielectric layer is improved, the probability that the capacitor dielectric layer is damaged by plasma in the subsequent etching process is reduced, and the reliability of the device is improved.
Optionally, in this embodiment of the application, the flow rate of the reaction gas for the first etching is a first flow rate, the flow rate of the reaction gas for the second etching is a second flow rate, and the first flow rate is greater than the second flow rate; the power of the second etching is the first power, the power of the third etching is the second power, and the second power is smaller than the first power; the air pressure of the second etching is the first air pressure, the power of the third etching is the second air pressure, and the second air pressure is smaller than the first air pressure.
In the first etching process, the protective layer 240 is quickly thinned at a higher etching rate through a larger flow; in the second etching process, the protective layer 240 on the second electrode layer 230 is etched cleanly at a slower etching speed through a smaller flow, a higher power meter and air pressure, so that a process window can be increased; in the third etching process, the appearance of the outer surface of the protective layer 240 is modified by low power and air pressure to form an arc shape.
Optionally, the reaction gas for the first etching includes C x1 F y1 (wherein C is carbon, F is fluorine, x1, y1 are natural numbers); the reaction gas for the second etching comprises CH x2 F y2 (wherein, H is hydrogen element, x2, y2 are natural numbers); optionally, the first flow rate is 200SCCM to 400 SCCM; optionally, the second flow rate is 30 to 60 SCCM.
Optionally, the first power is 1000 w to 1500 w; optionally, the second power is 200 w to 400 w; optionally, the first pressure is 80 mtorr to 150 mtorr; optionally, the second pressure is 30 mtorr to 60 mtorr.
To sum up, in the embodiment of the application, in the manufacturing process of the MIM capacitor, after the MIM capacitor thin film is etched, the protective layer is formed on the surface of the MIM capacitor, the protective layer is etched for three times, and the side wall with the arc-shaped outer surface is formed on the peripheral sides of the upper electrode and the capacitor dielectric layer of the MIM capacitor to protect the capacitor dielectric layer, so that the probability that the capacitor dielectric layer is damaged by plasma in the subsequent etching process is reduced, and the reliability of the device is improved.
Referring to fig. 6, a schematic cross-sectional view of a MIM capacitor according to an exemplary embodiment of the present application is shown, which can be fabricated according to any of the above embodiments, and includes:
the first electrode layer 210.
A capacitor dielectric layer 220 formed on the first electrode layer 210.
And a second electrode layer 230 formed on the capacitor dielectric layer 220.
The first electrode layer 210, the capacitor dielectric layer 220 and the second electrode layer 230 form a first step structure, the capacitor dielectric layer 220 and the second electrode layer 230 form an upper step of the first step structure, the first electrode layer 210 forms a lower step of the first step structure, a side wall 240 is formed on the peripheral side of the upper step, and the outer surface of the side wall 240 is arc-shaped.
Optionally, in this embodiment of the application, the first electrode layer 210 includes, from bottom to top, an aluminum layer 211, a titanium layer 212, and a first titanium nitride layer 213 in sequence, and the second electrode layer 230 includes a second titanium nitride layer; optionally, the capacitor dielectric layer 220 comprises silicon nitride.
Optionally, in the embodiment of the present application, the thickness of the titanium layer 212 is 50 angstroms to 500 angstroms; optionally, the thickness of the first titanium nitride layer 213 is 200 to 2000 angstroms; optionally, the thickness of the capacitor dielectric layer 220 is 50 angstroms to 1000 angstroms; optionally, the second titanium nitride layer has a thickness of 500 to 3000 angstroms.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention are intended to be covered by the present invention.

Claims (11)

1. A method for forming an MIM capacitor, comprising:
forming a protective layer on exposed surfaces of a second electrode layer, a capacitor dielectric layer and a first electrode layer, wherein the second electrode layer is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the first electrode layer, the capacitor dielectric layer and the second electrode layer form a first step-shaped structure, the capacitor dielectric layer forms a second step-shaped structure, the second step-shaped structure comprises a high step part and a low step part, the high step part and the second electrode layer form an upper step of the first step-shaped structure, and the low step part and the first electrode layer form a lower step of the first step-shaped structure;
etching the protective layer for the first time, and thinning the protective layer;
etching the protective layer for the second time, removing the protective layer on the second electrode layer and thinning the protective layer;
and etching the protective layer for the third time to enable the outer edge of the cross section of the protective layer to be arc-shaped, and forming side walls on the periphery sides of the second electrode layer and the capacitor dielectric layer by the rest protective layer.
2. The method of claim 1, wherein the protective layer comprises a silicon nitride layer.
3. The method according to claim 2, wherein the flow rate of the reaction gas for the first etching is a first flow rate, the flow rate of the reaction gas for the second etching is a second flow rate, and the first flow rate is greater than the second flow rate;
the power of the second etching is first power, the power of the third etching is second power, and the second power is smaller than the first power;
the air pressure of the second etching is first air pressure, the power of the third etching is second air pressure, and the second air pressure is smaller than the first air pressure.
4. The method of claim 3, wherein the reactive gas of the first etching comprises C x1 F y1 。
5. The method of claim 4, wherein the reactive gas of the second etching comprises CH x2 F y2 。
6. The method of claim 5, wherein the first flow is 200 to 400 SCCM.
7. The method of claim 6, wherein the second flow is 30 to 60 SCCM.
8. The method of claim 7, wherein the first power is 1000 watts to 1500 watts.
9. The method of claim 8, wherein the second power is 200 watts to 400 watts.
10. The method of claim 9, wherein the first pressure is 80 mtorr to 150 mtorr.
11. The method of claim 10, wherein the second gas pressure is 30 mtorr to 60 mtorr.
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CN108417565A (en) * 2018-02-05 2018-08-17 上海华虹宏力半导体制造有限公司 The process of MIM capacitor
CN111517272A (en) * 2020-04-01 2020-08-11 上海华虹宏力半导体制造有限公司 Method for preparing electrode

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108417565A (en) * 2018-02-05 2018-08-17 上海华虹宏力半导体制造有限公司 The process of MIM capacitor
CN111517272A (en) * 2020-04-01 2020-08-11 上海华虹宏力半导体制造有限公司 Method for preparing electrode

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