CN111517272A - Method for preparing electrode - Google Patents
Method for preparing electrode Download PDFInfo
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- CN111517272A CN111517272A CN202010248291.1A CN202010248291A CN111517272A CN 111517272 A CN111517272 A CN 111517272A CN 202010248291 A CN202010248291 A CN 202010248291A CN 111517272 A CN111517272 A CN 111517272A
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- layer
- etching
- metal layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00166—Electrodes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application discloses a preparation method of an electrode, which comprises the following steps: providing a substrate; sequentially forming a first oxide layer, an amorphous silicon layer, a metal layer and a dielectric anti-reflection layer on a substrate; carrying out first etching to remove the dielectric antireflection layer of the target area and the metal layer with the preset depth in the target area to form a first through hole; performing second etching to thin the dielectric antireflection layer and the exposed metal layer to form a second through hole; carrying out third etching to remove the metal layer in the target area and expose the amorphous silicon layer; and forming a second oxide layer on the surfaces of the exposed dielectric antireflection layer and the amorphous silicon layer. According to the method, the dielectric antireflection layer in the target area is removed through the first etching, the dielectric antireflection layer and the exposed metal layer are thinned through the second etching, and the metal layer in the target area is removed through the third etching, so that the subsequent oxide layer deposition is carried out, and the problem of low yield caused by the formation of an electrode through a wet etching process is solved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a preparation method of an electrode of a Micro-Electro-Mechanical System (MEMS) sensor.
Background
Amorphous silicon (α -Si) is an allotrope of silicon, which can be deposited in the form of a thin film on various substrates, provides specific functions for various electronic applications, and is widely used in the fields of mass-produced MEMS, Nano-Electromechanical systems (NEMS), solar cells, microcrystalline silicon, and micro-amorphous silicon. The following is an exemplary description of the application of amorphous silicon to MEMS sensors:
referring to fig. 1, a schematic top view of a MEMS sensor provided in the related art is shown. As shown in fig. 1, the MEMS sensor includes a substrate 101, and a sensing region 110, an electrode 120, a conductive line 130, and a pad 140 formed on the substrate 101, wherein the sensing region 110 is led out to the pad 140 through the electrode 120 and the conductive line 130. Wherein the sensing region 110 and the electrode 120 comprise an amorphous silicon layer.
However, in the related art, in the manufacturing process of the electrode of the MEMS sensor, the photoresist peeling phenomenon occurs when the electrode is wet etched, which results in poor device morphology and low yield.
Disclosure of Invention
The application provides a preparation method of an electrode, which can solve the problems of poor appearance and low yield caused by the preparation method of the electrode of the MEMS sensor in the related technology.
In one aspect, an embodiment of the present application provides a method for preparing an electrode, where the method is applied to preparing an electrode of a MEMS sensor, and the method includes:
providing a substrate;
sequentially forming a first oxide layer, an amorphous silicon layer, a metal layer and a dielectric anti-reflection layer (DARC) on the substrate;
carrying out first etching, removing the dielectric antireflection layer of a target area and the metal layer with a preset depth in the target area to form a first through hole, wherein the target area is an area where an electrode is not required to be formed;
performing second etching to thin the dielectric antireflection layer and the exposed metal layer to form a second through hole;
carrying out third etching to remove the metal layer in the target area and expose the first oxide layer;
and forming a second oxide layer on the surfaces of the exposed dielectric antireflection layer, the amorphous silicon layer and the first oxide layer.
Optionally, the performing the first etching to remove the dielectric antireflection layer in the target region and the metal layer with the predetermined depth in the target region includes:
covering a photoresist on the surface of the dielectric antireflection layer;
exposing and developing the light resistance of the target area, and then removing the light resistance of the target area;
performing the first etching through a dry etching process or a wet etching process to remove the dielectric antireflection layer of the target area and the metal layer with a predetermined depth in the target area;
and removing the residual photoresist.
Optionally, the performing the second etching to thin the dielectric antireflection layer and the exposed metal layer includes:
and performing the second etching by a dry etching process to thin the dielectric antireflection layer and the exposed metal layer.
Optionally, the thickness of the second etching is 10 angstroms
To 200 angstroms.
Optionally, the performing the third etching to remove the metal layer in the target region includes:
and carrying out the third etching by a wet etching process to remove the metal layer in the target area.
Optionally, the dielectric antireflective layer comprises silicon oxynitride (SiON) and silicon oxide.
Optionally, the metal layer includes titanium (Ti) and titanium nitride (TiN).
Optionally, the metal layer includes a titanium layer and a titanium nitride layer formed by overlapping in sequence.
Optionally, the first oxide layer and the second oxide layer include silicon oxide.
Optionally, the substrate includes a silicon substrate, or the substrate includes a silicon substrate with a silicon oxide layer formed on an upper surface thereof, or the substrate includes a silicon substrate with an amorphous silicon layer formed on an upper surface thereof.
The technical scheme at least comprises the following advantages:
in the preparation process of the MEMS sensor, after a first oxidation layer, an amorphous silicon layer, a metal layer and a dielectric antireflection layer are sequentially formed on a substrate, the dielectric antireflection layer of a target area corresponding to an induction area is removed through first etching, the dielectric antireflection layer and the exposed metal layer are thinned through second etching, and the metal layer of the target area is removed through third etching, so that subsequent oxidation layer deposition is carried out, the problems that the appearance of a device is poor and the yield is low due to the fact that electrodes are formed through a wet etching process in the related technology are solved, and the manufacturing yield of the MEMS sensor is improved to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic top view of a MEMS sensor provided in the related art;
FIG. 2 is a flow chart of a method of making an electrode provided by an exemplary embodiment of the present application;
fig. 3 to 8 are schematic views of a method for manufacturing an electrode according to an exemplary embodiment of the present disclosure.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, there is shown a flowchart of a method for preparing an electrode, which is applicable to the preparation of an electrode of a MEMS sensor, according to an exemplary embodiment of the present application, the method including:
in step 201, a substrate is provided.
Referring to fig. 3, there is shown a schematic cross-sectional view of a first oxide layer 321, an amorphous silicon layer 330, a metal layer 340, and a dielectric antireflective layer 350 formed on a substrate 310. Illustratively, as shown in fig. 3, the first oxide layer 321 may be deposited on the substrate 310 by a Chemical Vapor Deposition (CVD) process (e.g., Plasma Enhanced Chemical Vapor Deposition (PECVD)), the amorphous silicon layer 330 may be deposited on the first oxide layer 321 by a CVD process (e.g., PECVD), the metal layer 340 may be deposited on the amorphous silicon layer 330 by a Physical Vapor Deposition (PVD) process, and the dielectric anti-reflective layer 350 may be deposited on the second metal layer 340 by a CVD process (e.g., PECVD).
Alternatively, in this embodiment, the substrate 310 may be a silicon substrate, or the substrate 310 may be a silicon oxide (e.g., silicon dioxide SiO) formed on an upper surface thereof2) Or, the substrate 310 may be a silicon substrate having an amorphous silicon layer formed on an upper surface thereof.
Optionally, in the embodiment of the present application, the dielectric antireflection layer 350 includes silicon oxynitride and silicon oxide (e.g., silicon dioxide).
Optionally, in the embodiment of the present application, the metal layer 340 includes titanium and titanium nitride; optionally, the metal layer 340 includes a titanium layer and a titanium nitride layer formed by overlapping in sequence, for example, the metal layer 340 may be a titanium layer/titanium nitride layer disposed from bottom to top, a titanium nitride layer/titanium layer disposed from bottom to top, a titanium layer/titanium nitride layer structure disposed from bottom to top, a titanium nitride layer/titanium nitride layer structure disposed from bottom to top, a plurality of titanium layers/titanium nitride layers disposed from bottom to top in a periodically stacked manner, a plurality of titanium nitride layers/titanium nitride layers in a periodically stacked manner, a titanium nitride layer structure stacked after a plurality of titanium layers/titanium nitride layers in a periodically stacked manner, or a titanium nitride layer structure stacked after a plurality of titanium nitride layers/titanium nitride layers in a periodically stacked manner, which is not exhaustive.
Referring to fig. 4, a schematic cross-sectional view of the first etching is shown; referring to fig. 5, a cross-sectional view after the first etch to remove the photoresist is shown. As shown in fig. 4, a first via 303 is formed after the first etching, and the first via 303 extends to a predetermined depth in the metal layer 340; the target area 302 is an area where no electrode needs to be formed, and for example, the area may be a sensing area.
For example, as shown in fig. 4, in step 203, "performing a first etching to remove the dielectric antireflection layer in the target region and the metal layer at a predetermined depth in the target region" includes but is not limited to: covering a photoresist 301 on the surface of the dielectric antireflection layer 350; after exposing and developing the photoresist of the target area 302, removing the photoresist of the target area 302; performing first etching through a dry etching process or a wet etching process to remove the dielectric antireflection layer 350 of the target area 302 and the metal layer with a predetermined depth in the target area 302; the remaining photoresist 301 is removed.
And step 204, carrying out second etching to thin the dielectric antireflection layer and the exposed metal layer to form a second through hole.
Referring to fig. 6, a schematic cross-sectional view after a second etch is performed is shown. As shown in fig. 6, the second etching is a general etching, after the second etching, the remaining dielectric reflective layer 350 is thinned, and the exposed metal layer 340 is further thinned to form the second via 304, wherein the second etching may adopt a dry etching process. Optionally, the thickness of the second etching is 10 to 200 angstroms.
And step 205, carrying out third etching to remove the metal layer in the target area and expose the amorphous silicon layer.
Referring to fig. 7, a schematic cross-sectional view of the metal layer 340 removed by the third etching from the target area 302 is shown. As shown in fig. 7, after the third etching, the first oxide layer 321 of the target area 302 is exposed, wherein the third etching may use a wet etching process.
In step 206, a second oxide layer is formed on the exposed surfaces of the dielectric antireflection layer, the amorphous silicon layer and the first oxide layer.
Referring to fig. 8, a schematic cross-sectional view of forming a second oxide layer is shown. Illustratively, as shown in fig. 8, the second oxide layer 322 may be deposited on the surfaces of the exposed dielectric anti-reflective layer 350, the amorphous silicon layer 330 and the first oxide layer 321 by a CVD process (e.g., PECVD). Optionally, the second oxide layer 322 includes silicon oxide (e.g., silicon dioxide).
For example, after step 206, the sensing region 810 and the electrode 820, and the top view of the sensing region 810 and the electrode 820 formed by the method can be referred to in fig. 1, that is, the sensing region 810 formed in the embodiment of the present application can correspond to the sensing region 110 in the embodiment of fig. 1, and the electrode 820 formed in the embodiment of the present application can correspond to the electrode 120 in the embodiment of fig. 1. As shown in fig. 8, the sensing region 810 formed in the present embodiment sequentially includes a first oxide layer 321, an amorphous silicon layer 330, and a second oxide layer 322 from bottom to top, and the electrode 820 formed in the present embodiment sequentially includes the first oxide layer 321, the amorphous silicon layer 330, the metal layer 340, the dielectric anti-reflective layer 350, and the second oxide layer 322 from bottom to top.
It should be noted that the sensing region 810 and the electrode 820 indicated by the dotted line in fig. 8 are for exemplary purposes, and the sensing region and the electrode are formed not only at the portion indicated by the dotted line.
To sum up, in the embodiment of the application, in the preparation process of the MEMS sensor, after the first oxide layer, the amorphous silicon layer, the metal layer, and the dielectric antireflection layer are sequentially formed on the substrate, the dielectric antireflection layer of the target region corresponding to the sensing region is removed by the first etching, the dielectric antireflection layer and the exposed metal layer are thinned by the second etching, and the metal layer of the target region is removed by the third etching, so that the subsequent deposition of the oxide layer is performed, the problems of poor device morphology and low yield caused by the formation of the electrode by the wet etching process in the related art are solved, and the manufacturing yield of the MEMS sensor is improved to a certain extent.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A method for preparing an electrode, which is applied to the preparation of the electrode of a MEMS sensor, and comprises the following steps:
providing a substrate;
sequentially forming a first oxide layer, an amorphous silicon layer, a metal layer and a dielectric anti-reflection layer on the substrate;
carrying out first etching, removing the dielectric antireflection layer of a target area and the metal layer with a preset depth in the target area to form a first through hole, wherein the target area is an area where an electrode is not required to be formed;
performing second etching to thin the dielectric antireflection layer and the exposed metal layer to form a second through hole;
carrying out third etching to remove the metal layer in the target area and expose the first oxide layer;
and forming a second oxide layer on the surfaces of the exposed dielectric antireflection layer, the amorphous silicon layer and the first oxide layer.
2. The method according to claim 1, wherein the performing the first etching to remove the dielectric antireflection layer in the target region and the metal layer at a predetermined depth in the target region comprises:
covering a photoresist on the surface of the dielectric antireflection layer;
exposing and developing the light resistance of the target area, and then removing the light resistance of the target area;
performing the first etching through a dry etching process or a wet etching process to remove the dielectric antireflection layer of the target area and the metal layer with a predetermined depth in the target area;
and removing the residual photoresist.
3. The method according to claim 2, wherein the performing the second etching to thin the dielectric antireflection layer and the exposed metal layer comprises:
and performing the second etching by a dry etching process to thin the dielectric antireflection layer and the exposed metal layer.
4. The method according to claim 3, wherein the second etching is 10 to 200 angstroms thick.
5. The method according to any one of claims 1 to 4, wherein the performing the third etching to remove the metal layer in the target region comprises:
and carrying out the third etching by a wet etching process to remove the metal layer in the target area.
6. The production method according to any one of claims 1 to 4, wherein the dielectric antireflection layer comprises silicon oxynitride and silicon oxide.
7. The method of claim 6, wherein the metal layer comprises titanium and titanium nitride.
8. The method for preparing the metal layer of claim 7, wherein the metal layer comprises a titanium layer and a titanium nitride layer which are sequentially overlapped.
9. The method according to claim 8, wherein the first oxide layer and the second oxide layer comprise silicon oxide.
10. The production method according to claim 9, wherein the substrate comprises a silicon substrate, or wherein the substrate comprises a silicon substrate having a silicon oxide formed on an upper surface thereof, or wherein the substrate comprises a silicon substrate having an amorphous silicon layer formed on an upper surface thereof.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010248291.1A CN111517272B (en) | 2020-04-01 | 2020-04-01 | Method for producing electrode |
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| CN202010248291.1A CN111517272B (en) | 2020-04-01 | 2020-04-01 | Method for producing electrode |
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| CN111517272B CN111517272B (en) | 2023-07-04 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112053949A (en) * | 2020-08-31 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Etching method of metal interconnection structure |
| CN112185888A (en) * | 2020-09-14 | 2021-01-05 | 华虹半导体(无锡)有限公司 | MIM capacitor and forming method thereof |
| CN112374456A (en) * | 2020-11-12 | 2021-02-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MEMS device |
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| TW438908B (en) * | 1999-07-26 | 2001-06-07 | United Microelectronics Corp | Method for etching capacitor electrode |
| US6171940B1 (en) * | 1999-10-01 | 2001-01-09 | United Microelectronics Corp. | Method for fabricating semiconductor devices having small dimension gate structures |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112053949A (en) * | 2020-08-31 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Etching method of metal interconnection structure |
| CN112053949B (en) * | 2020-08-31 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Etching method of metal interconnection structure |
| CN112185888A (en) * | 2020-09-14 | 2021-01-05 | 华虹半导体(无锡)有限公司 | MIM capacitor and forming method thereof |
| CN112185888B (en) * | 2020-09-14 | 2022-08-16 | 华虹半导体(无锡)有限公司 | MIM capacitor and forming method thereof |
| CN112374456A (en) * | 2020-11-12 | 2021-02-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MEMS device |
| CN112374456B (en) * | 2020-11-12 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MEMS device |
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