CN106876371A - The manufacture method of MIM capacitor - Google Patents
The manufacture method of MIM capacitor Download PDFInfo
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- CN106876371A CN106876371A CN201710004624.4A CN201710004624A CN106876371A CN 106876371 A CN106876371 A CN 106876371A CN 201710004624 A CN201710004624 A CN 201710004624A CN 106876371 A CN106876371 A CN 106876371A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
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Abstract
The invention discloses a kind of manufacture method of MIM capacitor, including step：The laminated construction that formation is made up of bottom crown metal level, intermediate insulating layer and top crown metal level；First time metal etch etching is carried out to top crown metal level and with intermediate insulating layer as stop-layer；The intermediate insulating layer outside second insulating barrier etching removal top crown metal level is carried out by stop-layer of bottom crown metal level；Dielectric anti reflective layer is formed, dielectric anti reflective layer is directly contacted with bottom crown metal level；Third time metal etch is carried out to bottom crown metal level and MIM capacitor is formed.Influence of the intermediate insulating layer to the fluctuation of the reflectivity of dielectric reflective layer when the present invention can eliminate bottom and the intermediate insulating layer contact of dielectric reflective layer, so that the reflectivity of dielectric anti reflective layer keeps stabilization, the process window of the chemical wet etching of bottom crown metal level can finally be improved, so as to improve product yield, the time of third time metal etch can be reduced, the generation of polymer can be reduced.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor integrated circuit, more particularly to a kind of metal-insulator-metal
The manufacture method of (metal-insulator-metal, MIM) electric capacity.
Background technology
In semiconductor integrated circuit manufacture, and MIM capacitor (, metal-insulator-metal) and due to being integrated in rear road metal interconnection
In, chip area can be reduced and reduce parasitic capacitance, progressively instead of polysilicon insulation body polysilicon (poly-
Insulator-poly, PIP) electric capacity and metal oxide silicon substrate (metal-oxide-silicon, MOS) electric capacity, therefore
It is widely applied in memory, radio frequency and analog/mixed signal integrated circuit.
MIM capacitor usually using silicon nitride or silicon oxynitride as capacitor intermediate insulating layer, wherein, silicon nitride is
Si3N4And abbreviation SIN, silicon oxynitride is referred to as SION, and the use of different insulative body can influence the electric capacity and inductance value of capacitor.
In the conventional method, in IC products during integrated MIM capacitor, after MIM layers of top crown metal level is formed,
Need to perform etching top crown metal level using lithographic etch process, at this moment the etching of top crown metal level can stop at centre
On insulating barrier, so that intermediate insulating layer is as silicon nitride as an example, the etching of top crown metal level can be stopped on silicon nitride layer；And rear
Continue when carrying out the etching of bottom crown metal level, it is necessary to be initially formed one layer of dielectric anti reflective layer (DARC), DARC typically uses nitrogen oxygen
SiClx layer, is carrying out chemical wet etching afterwards, and chemical wet etching is to be initially formed photoresist layer, includes exposing using photoetching is carried out to photoresist
Photodevelopment etc. defines photoetching offset plate figure structure, is performed etching by mask of photoetching offset plate figure structure afterwards.It is special in existing method
Be not the chemical wet etching of bottom crown metal level process window it is small, the yield of product can be reduced.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of manufacture method of MIM capacitor, can improve bottom crown metal
The process window of the chemical wet etching of layer, improves product yield.
In order to solve the above technical problems, the manufacture method of the MIM capacitor of present invention offer comprises the following steps：
Step one, formed in the Semiconductor substrate for be formed with integrated circuit by bottom crown metal level, intermediate insulating layer and
The laminated construction of top crown metal level composition.
Step 2, carry out first time metal etch, the etch areas of the first time metal etch using lithographic definition simultaneously
For being performed etching to the top crown metal level, the first time metal etch is with the intermediate insulating layer as stop-layer.
Step 3, second insulating barrier etching is carried out, second insulating barrier is etched for will be positioned at the first time
The intermediate insulating layer outside the top crown metal level after metal etch is all removed, and second insulating barrier etching is with institute
Bottom crown metal level is stated for stop-layer.
Step 4, dielectric anti reflective layer is formed, in the outer dielectric anti reflective layer of the top crown metal level directly and institute
The contact of bottom crown metal level is stated, the intermediate insulation when bottom and the intermediate insulating layer for eliminating the dielectric reflective layer contact
Influence of the layer to the fluctuation of the reflectivity of the dielectric reflective layer.
Step 5, carry out third time metal etch, the etch areas of the third time metal etch using lithographic definition simultaneously
For being performed etching to the bottom crown metal level, by the top crown metal level after the first time metal etch and described
The intermediate insulating layer composition MIM capacitor of the bottom crown metal level and centre after third time metal etch.
Further improvement is that the material of the intermediate insulating layer includes silicon nitride or silicon oxynitride.
Further improvement is that the material of the top crown metal level includes titanium nitride.
Further improvement is that the bottom crown metal layer material includes aluminium copper.
Further improvement is that the bottom crown metal layer material also includes being formed at the lower surface shape of aluminum-copper alloy layer
Into have titanium layer and be formed at the aluminum-copper alloy layer top surface titanium and the superimposed layer of titanium nitride.
Further improvement is that the material of the dielectric anti reflective layer includes silicon oxynitride.
Further improvement is, after the completion of the first time metal etch, the remaining institute outside the top crown metal level
The thickness for stating intermediate insulating layer is
Further improvement is that the process conditions of second insulating barrier etching are：Temperature is 60 DEG C, and radio-frequency power is
300W~600W, pressure is 40 millitorr~70 millitorrs, CH2F2Flow be 20sccm~70sccm, the flow of AR for 50sccm~
130sccm, O2Flow be 10sccm~40sccm, the time be 8 seconds~20 seconds.
Further improvement is that the material of the dielectric anti reflective layer also includes being formed at the oxidation on silicon oxynitride surface
Layer.
Further improvement is that the thickness of the silicon oxynitride of the dielectric anti reflective layer isSilicon oxynitride surface
The thickness of oxide layer is
Further improvement be, after the completion of second insulating barrier etching of step 2 and step 4 forms described
Between dielectric anti reflective layer, also including being cleaned to remove the polymer produced in second insulating barrier etching process
Step.
Further improvement is that the thickness of the top crown metal level is
Further improvement is that the region of the MIM capacitor is located at the field oxide top of the Semiconductor substrate.
Further improvement is that the MIM capacitor is integrated in the integrated circuit in the Semiconductor substrate
In metal interconnecting layer.
Further improvement is, after the completion of the third time metal etch, also draws the MIM electricity including forming contact hole
Hold the bottom crown metal level and the top crown metal level electrode the step of.
The present invention is once removed pole by after the corresponding first time metal etch completion of top crown metal level
The technique of second insulating barrier etching of the intermediate insulating layer outside sheetmetal layer, will be upper by the technique of second insulating barrier etching
Intermediate insulating layer outside pole plate metal level is removed completely, and such subsequent medium anti-reflecting layer can be with the bottom crown metal level of bottom
Directly contact；Because intermediate insulating layer is as the stop-layer of first time metal etch therefore after the completion of first time metal etch
Thickness has larger fluctuation, and the thickness fluctuation that intermediate insulating layer can be eliminated after intermediate insulating layer is removed completely resists to medium
Intermediate insulating layer is to medium when the influence in reflecting layer, the i.e. present invention can eliminate bottom and the intermediate insulating layer contact of dielectric reflective layer
The influence of the fluctuation of the reflectivity in reflecting layer, so that the reflectivity of dielectric anti reflective layer keeps stabilization, can finally improve
The process window of the chemical wet etching of bottom crown metal level, so as to improve product yield.
In addition, the present invention before third time metal etch due to having eliminated the intermediate insulation outside top crown metal level
Layer, therefore the etching of intermediate insulating layer need not be again carried out when third time metal etch is etched, therefore third time metal can be reduced
The time of etching.
Equally, also without the underway etching of insulating barrier when subsequently carrying out the etching of contact hole, therefore can reduce
The polymer (polymer) produced when intermediate insulating layer is etched is carried out, namely the present invention can reduce the generation of polymer, and gather
There is a possibility that the short circuit of polar up and down of MIM capacitor during compound formation.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Fig. 1 E are the device architecture schematic diagrames in each step of manufacture method of existing MIM capacitor；
Fig. 2 is the influence distribution map of the thickness to the reflectivity of the silicon oxynitride of different-thickness of silicon nitride；
Fig. 3 is the flow chart of the manufacture method of embodiment of the present invention MIM capacitor；
Fig. 4 A- Fig. 4 F are the device architecture schematic diagrames in each step of present invention method.
Specific embodiment
Before the embodiment of the present invention is described in detail, first explain existing method and applicant is produced to existing method
The analysis of raw technical problem, as shown in Figure 1A to Fig. 1 E, be existing MIM capacitor each step of manufacture method in device architecture
Schematic diagram；The manufacture method of existing MIM capacitor comprises the following steps：
Step one, as shown in Figure 1A, forms by bottom crown being formed with the Semiconductor substrate of integrated circuit such as silicon substrate 1
The laminated construction of metal level 2, intermediate insulating layer 3 and top crown metal level 4 composition.
Step 2, carry out first time metal etch.First, as shown in Figure 1B, using photoetching process and photoresist figure is formed
Shape 101 defines the etch areas of the first time metal etch.Afterwards, as shown in Figure 1 C, the top crown metal level 4 is entered
Row etching, the first time metal etch is with the intermediate insulating layer 3 as stop-layer.The intermediate insulating layer 3 is in etching process
In have certain loss.Photoetching offset plate figure 101 is removed afterwards.
Both the above step is the etching to the top crown metal level 4, and step below will be described to the lower pole
The etching of sheetmetal layer 2：
Step 3, as shown in figure iD, forms dielectric anti reflective layer 5.Fig. 1 D only show the area outside the top crown metal level 4
Domain, it can be seen that the dielectric anti reflective layer 5 is formed at the surface of the intermediate insulating layer 3 of residual.
Step 4, carry out third time metal etch.First, as shown in figure iD, using photoetching process and photoresist figure is formed
Shape 102 defines the etch areas of the third time metal etch.Afterwards, as referring to figure 1E, the bottom crown metal level 2 is entered
Row etching, also needs to first be sequentially etched the dielectric anti reflective layer 5 and institute before performing etching the bottom crown metal level 2
State intermediate insulating layer 3.After the completion of etching, formed by the top crown metal level 4 after the first time metal etch and described
The composition MIM capacitor of the intermediate insulating layer 3 of the bottom crown metal level 2 and centre after third time metal etch.
Due to, the process window very little of third time metal etch in above-mentioned existing method, and yield issues are easily produced, and
Yield is reduced namely means the rising of cost, therefore is had a significant impact to economic benefit.In order to find out third time metal etch
The problem of process window very little, applicant has done following analysis：
The material of the intermediate insulating layer 3 includes silicon nitride or silicon oxynitride, and the material of dielectric anti reflective layer 5 is typically adopted
Use silicon oxynitride；With the intermediate insulating layer 3 as silicon nitride, the material of dielectric anti reflective layer 5 for as a example by silicon oxynitride,
After the completion of the first time metal etch of step 2, the intermediate insulating layer 3 outside the top crown metal level 4 has certain damage
Consumption, and this loss causes the intermediate insulating layer 3 and uneven outside the top crown metal level 4, with certain ripple
Dynamic property, exactly this fluctuation causes that the reflectivity of the dielectric anti reflective being subsequently formed layer 5 has fluctuation, can finally cause the
The process window of three minor metals etching reduces.Reason may be referred to shown in Fig. 2, and Fig. 2 is the thickness of silicon nitride to different-thickness
The influence distribution map of the reflectivity of silicon oxynitride, the thickness of the silicon nitride that ordinate is represented is i.e. exhausted corresponding to the centre in Fig. 2
The thickness of edge layer 3, the thickness of abscissa silicon oxynitride is the thickness for corresponding to dielectric anti reflective layer 5, in actual process, institute
Matter anti-reflecting layer 5 is given an account of typically using the thickness at position shown in AA lines in 30 nanometers, i.e. Fig. 2, it can be seen that in the whole of AA lines
The change of the thickness of silicon nitride is illustrated on individual longitudinal direction, it is known that when the thickness change of silicon nitride, the reflectivity of silicon oxynitride becomes
Change larger.The size of reflectivity is represented with different gray scales in Fig. 2.So, figure it is seen that the reflectivity of silicon oxynitride
Thickness to silicon nitride is sensitive, namely when the intermediate insulating layer 3 being made up of silicon nitride it is in uneven thickness when, by nitrogen
The reflectivity of the dielectric anti reflective layer 5 of silica composition is also just uneven, and the third time that existing method has finally occurs
The process window very little of metal etch, and easily produce the defect of yield issues.
Applicant forms present invention method according to the analysis to above-mentioned technical problem, is now described as follows：
As shown in figure 3, being the flow chart of the manufacture method of embodiment of the present invention MIM capacitor；As shown in Fig. 4 A to Fig. 4 F, it is
Device architecture schematic diagram in each step of present invention method, the manufacture method of embodiment of the present invention MIM capacitor is included such as
Lower step：
Step one, as shown in Figure 4 A, formed in the Semiconductor substrate 1 for being formed with integrated circuit by bottom crown metal level 2,
The laminated construction of intermediate insulating layer 3 and the composition of top crown metal level 4.
Preferably, the material of the intermediate insulating layer 3 includes silicon nitride or silicon oxynitride.
The material of the top crown metal level 4 includes titanium nitride.
The material of bottom crown metal level 2 includes aluminium copper, also including being formed at the lower surface shape of aluminum-copper alloy layer
Into have titanium layer and be formed at the aluminum-copper alloy layer top surface titanium and the superimposed layer of titanium nitride.
For the ease of clearer explanation, a design parameter is listed here：The thickness of the top crown metal level 4 isThe thickness of the aluminium copper of the material of bottom crown metal level 2 isIt is formed at the lower surface of aluminum-copper alloy layer
The thickness for being formed with titanium layer isThe titanium for being formed at the top surface of the aluminum-copper alloy layer isTitanium nitride is
The intermediate insulating layer 3 use silicon nitride and thickness for
Step 2, carry out first time metal etch.First, as shown in Figure 4 B, using photoetching process and photoresist figure is formed
Shape 101 defines the etch areas of the first time metal etch.Afterwards, as shown in Figure 4 C, the top crown metal level 4 is entered
Row etching, the first time metal etch is with the intermediate insulating layer 3 as stop-layer.The intermediate insulating layer 3 is in etching process
In have certain loss.Photoetching offset plate figure 101 is removed afterwards.
For the ease of clearer explanation, a design parameter is listed here：After the completion of the first time metal etch,
The thickness of the remaining described intermediate insulating layer 3 outside the top crown metal level 4 is
Step 3, as shown in Figure 4 D, carries out second insulating barrier etching, and second insulating barrier is etched for that will be located at
The intermediate insulating layer 3 outside the top crown metal level 4 after the first time metal etch is all removed, and described second absolutely
Edge layer is etched with the bottom crown metal level 2 as stop-layer.
For the ease of clearer explanation, a design parameter is listed here：The work of second insulating barrier etching
Skill condition is：Temperature is 60 DEG C, and radio-frequency power is 300W~600W, and pressure is 40 millitorr~70 millitorrs, CH2F2Flow be
The flow of 20sccm~70sccm, AR is 50sccm~130sccm, O2Flow be 10sccm~40sccm, the time be 8 seconds~
20 seconds.
After the completion of second insulating barrier etching of step 2 and step 4 formed dielectric anti reflective layer 5 it
Between, also including being cleaned to remove the polymer produced in second insulating barrier etching process the step of.
Step 4, as shown in Figure 4 E, forms dielectric anti reflective layer 5.Fig. 4 E only show the area outside the top crown metal level 4
Domain, it can be seen that directly connect with the bottom crown metal level 2 in the outer dielectric anti reflective layer 5 of the top crown metal level 4
Touch, 3 pairs of media of the intermediate insulating layer are anti-when the bottom and the intermediate insulating layer 3 for eliminating the dielectric reflective layer contact
Penetrate the influence of the fluctuation of the reflectivity of layer.
Preferably, the material of the dielectric anti reflective layer 5 includes silicon oxynitride and is formed at the oxygen on silicon oxynitride surface
Change layer.For the ease of clearer explanation, a design parameter is listed here：The silicon oxynitride of the dielectric anti reflective layer 5
Thickness beThe thickness of the oxide layer on silicon oxynitride surface is
Step 5, carry out third time metal etch.First, as shown in Figure 4 E, using photoetching process and photoresist figure is formed
Shape 102 defines the etch areas of the third time metal etch.Afterwards, as illustrated in figure 4f, the bottom crown metal level 2 is entered
Row etching, also needs to first etch away the dielectric anti reflective layer 5 before performing etching the bottom crown metal level 2.Etch
Cheng Hou, by under described after the top crown metal level 4 and the third time metal etch after the first time metal etch
The composition MIM capacitor of the intermediate insulating layer 3 of pole plate metal level 2 and centre.
Preferably, the region of the MIM capacitor is located at the field oxide top of the Semiconductor substrate 1.The MIM capacitor
It is integrated in the metal interconnecting layer of the integrated circuit in the Semiconductor substrate 1.The third time metal etch is complete
Cheng Hou, also draws the bottom crown metal level 2 and the top crown metal level 4 of the MIM capacitor including forming contact hole
The step of electrode.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacture method of MIM capacitor, it is characterised in that comprise the following steps：
Step one, formed by bottom crown metal level, intermediate insulating layer and upper pole in the Semiconductor substrate for be formed with integrated circuit
The laminated construction of sheetmetal layer composition；
Step 2, carry out first time metal etch, the first time metal etch etch areas are using lithographic definition and are used for
The top crown metal level is performed etching, the first time metal etch is with the intermediate insulating layer as stop-layer；
Step 3, second insulating barrier etching is carried out, second insulating barrier is etched for will be positioned at first minor metal
The intermediate insulating layer outside the top crown metal level after etching is all removed, and second insulating barrier etching is with described
Pole plate metal level is stop-layer；
Step 4, form dielectric anti reflective layer, the outer dielectric anti reflective layer of the top crown metal level directly and it is described under
Pole plate metal level is contacted, the intermediate insulating layer pair when the bottom and the intermediate insulating layer for eliminating the dielectric reflective layer contact
The influence of the fluctuation of the reflectivity of the dielectric reflective layer；
Step 5, carry out third time metal etch, the third time metal etch etch areas are using lithographic definition and are used for
The bottom crown metal level is performed etching, by the top crown metal level and the described 3rd after the first time metal etch
The intermediate insulating layer composition MIM capacitor of the bottom crown metal level and centre after minor metal etching.
2. the manufacture method of MIM capacitor as claimed in claim 1, it is characterised in that：The material of the intermediate insulating layer includes
Silicon nitride or silicon oxynitride.
3. the manufacture method of MIM capacitor as claimed in claim 1, it is characterised in that：The material bag of the top crown metal level
Include titanium nitride.
4. the manufacture method of MIM capacitor as claimed in claim 1, it is characterised in that：The bottom crown metal layer material includes
Aluminium copper.
5. the manufacture method of MIM capacitor as claimed in claim 4, it is characterised in that：The bottom crown metal layer material is also wrapped
Include and be formed at the lower surface of aluminum-copper alloy layer and be formed with titanium layer and be formed at the titanium of the top surface of the aluminum-copper alloy layer
With the superimposed layer of titanium nitride.
6. the manufacture method of MIM capacitor as claimed in claim 1, it is characterised in that：The material bag of the dielectric anti reflective layer
Include silicon oxynitride.
7. the manufacture method of MIM capacitor as claimed in claim 2, it is characterised in that：After the completion of the first time metal etch,
The thickness of the remaining described intermediate insulating layer outside the top crown metal level is
8. the manufacture method of MIM capacitor as claimed in claim 7, it is characterised in that：The work of second insulating barrier etching
Skill condition is：Temperature is 60 DEG C, and radio-frequency power is 300W~600W, and pressure is 40 millitorr~70 millitorrs, CH2F2Flow be
The flow of 20sccm~70sccm, AR is 50sccm~130sccm, O2Flow be 10sccm~40sccm, the time be 8 seconds~
20 seconds.
9. the manufacture method of MIM capacitor as claimed in claim 6, it is characterised in that：The material of the dielectric anti reflective layer is also
Oxide layer including being formed at silicon oxynitride surface.
10. the manufacture method of MIM capacitor as claimed in claim 9, it is characterised in that：The nitrogen oxidation of the dielectric anti reflective layer
The thickness of silicon isThe thickness of the oxide layer on silicon oxynitride surface is
The manufacture method of 11. MIM capacitors as claimed in claim 1, it is characterised in that：In second minor insulation of step 2
After the completion of layer etching and step 4 is formed between dielectric anti reflective layer, also including being cleaned to remove described second
The step of polymer produced in insulating barrier etching process.
The manufacture method of 12. MIM capacitor as described in claim 1 or 3, it is characterised in that：The thickness of the top crown metal level
Spend and be
The manufacture method of 13. MIM capacitor as described in claim 1 or 3, it is characterised in that：The region of the MIM capacitor is located at
The field oxide top of the Semiconductor substrate.
The manufacture method of 14. MIM capacitors as claimed in claim 13, it is characterised in that：The MIM capacitor is integrated in positioned at institute
In stating the metal interconnecting layer of the integrated circuit in Semiconductor substrate.
The manufacture method of 15. MIM capacitors as claimed in claim 1, it is characterised in that：The third time metal etch is completed
Afterwards, the bottom crown metal level of the MIM capacitor and the electrode of the top crown metal level also are drawn including forming contact hole
The step of.
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| CN112053932A (en) * | 2020-08-31 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Manufacturing method of MIM capacitor |
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| CN111517272A (en) * | 2020-04-01 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Method for preparing electrode |
| CN112053932A (en) * | 2020-08-31 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Manufacturing method of MIM capacitor |
| CN112053932B (en) * | 2020-08-31 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Manufacturing method of MIM capacitor |
| CN112185887A (en) * | 2020-09-08 | 2021-01-05 | 华虹半导体(无锡)有限公司 | Manufacturing method of MIM capacitor |
| CN112185887B (en) * | 2020-09-08 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Manufacturing method of MIM capacitor |
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