CN100517559C - Making method for storage capacitor - Google Patents
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- CN100517559C CN100517559C CNB2006100299165A CN200610029916A CN100517559C CN 100517559 C CN100517559 C CN 100517559C CN B2006100299165 A CNB2006100299165 A CN B2006100299165A CN 200610029916 A CN200610029916 A CN 200610029916A CN 100517559 C CN100517559 C CN 100517559C
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Abstract
A manufacturing method of a storage capacitor comprises the following steps: a primary dielectric layer is formed on an insulating substrate; a primary conducting layer is formed on the primary dielectric layer; the primary conducting layer and the primary dielectric layer are selectively etched to form a groove of which the bottom exposes the insulating substrate surface; a secondary dielectric layer is formed on the groove side wall; a secondary conducting layer is formed at the groove bottom as well as the secondary dielectric layer; a tertiary dielectric layer is formed on the secondary conducting layer side wall and top surface; the primary conducting layer and the tertiary dielectric layer in groove are filled with a tertiary conducting layer. The manufacturing method avoids the disadvantage that the capacitor plate collapses in manufacturing process.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of holding capacitor.
Background technology
The dynamic random access memory memory cell generally comprises a storage capacitance and a MOS transistor.The increase of its storage density needs integrated more memory cell and unit storage unit storage more information on the unit are.Integrated more memory cell depends on device size and reduces the photoetching process progress on the unit are; For unit storage unit storage more information, except seeking high dielectric constant material and reducing the capacitor plate distance, at present people adopt mostly and increase the long-pending method of polar board surface, and for example, capacitor plate is designed to tubbiness, column, shape such as crown to increase the area of pole plate.Number of patent application is the manufacture method that the Chinese patent of 98118488.X has proposed a kind of holding capacitor.This method forms crown pole plate by self-registered technology and increases memory capacity, Fig. 1 is the structural representation after the method for this patent disclosure forms first pole plate, as shown in Figure 1, be formed with channel separating zone 110 in the Semiconductor substrate 100, source electrode 120a, drain electrode 120b forms oxide layer 125 and grid 130 on described substrate 100, on described oxide layer 125 and grid 130, be formed with dielectric layer 125, in described dielectric layer, be formed with connecting hole 150.Be formed with crown first pole plate 155 of capacitor on described dielectric layer 125, described first pole plate 155 bottoms are connected with described connecting hole 150.By the autoregistration etching with the pole plate of first pole plate 155 can do very thin, yet the thin vertical capacitor pole plate that this method forms but causes pole plate to collapse easily in cleaning process, and makes the shape of capacitor be difficult to control.
Existing another manufacture method of crown capacitor such as Fig. 2～shown in Figure 10.
As shown in Figure 2, be formed with connecting hole 101 in described insulating barrier 100, wherein, insulating barrier 100 is covered on the transistor.Metal in the connecting hole 101 links to each other with transistorized source electrode.On described insulating barrier 100, form etching stop layer 102, the first dielectric layers, 104, the first oxide layers 106 and hard mask layer 108 successively.Spin coating photoresist 110 and form channel patterns 112 on described hard mask layer 108.
As shown in Figure 3, etching is transferred to described channel patterns and is formed pattern 112a on the described hard mask layer 108, removes described photoresist 110.
As shown in Figure 4, as the barrier layer, continue the described pattern 112a of etching with hard mask layer 108, form groove 112b, described groove 112b exposes the bottom metal in the connecting hole 101.
As shown in Figure 5, deposition first polysilicon layer 114 in described groove, and on described first polysilicon layer 114, form second oxide layer 116.
As shown in Figure 6, remove first polysilicon layer 114 and second oxide layer 116 on described first oxide layer 106 tops by cmp (CMP).
As shown in Figure 7, return and carve described polysilicon layer 114 and form the second polysilicon 114a at described groove 112a sidewall.The described second polysilicon layer 114a is first pole plate of capacitor.
As shown in Figure 8, spin coating photoresist and graphical on described first oxide layer 106, first oxide layer 106 between the described second polysilicon layer 114a of etching forms groove 106a.Remove described photoresist and wet-cleaned by ashing (Ashing).
As shown in Figure 9, form second dielectric layer 118 on the described second polysilicon layer 114a and bottom the groove 106a, described second dielectric layer 118 is a silica.
As shown in figure 10, on described second dielectric layer 118, form second pole plate 119.
In above-mentioned manufacture method, after forming groove 106a, first oxide layer 106 between the described first pole plate 114a is removed, thereby in back step removal photoresist and cleaning process, the first pole plate 114a is collapsed, cause the pole plate shape to be difficult to control, influence the formation of the subsequent step dielectric layer and second pole plate.
Because groove 106a is darker, can causes second pole plate, 119 materials of groove 106a sidewall in deposition process, to stop up the top of groove 106a, and in groove 106a, form the air gap 119a of sealing, shown in Figure 10 a.In the bake process of back step process, the air expanded by heating among the 119a of this air gap and producing causes capacitor manufacturing failure.Reduce the groove 106a degree of depth and can avoid forming described air gap 119a, but but sacrificed the surface area of capacitor plate and the capacity of holding capacitor is reduced.
Summary of the invention
The invention provides a kind of manufacture method of holding capacitor, this method can be avoided the defective that causes capacitor plate to collapse in the manufacture process under the situation of sacrificial capacitors capacity not.
The manufacture method of a kind of holding capacitor provided by the invention comprises:
On the insulating barrier of substrate, form first dielectric layer;
On described first dielectric layer, form first conductive layer;
Described first conductive layer of etching and first dielectric layer form groove selectively, and described channel bottom exposes described surface of insulating layer;
Form second dielectric layer at described trenched side-wall;
Form second conductive layer at described channel bottom and second dielectric layer surface;
Second conductive layer surface in described groove forms the 3rd dielectric layer;
Fill the 3rd conductive layer on the 3rd dielectric layer in described first conductive layer and groove.
The described first dielectric layer material can be a boron-phosphorosilicate glass.
Described first conductive layer is a polysilicon.
Be formed with etching stop layer between the described insulating barrier and first dielectric layer.
The described second dielectric layer material comprises silica, silicon nitride or its combination.
The formation step of described second conductive layer is:
Filled conductive layer on second dielectric layer in described groove;
Spin coating photoresist and graphical described photoresist on described conductive layer;
Remove the conductive layer that is not covered in the groove by etching and form second conductive layer by photoresist;
Remove described photoresist.
Described second conductive comprises polysilicon.
The formation step of described the 3rd dielectric layer is:
Filled media layer on second conductive layer in described groove;
Spin coating photoresist and graphical described photoresist on described dielectric layer;
Remove the dielectric layer that is not covered in the groove by etching and form the 3rd dielectric layer by photoresist;
Remove described photoresist.
Described the 3rd dielectric layer material comprises silica, silicon nitride or its combination.
Described the 3rd conductive layer comprises a kind of or its combination in polysilicon, titanium, tungsten, the titanium nitride.
This method further comprises: form tack coat between described the 3rd conductive layer and described the 3rd dielectric layer.
Described bonding layer material can be titanium or titanium nitride.
Compared with prior art, the present invention has the following advantages: the present invention makes the capacitor method and forms in the crown capacitor process, deposition forms first conductive layer on described first dielectric layer, described first conductive layer at first is formed as the part of electric capacity second pole plate, avoid in subsequent technique having overcome filling groove and interstitial problem for forming the process that the first etching groove of this part recharges.Also avoided simultaneously removing the problem that capacitor plate collapses in the photoresist cleaning process in multistep, make the capacitor that forms have higher robustness (robust), thereby the defective that reduces to form in the manufacture process reduces the electrical failure of the device that forms, but does not but have the memory capacity of sacrificial capacitors.
Description of drawings
Fig. 1～Figure 10 is the generalized section of existing crown holding capacitor manufacture method;
Figure 10 a produces the generalized section of defective for existing crown holding capacitor manufacture method;
Figure 11 is the flow chart according to the manufacture method of the embodiment of the invention;
Figure 12～Figure 26 is the manufacture method generalized section according to the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Figure 11 is the manufacture method flow chart according to the embodiment of the invention.As shown in figure 11, at first.Semi-conductive substrate is provided, on described Semiconductor substrate, is formed with device layer, as metal oxide semiconductor transistor.Deposition one insulating barrier silica for example forms connecting hole in described insulating barrier on described device becomes, and is filled with conductive materials in the connecting hole, described connecting hole bottom link to each other with transistor source (S300).
On described insulating barrier, form first dielectric layer (S310); The described first dielectric layer material can be boron-phosphorosilicate glass (BPSG).
Form first conductive layer (S320) on described first dielectric layer, described first conductive layer can be a polysilicon.
Form hard mask layer (S330) on described first conductive layer, described hard mask layer can be a silicon nitride.
Spin coating photoresist on described hard mask layer, exposure imaging forms channel patterns, by etching described channel patterns is transferred on the described hard mask layer, remove the photoresist on the described hard mask layer, first conductive layer of channel patterns bottom and first dielectric layer form groove on the described hard mask layer of etching, and described channel bottom exposes the conductive materials in the connecting hole (S340) in the described insulating barrier.
Form second dielectric layer (S350) at described trenched side-wall.Described second dielectric layer can be silica or silicon nitride or its combination.
Form second conductive layer (S360) at the described channel bottom and the second dielectric layer sidewall.Described second conductive layer can be a polysilicon, and this second conductive layer is first pole plate of capacitor.Described second conductive layer and described first conductive layer are by the second dielectric layer isolated insulation.
(S370) exposed at hard mask layer to the described first conductive layer top that removes on described first conductive layer.
Form the 3rd dielectric layer (S380) above the second conductive layer sidewall in described groove reaches, described the 3rd dielectric layer is silica or silicon nitride or its combination.
Fill the 3rd conductive layer (S380) on the 3rd dielectric layer in described first conductive layer and groove.Described the 3rd conductive layer is with the first conductive layer physical connection and be electrically connected.Described the 3rd conductive can be a polysilicon, tungsten, tungsten nitride, a kind of or its combination in the titanium.Described the 3rd conductive layer and first conductive layer are formed second pole plate of electric capacity jointly.
Embodiment to manufacture method of the present invention is described in detail below.
Figure 12～Figure 25 is the generalized section according to the manufacture method of the inventive method embodiment.
As shown in figure 12, semi-conductive substrate 200 is provided, on the described Semiconductor substrate device layer is arranged, described device layer is metal oxide semiconductor transistor (MOS), cover an insulating barrier 200a on described device layer, described insulating barrier 200a material can be a silica.Form connecting hole 201 in described insulating barrier 200a, be filled with conductive materials in the described connecting hole 201, connecting hole 201 bottoms are electrically connected with described metal oxide semiconductor transistor source electrode.
As shown in figure 13, deposition-etch stops layer 202, the first dielectric layer 204, oxide layer 206 successively on described insulating barrier 200a.Described etching stop layer 202 materials can be silicon nitrides, and first dielectric layer, 204 materials can be boron-phosphorosilicate glass (BPSG), and the spin coating photoresist walks abreast into pattern 211 on described oxide layer 206.
As shown in figure 14, etching is removed the described oxide layer 206 that is not covered by photoresist.The oxide layer 206a zone that is covered by photoresist is used for forming peripheral circuit.Remove described photoresist 210 by ashing (Ashing) and wet-cleaned.
As shown in figure 15, deposition first conductive layer 207 on described first dielectric layer 204 and oxide layer 206a, described first conductive can be polysilicon or doped polycrystalline silicon.The mode that forms can be chemical vapour deposition (CVD).Remove the polysilicon of described oxide layer 206a top by cmp.
As shown in figure 16, form hard mask layer 208 at described first conductive layer 207 and oxide layer 206a surface, described hard mask layer is a silicon nitride, and the mode of formation is chemical vapour deposition (CVD).Spin coating photoresist 210a on described hard mask layer forms channel patterns 212 by exposure imaging.
As shown in figure 17, by etching described channel patterns is transferred to formation channel patterns 212a on the hard mask layer 208.Remove described photoresist 210a
As shown in figure 18, as etching barrier layer, first conductive layer 207 and first dielectric layer 204 to the described etching stop layer 202 of channel patterns 212a bottom expose on the described hard mask layer 208 of etching, form groove 212b with described hard mask layer 208.Described etching stop layer 202 is the etching terminal detection layers that forms this groove 212b; in forming groove 212b process, be etched in and stop when described etching stop layer 202 exposes, can protect the conductive materials in the connecting hole 201 of described etching stop layer 202 lower floors to avoid the etching plasma damage.
The step of described formation groove 212b is at first transferring to described channel patterns 212 on the hard mask layer 208 from photoresist 210a by etching, remove described photoresist 210a, then with described hard mask layer 208 as etching barrier layer, continuing method that described first conductive layer 207 of etching and first dielectric layer 204 form groove 212b, can to improve the side wall profile of groove 212b of the resolution of groove 212b of formation and formation better.
Described hard mask layer 208 also can be protected in removing photoresist 210a process, and the material of described first conductive layer 207 is not subjected to the damage of ashing.
As shown in figure 19, the etching stop layer 202 of etching groove 212b bottom exposes to the conductive materials in the described connecting hole 201, and filled media layer 214 in described groove 212b, described dielectric layer material are silica, silicon nitride or its combination.
As shown in figure 20, return to carve described dielectric layer 214, and form the second dielectric layer 214a at the reserve part dielectric layer material of described groove 212b sidewall, groove 212b exposes the bottom conductive materials in the described connecting hole 201.
As shown in figure 21, filled conductive layer 218 in described groove 212b, described conductive layer 218 materials can be polysilicons.The method that forms described conductive layer 218 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
As shown in figure 22, spin coating photoresist and graphical on described conductive layer 218, remove the conductive that is not covered by photoresist by etching, form the second conductive layer 218a at described second dielectric layer 214a sidewall and groove 212b bottom, the described second conductive layer 218a is first pole plate of capacitor, and the described second conductive layer 218a top is lower than described first conductive layer 207 tops.Remove described photoresist.
As shown in figure 23, remove the hard mask layer 208 and the second dielectric layer 214a of described first conductive layer 207 tops, described first conductive layer, 207 upper surfaces are exposed.
As shown in figure 24, form dielectric layer 220 in the groove above the described second conductive layer 218a and on described first conductive layer 207, described dielectric layer 220 materials can be silica, silicon nitride or its combination.
As shown in figure 25, spin coating photoresist and graphical on described dielectric layer 220, etching forms the 3rd dielectric layer 220a, and expose at dielectric layer 220 to described first conductive layer 207 tops of removing on described first conductive layer 207.
As shown in figure 26, form the 3rd conductive layer 222 on described first dielectric layer 207 and on the 3rd dielectric layer 220a in the groove.Described the 3rd conductive layer 222 materials can be a kind of or its combinations in polysilicon, titanium, tungsten, the titanium nitride.Before forming the 3rd conductive layer 222, also can go ahead of the rest into tack coat (not drawing in the present embodiment accompanying drawing), described bonding layer material can be a titanium, materials such as titanium nitride, described tack coat increase the caking property of the 3rd conductive layer 222 and the 3rd dielectric layer 220a and stop the 3rd conductive layer 222 materials to spread to change the 3rd dielectric layer 220a dielectric constant to described the 3rd dielectric layer 220a.Described the 3rd conductive layer 222 is electrically connected with described first conductive layer 207, forms capacitor second pole plate jointly.The second dielectric layer 214a between described the 3rd dielectric layer 220a and the described second conductive layer 218a and first conductive layer 207 forms dielectric between capacitor plate jointly.
In the manufacture method of the present invention, deposition forms first conductive layer 207 on described first dielectric layer 204, described first conductive layer at first is formed as the part of electric capacity second pole plate, relatively and prior art, avoid in subsequent technique having overcome the interstitial problem of filling groove for forming the process that the first etching groove of this part recharges.Also avoided simultaneously removing the problem that capacitor plate collapses in the photoresist cleaning process, make the capacitor that forms have higher robustness (robust), thereby the defective that reduces to form in the manufacture process has reduced the electrical failure of the device that forms in the postorder multistep.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1, a kind of manufacture method of holding capacitor is characterized in that comprising:
On the insulating barrier of substrate, form first dielectric layer;
On described first dielectric layer, form first conductive layer;
Described first conductive layer of etching and first dielectric layer form groove selectively, and described channel bottom exposes described surface of insulating layer;
Form second dielectric layer at described trenched side-wall;
Form second conductive layer at the described channel bottom and the second dielectric layer sidewall, the top of described second conductive layer is lower than the top of described first conductive layer;
Second conductive layer surface of the second conductive layer sidewall, top and described channel bottom in described groove forms the 3rd dielectric layer;
Fill the 3rd conductive layer on the 3rd dielectric layer in described first conductive layer and groove.
2, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the described first dielectric layer material can be a boron-phosphorosilicate glass.
3, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described first conductive layer is a polysilicon.
4, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: be formed with etching stop layer between the described insulating barrier and first dielectric layer.
5, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the described second dielectric layer material comprises silica, silicon nitride or its combination.
6, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the formation step of described second conductive layer is:
Filled conductive layer on second dielectric layer in described groove;
Spin coating photoresist and graphical described photoresist on described conductive layer;
Remove the conductive layer that is not covered in the groove by etching and form second conductive layer by photoresist;
Remove described photoresist.
7, as the manufacture method of claim 1 or 6 described holding capacitors, it is characterized in that: described second conductive comprises polysilicon.
8, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the formation step of described the 3rd dielectric layer is:
Filled media layer on second conductive layer in described groove;
Spin coating photoresist and graphical described photoresist on described dielectric layer;
Remove the dielectric layer that is not covered in the groove by etching and form the 3rd dielectric layer by photoresist;
Remove described photoresist.
9, as the manufacture method of claim 1 or 8 described holding capacitors, it is characterized in that: described the 3rd dielectric layer material comprises silica, silicon nitride or its combination.
10, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described the 3rd conductive layer comprises a kind of or its combination in polysilicon, titanium, tungsten, the titanium nitride.
11, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: this method further comprises: form tack coat between described the 3rd conductive layer and described the 3rd dielectric layer.
12, the manufacture method of holding capacitor as claimed in claim 11 is characterized in that: described bonding layer material can be titanium or titanium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100299165A CN100517559C (en) | 2006-08-10 | 2006-08-10 | Making method for storage capacitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100299165A CN100517559C (en) | 2006-08-10 | 2006-08-10 | Making method for storage capacitor |
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| CN101123169A CN101123169A (en) | 2008-02-13 |
| CN100517559C true CN100517559C (en) | 2009-07-22 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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Effective date of registration: 20111109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |