CN111524887A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN111524887A
CN111524887A CN201910104364.7A CN201910104364A CN111524887A CN 111524887 A CN111524887 A CN 111524887A CN 201910104364 A CN201910104364 A CN 201910104364A CN 111524887 A CN111524887 A CN 111524887A
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conductive
layer
air gap
semiconductor device
dielectric layer
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CN201910104364.7A
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CN111524887B (en
Inventor
简毅豪
竹迫寿晃
任楷
魏宏谕
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The method of manufacturing a semiconductor device includes forming a first dielectric layer and a plurality of first conductive structures on a substrate, the first dielectric layer being located between the plurality of first conductive structures. The method of manufacturing a semiconductor device also includes forming a trench in the first dielectric layer and between the plurality of first conductive structures. The method of manufacturing a semiconductor device further includes forming a liner material on sidewalls and a bottom of the trench, and forming a conductive plug on the liner material in the trench. The method of manufacturing the semiconductor device further includes removing the liner material to form an air gap, wherein the air gap is between the conductive plug and the first dielectric layer. The semiconductor and the manufacturing method thereof can effectively reduce the parasitic capacitance of the bit line, thereby keeping good capacitor amplification.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device applied to a Dynamic Random Access Memory (DRAM) and a method for fabricating the same.
Background
In current random access memory (DRAM) architectures, capacitors are bridged by capacitor contacts (capacitorcontacts), and bit lines are arranged close to the capacitor contacts. The parasitic capacitance of the bit line is influenced by many factors, but mainly comes from the bit line-capacitance contact parasitic capacitance (BL-CC capacitance) between the bit line and the capacitance contact. However, as the size of the manufacturing process is continuously reduced, the distance between the bit line and the capacitor contact in the random access memory is shorter and shorter, and as the capacity requirement of the random access memory is larger and larger, the length of the bit line is longer and longer. These will result in an increase in the parasitic capacitance of the bit line, which in turn will reduce the capacitance amplified signal.
Therefore, a semiconductor device and a method for manufacturing the same are needed to reduce the parasitic capacitance of the bit line.
Disclosure of Invention
Some embodiments of the present invention provide methods of fabricating semiconductor devices. The method of manufacturing a semiconductor device includes forming a first dielectric layer and a plurality of first conductive structures on a substrate, the first dielectric layer being located between the plurality of first conductive structures. The method of manufacturing a semiconductor device also includes forming a trench in the first dielectric layer and between the plurality of first conductive structures. The method of manufacturing a semiconductor device further includes forming a liner material on sidewalls and a bottom of the trench, and forming a conductive plug on the liner material in the trench. The method of manufacturing the semiconductor device further includes removing the liner material to form an air gap, wherein the air gap is between the conductive plug and the first dielectric layer.
Some embodiments of the present invention provide a semiconductor device. The semiconductor device comprises a plurality of first conductive structures and a plurality of second conductive structures, wherein the first conductive structures are arranged on a substrate, and the second conductive structures are arranged on the substrate and positioned among the plurality of first conductive structures. The second conductive structure comprises an ohmic contact layer, a conductive plug, a metal liner and an air gap. The conductive plug is located on the ohmic contact layer. An air gap is located on the ohmic contact layer and on a sidewall of the conductive plug. The metal lining layer is positioned between the ohmic contact layer and the air gap and positioned on the side wall of the conductive plug.
Based on the above, the semiconductor and the manufacturing method thereof provided by the invention can effectively reduce the parasitic capacitance of the bit line, thereby maintaining a good capacitor amplification signal.
Drawings
In order to make the features and advantages of the present invention comprehensible, various embodiments accompanied with figures are described in detail as follows:
fig. 1 is a schematic top view of a semiconductor device according to some embodiments of the present invention.
Fig. 2 is a schematic cross-sectional view of the semiconductor device shown along the sectional line I-I in fig. 1 according to some embodiments of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to some other embodiments of the present invention.
Fig. 4A-4M are cross-sectional views illustrating various stages in the formation of a semiconductor device, in accordance with some embodiments of the present invention.
Fig. 5A-5B are schematic cross-sectional views illustrating different stages in forming a semiconductor device, according to some other embodiments of the present invention.
Reference numerals:
10. 20 semiconductor device 230 metal liner
100 first conductive structure 240 air gap
110-conductive structure 240 a-top
120-conductive contact 250-conductive layer
130-insulating layer 300-substrate
200-second conductive structure 301-isolation structure
210-ohmic contact layer 303-active region
220-conductive plug 400-first dielectric layer
220a, 230a, 430 a-top surface 410, 830-groove surface
420- metal material 220S, 430S-side wall
430-gasket material 500-conductive connection layer
900-dry etching process 600-capacitor element
910-cleaning process after etching 700-third conductive structure
CBL parasitic capacitance 800 second dielectric layer
H1, H2-height 810, 820-dielectric layer
I-section line
Detailed Description
The present invention is described more fully hereinafter with reference to the accompanying drawings of embodiments of the invention. However, the present invention may be implemented in various different embodiments, and should not be limited to the embodiments described herein. The thickness of layers and regions in the figures may be exaggerated for clarity and the same or similar reference numbers indicate the same or similar elements throughout the figures.
Fig. 1 is a schematic top view of a semiconductor device 10 according to some embodiments of the present invention; fig. 2 is a cross-sectional view of the semiconductor device 10, taken along the line I-I in fig. 1, according to some embodiments of the present invention.
As shown in fig. 1 and 2, the semiconductor device 10 includes a plurality of first conductive structures 100 and second conductive structures 200, wherein the first conductive structures 100 are disposed on a substrate 300, and the second conductive structures 200 are disposed on the substrate 300 and between the first conductive structures 100. The second conductive structure 200 includes an ohmic contact layer 210, a conductive plug 220, a metal liner 230, and an air gap 240. The conductive plug 220 is positioned on the ohmic contact layer 210. The air gap 240 is located on the ohmic contact layer 210 and on the sidewall 220S of the conductive plug 220. The metal liner layer 230 is located between the ohmic contact layer 210 and the air gap 240 and on the sidewall 220S of the conductive plug 220.
As shown in fig. 2, the metal liner 230 may directly contact the conductive plug 220, for example, and the air gap 240 may directly contact the conductive plug 220, for example.
As shown in fig. 1, the semiconductor device 10 may further include a plurality of third conductive structures 700, wherein the third conductive structures 700 and the first conductive structures 100 are configured to extend in directions perpendicular to each other when viewed from the top. In some embodiments, the first conductive structure 100 is, for example, a bit line structure, the second conductive structure 200 is, for example, a capacitor contact structure, the third conductive structure 700 is, for example, an embedded (embedded) word line structure, and the semiconductor device 10 is, for example, a dynamic random access memory structure.
The semiconductor device 10 may further include an isolation structure 301 formed in the substrate 300, the isolation structure 301 defining a plurality of active regions 303 in the substrate 300.
In some embodiments, the substrate 300 may comprise a semiconductor substrate, such as a silicon substrate or a silicon germanium substrate, and the isolation structure 301 may comprise a Shallow Trench Isolation (STI).
In some embodiments, the first conductive structure 100 may include a conductive structure 110 (e.g., a bit line) and a conductive contact 120 (e.g., a bit line contact), the conductive contact 120 being located between the active region 303 and the conductive structure 110. In some embodiments, the conductive structure 110 and the conductive contact 120 may each be made of, for example, polysilicon, metal, or other suitable conductive material.
As shown in fig. 2, the semiconductor device 10 may further include a plurality of insulating layers 130, wherein the insulating layers 130 are located between the isolation structures 301 and a portion of the conductive contacts 120. In some embodiments, the insulating layer 130 may be made of, for example, silicon oxide or other suitable insulating material. It is noted that, for simplicity and clarity of the embodiment of the present invention, only the conductive contact 120 connected to the active region 303 is illustrated in fig. 1, and the conductive contact 120 disposed on the insulating layer 130 is omitted.
The second conductive structure 200 may further include a conductive layer 250, the conductive layer 250 being formed between the ohmic contact layer 210 and the substrate 300. In some embodiments, the conductive layer 250 may comprise a conductive material, such as a polysilicon layer.
In some embodiments, the ohmic contact layer 210 may comprise a metal silicide, such as cobalt silicide (CoSix, x is less than or equal to 2). The ohmic contact layer 210 is, for example, a cobalt silicide layer, and can be used to reduce the resistance between the conductive layer 250 and the conductive plug 220.
In some embodiments, the conductive plug 220 may comprise a metal. For example, the conductive plug 220 may comprise tungsten, other suitable metallic materials, or any combination thereof.
In some embodiments, the metal liner 230 may comprise a metal or a metal nitride. For example, the metal liner 230 may comprise titanium, titanium nitride, tantalum nitride, or any combination thereof.
In some embodiments, the metal liner layer 230 is disposed between the ohmic contact layer 220 and the air gap 240, and can isolate the air gap 240 and the ohmic contact layer 220 from each other, so that the metal liner layer 230 not only facilitates the growth of the metal material of the conductive plug 220, but also protects the ohmic contact layer 220 from being damaged by a subsequent etching step and/or a cleaning step during the manufacturing process of the semiconductor device.
In some embodiments, the top surface 230a of the metal liner 230 may be lower than the top surface 220a of the conductive plug 220. In some embodiments, the top surface 230a of the metal liner 230 may be exposed in the air gap 240, and the top 240a of the air gap 240 and the top surface 220a of the conductive plug 220 may be substantially coplanar. Specifically, the air gap 240 may be stacked on the metal liner 230, and the stacked air gap 240 and the metal liner 230 may jointly surround and cover the sidewall of the conductive plug 220.
In some embodiments, the total height H2 of the metal liner 230 and the air gap 240 is, for example, substantially equal to the height of the conductive plug 220. In some embodiments, the height H1 of the metal liner 230 is less than the total height H2 of the metal liner 230 and the air gap 240, so that the air gap 240 stacked on the metal liner 230 and having a low dielectric constant can effectively help to reduce the parasitic capacitance CBL formed between the second conductive structure 200 and the adjacent first conductive structure 100.
The semiconductor device 10 may further include a first dielectric layer 400 disposed on the substrate 300. In some embodiments, the first dielectric layer 400 may comprise a nitride, and the first dielectric layer 400 is, for example, a silicon nitride layer.
The first dielectric layer 400 may be located between the first conductive structure 100 and the second conductive structure 200, and the air gap 240 may be located between the conductive plug 220 and the first dielectric layer 400. In some embodiments, the air gap 240 may be located between the conductive plug 220 of the second conductive structure 200 and the first conductive structure 100, so that the parasitic capacitance CBL formed between the second conductive structure 200 and the adjacent first conductive structure 100 may be effectively reduced.
More specifically, since the capacitance is proportional to the dielectric constant of the medium (C ═ a/d, where C is the capacitance and is the dielectric constant of the medium, a is the surface area, and d is the thickness of the medium), the air gap 240 and the first dielectric layer 400 of the second conductive structure 200 are located between the conductive plug 220 of the second conductive structure 200 and the conductive structure 110 of the first conductive structure 100, so that the combination of the air gap 240 and the first dielectric layer 400 constitutes the medium between the two conductive structures, and the low dielectric constant of the air gap 240 (e.g., the dielectric constant air ai is 1.0006) makes the equivalent dielectric constant of this medium lower than the dielectric constant of the first dielectric layer 400 itself. Specifically, the air gap 240 with a low dielectric constant helps to further effectively reduce the parasitic capacitance CBL between the two conductive structures that would otherwise be caused only by the relatively high dielectric constant of the first dielectric layer 400 (e.g., the dielectric constant of silicon nitride, SiN of 7).
The semiconductor device 10 may further include a conductive connection layer 500 and a capacitive element 600. The conductive connection layer 500 may be disposed on the conductive plug 220 and the air gap 240, and the capacitive element 600 may be disposed on the conductive connection layer 500.
The semiconductor device 10 may further include a second dielectric layer 800, the second dielectric layer 800 may be disposed on the first dielectric layer 400, and the conductive connection layer 500 and the capacitive element 600 may be formed in the second dielectric layer 800. In some embodiments, the second dielectric layer 800 may comprise silicon oxide, silicon nitride, or a combination thereof.
Fig. 3 is a cross-sectional schematic view of a semiconductor device 20 according to some other embodiments of the present invention. The top view of the semiconductor device 20 is similar to that shown in fig. 1, and the cross-sectional view of the semiconductor device 20 shown in fig. 3 can be seen as being taken along the line I-I in fig. 1. Unless otherwise specified, similar elements in the embodiment shown in fig. 3 and the previous embodiments are denoted by the same reference numerals and may be formed by similar materials and methods, and thus are not described again.
According to some other embodiments of the present invention, the semiconductor device 20 shown in fig. 3 has a structure similar to that shown in fig. 2, except that the second conductive structure 200 of the semiconductor device 20 does not include a metal liner, the air gap 240 surrounds and covers the sidewall of the conductive plug 220, and the air gap 240 is connected to the underlying ohmic contact layer 210, such that the air gap 240 with a low dielectric constant helps to further effectively reduce the parasitic capacitance CBL between the first conductive structure 100 and the second conductive structure 200, which is otherwise caused only by the relatively high dielectric constant of the first dielectric layer 400.
The embodiment of the invention also provides a manufacturing method of the semiconductor device. Fig. 4A-4M are cross-sectional views illustrating the formation of a semiconductor device 20 at various stages according to some embodiments of the present invention. Unless otherwise specified, similar elements in the following embodiments and the preceding embodiments are denoted by the same reference numerals, and thus are not described again.
Referring to fig. 4A, a first dielectric layer 400 and a plurality of first conductive structures 100 are formed on a substrate 300, wherein the first dielectric layer 400 is located between the first conductive structures 100. A dielectric layer (not shown) may be formed on the substrate 300, and a plurality of trenches (not shown) may be formed in the dielectric layer by an etching process, for example, wherein the bottoms of some trenches are exposed to the top surface of the active region 303 of the substrate 300, and the bottoms of other trenches are exposed to the top surface of the isolation structure 301 of the substrate 300.
Next, an insulating layer 130 is formed in some of the trenches exposing the top surface of the isolation structure 301, and then a conductive contact 120 is formed on the insulating layer 130 in some of the trenches and the top surface of the active region 303 in the remaining trenches, and then a conductive structure 110 is formed on the conductive contact 120.
Referring to fig. 4B, a trench 410 is formed in the first dielectric layer 400 and between two adjacent first conductive structures 100.
For example, the first dielectric layer 410 may be etched by using a mask pattern (not shown) on the first dielectric layer 400 as an etching mask, and the trench 410 may be formed by etching until the surface of the substrate 300 is exposed.
Referring to fig. 4C, a conductive layer 250 and an ohmic contact layer 210 are formed in the trench 410, and the ohmic contact layer 210 is formed on the conductive layer 250.
In some embodiments, a metal layer may be formed on the upper surface of the conductive layer 250, and then a Physical Vapor Deposition (PVD) process may be performed to form the ohmic contact layer 210 comprising metal silicide.
In some embodiments, when the conductive layer 250 comprises a silicon material (e.g., polysilicon), a high temperature annealing process may be performed on the metal layer to silicide the metal layer, thereby forming a metal silicide layer. In one embodiment, the metal layer is, for example, a cobalt metal layer, and the metal silicide layer is, for example, a cobalt silicide layer.
Referring to fig. 4D, a liner material 430 is formed on the sidewalls and bottom of the trench 410 and on the top of the first dielectric layer 400. In some embodiments, the liner material 430 is, for example, a metal liner material, which may comprise a metal or a metal nitride. Referring also to fig. 1, the top view of the trench 410 is similar to the top view of the second conductive structure 200, such that the trench 410 has a complete sidewall around it, and the liner material 430 may be formed on the entire sidewall, bottom, and top of the first dielectric layer 400 inside the trench 410, for example.
Referring to fig. 4E, a metal material 420 is deposited on the liner material 430 in the trench 430 to fill the trench 430 and cover the top surface of the first dielectric layer 400.
Referring to fig. 4F, a planarization process, such as a chemical mechanical polishing process, is performed on the metal material 420 to remove the metal material 420 on the top surface of the first dielectric layer 400, and the metal material 420 remaining in the trench 430 and on the liner material 430 forms the conductive plug 220, and the liner material 430 directly contacts the conductive plug 220. Since the liner material 430 comprises titanium, titanium nitride, tantalum nitride, or any combination thereof, the liner material 430 facilitates the deposition growth of the metal material 420 and improves the adhesion of the subsequently formed conductive plug 220, so that the peeling (peeling) of the formed conductive plug 220 is not likely to occur, and the stability of the semiconductor device can be improved.
Referring to fig. 4G and 4H, the liner material 430 may be removed by performing a dry etching process 900 to form the air gap 240, wherein the air gap 240 is formed between the conductive plug 220 and the first dielectric layer 400. In some embodiments, the dry etch process 900 may include a gaseous etch or a plasma etch. According to the embodiment of the invention, by using the dry etching process with high selectivity, the liner material 430 can be removed simultaneously to form the air gap 240 and achieve a structure that does not damage or only minimally damages the first dielectric layer 400 and the conductive plug 220 as much as possible.
Referring to fig. 4H, the liner material 430 is etched from the exposed top surface 430a of the liner material 430 toward the substrate 300 to remove the liner material 430 and form the air gap 240.
According to the embodiment of the invention, the liner material 430 is formed first, which is helpful for preventing the formed conductive plug 220 from peeling off, and then the liner material 430 is removed to form the air gap 240, so that the air gap 240 can be utilized to effectively reduce the parasitic capacitance CBL formed between the second conductive structure 200 and the adjacent first conductive structure 100, and thus, the air gap 240 is manufactured by utilizing the space where the liner material 430 is originally formed, and the air gap 240 replaces the arrangement position and the device volume of the original liner material 430, so that the air gap is manufactured without further increasing the additional device volume, and the formation and growth of the conductive plug 220 can be promoted and the parasitic capacitance in the semiconductor device can be reduced in the process.
Furthermore, according to the embodiment of the present invention, the air gap 240 is formed by utilizing the space originally formed with the liner material 430, so that it is not necessary to add additional elements other than the metal liner around the conductive plug 220 (for example, an additional sacrificial layer is formed in the trench 430 and then the sacrificial layer is removed to form the air gap), and therefore, the filling volume of the metal material 420 is not required to be sacrificed due to the arrangement of the additional elements, so that the formed conductive plug 220 can have a larger volume, and further, the better conductivity of the conductive plug 220 is maintained.
Furthermore, if an additional element other than the metal liner is added into the trench 430 before the metal material 420 is filled, the cross-sectional dimension of the trench 430 into which the metal material 420 is to be filled is reduced, so that the trench 430 has a larger aspect ratio (aspect ratio), which may cause incomplete filling during the filling of the metal material 420 to generate voids (voids) or gaps (seam) in the formed conductive plug 220; according to the embodiment of the present invention, it is not necessary to reduce the predetermined cross-sectional dimension of the conductive plug 220 for forming the air gap, so as to avoid the poor filling of the metal material 420, and achieve the effect of manufacturing the conductive plug 220 with good filling property and good conductivity.
In some embodiments, the dry etching process 900 is performed to remove the liner material 430 until the ohmic contact layer 210 is exposed, the air gap 240 is formed to surround and cover the sidewall of the conductive plug 220, the air gap 240 can be directly connected to the ohmic contact layer 210, and a portion of the liner material 430 under the conductive plug 220 is not removed by the dry etching process 900.
In some embodiments, after removing the liner material 430, the sidewalls 430S of the trench 430 and the sidewalls 220S of the conductive plug 220 are exposed. Sidewalls 430S of the trench 430 are formed by the first dielectric layer 400.
Referring to fig. 4I, a post-etch cleaning process 910 is performed on the sidewalls 430S of the trench 430 and the sidewalls 220S of the conductive plug 220.
Referring to fig. 4J, a conductive connection layer 500 is formed on the conductive plug 220 and the air gap 240. For example, a whole conductive material layer (not shown) may be formed on the top surface of the first dielectric layer 400, the top surface of the conductive plug 220 and the air gap 240, and then a patterning process may be performed on the conductive material layer to form a plurality of conductive connection layers 500, wherein each conductive connection layer 500 is correspondingly disposed on one conductive plug 220 and one air gap 240 adjacent to the sidewall 220S thereof.
Referring to fig. 4K, a dielectric layer 810 is formed on the conductive connection layer 500, the dielectric layer 810 covers the top surfaces of the conductive connection layer 500 and the first dielectric layer 400, and then a dielectric layer 820 is formed on the insulating layer 810. The dielectric layers 810 and 820 constitute a second dielectric layer 800. In some embodiments, the dielectric layer 810 comprises silicon nitride, the dielectric layer 820 comprises silicon oxide, and the dielectric layer 810 (silicon nitride layer) surrounds the conductive connection layer 500 and covers the top surface of the first dielectric layer 400, thereby having an etching stop effect, preventing the etchant (e.g., hydrofluoric acid or other similar strong acid) of the etching process from undesirably penetrating between the conductive connection layers 500 to damage the first dielectric layer 400 and other layers and/or elements therebelow, and increasing the process window of the etching process.
Referring to fig. 4L, a trench 830 is formed in the second dielectric layer 800 and corresponding to the conductive connection layer 500. For example, the second dielectric layer 800 may be etched through a mask pattern (not shown) on the second dielectric layer 800 as an etching mask, and the trench 830 may be formed by etching until the surface of the conductive connection layer 500 is exposed.
Referring to fig. 4M, a capacitor element 600 is formed in the trench 830. Thus, the semiconductor device 20 shown in fig. 3 is formed.
Fig. 5A-5B are cross-sectional views illustrating various stages in forming a semiconductor device, according to some embodiments of the present invention. Please refer to fig. 4A to 4G and fig. 4J to 4M simultaneously. Unless otherwise specified, similar elements in the following embodiments and the previous embodiments are denoted by the same reference numerals and may be formed by similar materials and methods, and thus are not described again.
First, the process shown in fig. 4A to 4G is performed to form the structure shown in fig. 4G, and the steps and details of the process are as described above and will not be described herein again.
Next, referring to fig. 4G and fig. 5A, a dry etching process 900 is performed to etch the liner material 430 from the exposed top surface 430a of the liner material 430 toward the substrate 300 to partially remove the liner material 430 and form an air gap 240 and a metal liner 230 under the air gap 240, wherein the metal liner 230 is on the ohmic contact layer 210, and the metal liner 230 is between the ohmic contact layer 210 and the air gap 240. After forming the metal liner 230, a post etch cleaning process 910 is performed on the sidewalls of the trench 430 and the sidewalls of the conductive plug 220.
Next, referring to fig. 4J to fig. 4M and fig. 5B, a conductive connection layer 500 is formed on the conductive plug 220 and the air gap 240, and a capacitor 600 is formed on the conductive connection layer 500. Also, a second dielectric layer 800 is formed, and the conductive connection layer 500 and the capacitive element 600 are located in the second dielectric layer 800. Thus, the semiconductor device 10 shown in fig. 1 to 2 is formed.
Although the present invention has been described with reference to the above embodiments, it is not intended to limit the invention. Those skilled in the art to which the invention pertains will readily appreciate that numerous changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising:
forming a first dielectric layer and a plurality of first conductive structures on a substrate, wherein the first dielectric layer is positioned among the plurality of first conductive structures;
forming a trench in the first dielectric layer and between the plurality of first conductive structures;
forming a liner material on a sidewall and a bottom of the trench;
forming a conductive plug over the liner material in the trench; and
removing the liner material to form an air gap, wherein the air gap is located between the conductive plug and the first dielectric layer.
2. The method of claim 1, wherein the liner material comprises a metal or a metal nitride and the conductive plug comprises a metal.
3. The method of claim 1, wherein the liner material directly contacts the conductive plug.
4. The method of claim 1, wherein the liner material is removed by performing a dry etch process.
5. The method of claim 1, wherein removing the liner material comprises:
etching the liner material from an exposed top surface of the liner material in a direction toward the substrate to partially remove the liner material and form the air gap and a liner layer underlying the air gap.
6. The method of claim 5, wherein prior to forming said liner material on said sidewalls of said trench, said method further comprises:
forming an ohmic contact layer in the trench;
wherein the liner layer is located between the ohmic contact layer and the air gap.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a conductive connection layer on the conductive plug and the air gap after removing the liner material to form the air gap; and
a capacitive element is formed on the conductive connection layer.
8. A semiconductor device, comprising:
a plurality of first conductive structures disposed on a substrate; and
a second conductive structure disposed on the substrate and between the plurality of first conductive structures, wherein the second conductive structure comprises:
an ohmic contact layer;
a conductive plug on the ohmic contact layer;
an air gap on the ohmic contact layer and on a sidewall of the conductive plug; and
a metal lining layer located between the ohmic contact layer and the air gap and on the sidewall of the conductive plug.
9. The semiconductor device according to claim 8, further comprising:
and a first dielectric layer disposed on the substrate and between the first conductive structures and the second conductive structures, wherein the air gap is disposed between the conductive plug and the first dielectric layer.
10. The semiconductor device according to claim 8, further comprising:
a conductive connection layer disposed on the conductive plug and the air gap; and
and the capacitor element is arranged on the conductive connecting layer.
11. The semiconductor device of claim 8, wherein said metal liner comprises a metal or a metal nitride and said conductive plug comprises a metal.
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