KR101096215B1 - Method for fabricating semiconductor device with buried gate - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device having a buried gate which reduces a loss of a gate insulating film when forming a buried gate and improves a defect of a buried gate due to residues, the method comprising: forming a hard mask pattern on a substrate; Etching the substrate using the hard mask pattern as an etch barrier to form a trench for a buried gate; Forming a gate insulating film along a step of the entire structure including the trench; Forming a buried gate conductive film filling the trench on the gate insulating film; A first etching step of recessing the conductive film and the gate insulating film to a predetermined depth; And forming a buried gate by second-etching the conductive layer so that the conductive layer remains at a predetermined depth in the trench, thereby improving a problem in which the top corner of the trench is exposed, attacking and loss of the gate insulating layer. (Loss) is reduced, thereby improving the reliability of the device, and by etching the gate insulating film on the sidewall of the hard mask by primary etching, the subsequent hard mask film removing process is smoothly performed, thereby preventing the occurrence of residues. It is effective.

Landfill gate, selectivity ratio

Description

A method of manufacturing a semiconductor device having a buried gate {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a semiconductor device having a buried gate.

DRAM cell structures have changed due to the weakening of device characteristics as design rules become smaller. Recently, the DRAM cell has a recessed gate structure in order to improve refreshing characteristics. The structure of the DRAM cell forms a trench on a silicon substrate to fill polysilicon, and then a metal thin film thereon. And a word line (WL) pattern are formed by performing an exposure process and an etching process. Recess gates have gate oxides formed along the holes to make the channel between the source and the drain longer, so that the refresh characteristics can be improved compared to the conventional stack type structure.

On the other hand, there is a problem that the processing speed of the memory cell is reduced by the parasitic capacitance in the memory cell. Parasitic capacitance refers to various kinds of capacitances generated by conductive materials such as word lines, bit lines, and upper electrodes, and insulating films therebetween. Even when the recess gate structure is applied, it is difficult to improve the parasitic capacitance problem.

Accordingly, in order to improve problems such as parasitic capacitance, buried gate (BG) structures have recently been researched and developed.

1A to 1C illustrate a buried gate manufacturing method according to the prior art.

As shown in FIG. 1A, after defining the active region 12 in the semiconductor substrate 11, a hard mask layer 13 is formed. Here, the hard mask film 13 is a nitride film.

Next, the trench 14 may be formed by etching the active region 12 using the hard mask layer 13 as an etch barrier.

As shown in FIG. 1B, a gate oxidation process for forming the gate insulating film 15 is performed.

As illustrated in FIG. 1C, the gate conductive film used as the buried gate is deposited to gap fill the trench, and then the CMP (Chemical Mechanical Polishing) process and the etchback process are sequentially performed to recess the buried gate to a predetermined depth. (16) is formed.

However, the prior art cannot avoid the loss of the gate insulating film 15 at the top corner of the trench (see 'A' in FIG. 1C) during the etch back process for forming the buried gate. As such, when the gate insulating film 15 is excessively lost, the thickness of the remaining gate insulating film (Remain Gate Oxide) becomes considerably thinner than that of the trench sidewall (Thinning), thereby deteriorating the refresh characteristics of the semiconductor device.

Figure 2 is a photograph showing the result after forming the buried gate according to the prior art, it can be seen that the gate insulating film is thinning in the top corner of the trench.

In order to improve the problem of the prior art as described above, etching is performed under conditions having a high selectivity with the gate conductive film so that the gate insulating film 15 in the trench can be sustained without being lost.

However, when the etching is performed under a condition having a high selectivity, the gate insulating film 15 on the side of the hard mask film 13 also does not proceed well, so that the oxide film is removed during the subsequent removal of the nitride film hard mask film 13. The strip process is difficult due to the gate insulating film 15.

3A and 3B are photographs showing the results of the etching performed under the condition of having a high selectivity, and it can be seen that the gate insulating film remains on the sidewall of the hard mask film.

When etching is performed under a condition having a high selectivity, another problem is that when a fine residual material is present in the planarization process, the gate conductive layer is not etched well, resulting in a defect. This is because the etching of the metal series with the high selectivity etching proceeds smoothly, but the residue or the oxide film is not etched well.

Figure 3c is a photograph showing the defects caused by the fine residual material, it can be seen that the residues (eg, slurry residues) remaining in the oxide film or the previous process is not etched well, a defect occurs. This defect occurs in a whirlwind form throughout the wafer.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device having a buried gate which reduces a loss of a gate insulating film when forming a buried gate.

Another object is to provide a method for manufacturing a semiconductor device having a buried gate that improves a defect of the buried gate due to residues or the like.

A semiconductor device manufacturing method having a buried gate of the present invention for achieving the above object comprises the steps of forming a hard mask pattern on a substrate; Etching the substrate using the hard mask pattern as an etch barrier to form a trench for a buried gate; Forming a gate insulating film along a step of the entire structure including the trench; Forming a buried gate conductive film filling the trench on the gate insulating film; A first etching step of recessing the conductive film and the gate insulating film to a predetermined depth; And forming a buried gate by secondary etching the conductive layer so that the conductive layer remains at a predetermined depth in the trench.

In particular, the conductive film is a metal film, the conductive film is formed in a single layer or a multilayer, the conductive film includes at least one selected from the group consisting of tantalum nitride film (TaN), titanium nitride film (TiN) and tungsten film (W) The conductive film is characterized in that a single layer of TiN or TaN, a multilayer structure of TiN / W or TaN / W.

In addition, the gate insulating film is characterized in that the oxide film.

In addition, the first etching proceeds to a low selectivity etching process where the metal film and the oxide film have similar etching rates, wherein the primary etching uses SF ₆ gas as the main etching gas, and the primary etching is applied with a bias power. It is not characterized in that the progress in the pressure of 7mTorr ~ 15mTorr.

In addition, the secondary etching proceeds to an etching having a selectivity with respect to the oxide film, the secondary etching is the primary etching using SF ₆ gas as the main etching gas, the primary etching is not applied to the bias power It is characterized by proceeding at a pressure of 30mTorr ~ 50mTorr.

In the method of fabricating a semiconductor device having a buried gate according to the present invention, the first etching is performed under the condition that the selectivity between the oxide film and the metal film is low, and the second etching is performed under the condition that the selectivity between the oxide film and the metal film is high. When the gate insulating film is etched, there is an effect of improving the problem that the top corner of the trench 24 is exposed.

In addition, the attack and loss of the gate insulating layer are reduced by the high selectivity during the secondary etching, thereby improving the reliability of the device.

In addition, since the gate insulating film on the hard mask film sidewall is etched by the primary etching, the subsequent hard mask film removing process may be smoothly performed, and thus, residues may be prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

As shown in FIG. 4A, the active region 22 is formed in the semiconductor substrate 21. Here, the semiconductor substrate 21 includes a silicon substrate, and the active region 22 is formed by a device isolation process as is well known. The device isolation film will not be shown.

Next, the hard mask film 23 is formed. Here, the hard mask film 23 includes a nitride film. In addition, the hard mask layer 23 may include an oxide layer and a silicon oxynitride layer.

Subsequently, after the hard mask layer 23 is etched using the buried gate mask (not shown), the trench 24 in which the buried gate is buried is successively etched using the hard mask layer 23 as an etch barrier. Form. At this time, the trench 24 is formed by etching the active region 22 to a predetermined depth.

As shown in FIG. 4B, the sacrificial gate insulating layer 25 is formed through the sacrificial gate oxidation process. In this case, the gate insulating layer 25 may include a silicon oxide layer, and may be formed only on the surface of the trench 24 of the semiconductor substrate 21.

As shown in FIG. 4C, the gate conductive layer 26 is deposited on the entire surface until the trench 24 is gap-filled. The gate conductive layer 26 may include at least one selected from the group consisting of a tantalum nitride layer (TaN), a titanium nitride layer (TiN), and a tungsten layer (W). For example, the gate conductive film 26 may be formed of a two-layer structure such as TiN / W or TaN / W, which uses TiN or TaN alone or a tungsten film is laminated on a titanium nitride film and a tantalum nitride film.

Subsequently, a chemical mechanical polishing (CMP) process is performed to stop polishing on the surface of the hard mask film 23. As a result, the gate conductive film 26 is removed from the surface of the hard mask film 23 so that the gate conductive film 26 remains only between the trench 24 and the hard mask film 23. In addition, since the CMP process was performed to the target on which the surface of the hard mask film 23 is exposed, the gate insulating film 25 (see FIG. 4B) is removed from the surface of the hard mask film 23 to form the trench 24 and the hard mask film. The primary gate insulating film pattern 25A remains only on the sidewalls of 23.

As shown in FIG. 4D, the primary etching is performed to recess the gate conductive layer 26 (see FIG. 4C) and the primary gate insulating layer pattern 25A (see FIG. 4C) to a predetermined depth.

In particular, the primary etching may be performed under the condition that the primary gate insulating layer pattern 25A (see FIG. 4C) of the sidewall of the hard mask layer 23 is etched together with the gate conductive layer 26 (see FIG. 4C). That is, the primary etching is performed under conditions having low selectivity so that the gate conductive film 26 (see FIG. 4C), which is a metal film, and the primary gate insulating film pattern 25A (see FIG. 4C), which is an oxide film, are etched at similar etching rates. It is preferable.

For this purpose, in the primary etching process, SF ₆ gas is used as the main etching gas, and the bias power is not applied, and it is preferable to proceed at a pressure of at least 15 mTorr (7 mTorr to 15 mTorr).

By the primary etching, the gate conductive layer 26 (see FIG. 4C) and the primary gate insulating layer pattern 25A (see FIG. 4C) are recessed to a predetermined depth so that the primary gate conductive layer pattern 26A and the secondary gate insulating layer pattern ( 25B is formed, in which the height 'd' of the primary gate conductive film pattern 26A and the secondary gate insulating film pattern 25B is preferably left to be at least higher than the surface of the semiconductor substrate 21. . That is, it is preferable to leave the primary gate conductive film pattern 26A and the secondary gate insulating film pattern 25B so as to have a height of 400 kPa to 800 kPa from the semiconductor substrate 21.

As shown in FIG. 4E, the secondary etching is performed to recess the primary gate conductive layer 26A (see FIG. 4D). The recessed primary gate conductive film 26A (see FIG. 4D) becomes a buried gate 26B.

In particular, it is preferable that the secondary etching is performed by etching only the primary gate conductive film 26A (see FIG. 4D), and the secondary gate insulating film pattern 25B (see FIG. 4D) remains unetched. That is, a condition having a selectivity with respect to the secondary gate insulating film pattern 25B (see FIG. 4D), which is an oxide film, and a high selectivity for selectively etching only the primary gate conductive film 26A (see FIG. 4D), which is a metal film. It is preferable to proceed with secondary etching.

For this purpose, in the secondary etching process, SF ₆ gas is used as the main etching gas, and the bias power is not applied, and it is preferable to proceed at a pressure of at least 30 mTorr (30 mTorr to 50 mTorr). When etching is performed at a pressure of 30 mTorr to 50 mTorr, the free gas path of the etching gas decreases, thereby increasing the chemical etching characteristics and, conversely, lowering the physical etching characteristics. Therefore, metal films having strong chemical etching characteristics can be easily etched. On the contrary, in the case of an oxide film having strong bonding bonds and having strong physical etching characteristics, etching is difficult. Therefore, only the primary gate conductive layer 26A (see FIG. 4D) may be selectively etched without losing the secondary gate insulating layer pattern 25B (see FIG. 4D).

As described above, the first etching is performed under the condition that the selectivity between the oxide film and the metal film is low, and the recess is recessed to remain at a predetermined depth (for example, 400 kPa to 800 kPa) on the semiconductor substrate 21, and then the condition that the selectivity between the oxide film and the metal film is high. By selectively recessing only the first gate conductive layer 26A (see FIG. 4D) by performing the second etching process, the gate insulating layer is etched during the etching of the metal layer to reveal the top corner of the trench 24. It can be improved. In addition, the attack and loss of the gate insulating layer are reduced by the high selectivity during the secondary etching, thereby improving the reliability of the device.

In addition, since the gate insulating layer on the sidewall of the hard mask layer 23 is etched by the primary etching, the subsequent process of removing the hard mask layer 23 may be smoothly performed.

In addition, since the residues during the CMP of the gate conductive film are removed during the first etching of the low selectivity in FIG. 4C, defects due to the residues can also be prevented.

5A and 5B illustrate the distribution of a buried gate and defects according to an exemplary embodiment of the present invention. The gate insulating layer is almost removed from the sidewall of the hard mask layer, and the gate insulating layer is formed on the sidewall of the trench so that the top corner of the trench is not exposed. It can be confirmed that it remains. In addition, unlike the defects shown on the front surface of the wafer in a whirlwind shape in FIG. 3C, the defects are evenly distributed on the front surface of the wafer, and the defects are significantly reduced in FIG. 3C.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1a to 1c is a view showing a buried gate manufacturing method according to the prior art,

Figure 2 is a photograph showing the result after the buried gate formation according to the prior art,

3A and 3B are photographs showing the results of etching performed under conditions having a high selectivity;

4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention;

5A and 5B are photographs showing distribution of buried gates and defects according to an embodiment of the present invention.

Claims (12)

Forming a hard mask pattern on the substrate; Etching the substrate using the hard mask pattern as an etch barrier to form a trench for a buried gate; Forming a gate insulating film along a step of the entire structure including the trench; Forming a buried gate conductive film filling the trench on the gate insulating film; A first etching step of recessing the conductive film and the gate insulating film to a predetermined depth; And Forming a buried gate by performing secondary etching under a pressure higher than the primary etching so that the conductive film remains in the trench in a predetermined depth. Method of manufacturing a semiconductor device having a buried gate comprising Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The conductive film is a semiconductor device manufacturing method having a buried gate is a metal film Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, Claim 4 was abandoned when the registration fee was paid. 3. The method of claim 2, The conductive film has a buried gate including at least one selected from the group consisting of a tantalum nitride film (TaN), a titanium nitride film (TiN), and a tungsten film (W). Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3, The conductive film has a single layer of TiN or TaN, a semiconductor device manufacturing method having a buried gate of a multi-layer structure of TiN / W or TaN / W Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The gate insulating film is a semiconductor device manufacturing method having a buried gate is an oxide film Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 2 or 6, Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The first etching is a semiconductor device manufacturing method having a buried gate using SF ₆ gas as the main etching gas Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The first etching process is a semiconductor device manufacturing method having a buried gate that does not apply a bias power, but proceeds to a pressure of 7mTorr ~ 15mTorr Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 2 or 6, The secondary etching is a semiconductor device manufacturing method having a buried gate proceeds to the etching having a selectivity with respect to the oxide film Claim 11 was abandoned upon payment of a setup registration fee. The secondary etching is a semiconductor device manufacturing method having a buried gate using the primary etching SF ₆ gas as the main etching gas Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, The first etching process is a semiconductor device manufacturing method having a buried gate that does not apply a bias power, but proceeds to a pressure of 30mTorr ~ 50mTorr

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