KR101062833B1 - Method of forming contact plug of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a contact plug of a semiconductor device that can prevent a bridge phenomenon between plugs while preventing SAC fail when forming a contact hole using the SAC process, and for this purpose, the present invention is provided on a substrate on which a conductive film is formed. Forming a plurality of neighboring conductive patterns having a hard mask thereon; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on a target to which the etch stop layer is exposed; Depositing a buffer insulating layer having a thickness sufficient to alleviate the step difference generated during the planarization process; Selectively etching the buffer insulating layer, the interlayer insulating layer, and the etch stop layer to form a contact hole exposing the conductive layer; Forming a conductive film to fill the contact hole; And forming a plug in which the hard mask is exposed to form a planarization process and forming an isolated plug in the contact hole.

SAC, contact hole, plug, etch stop film, spacer, recess, buffer insulating film, planarization.

Description

FORMING METHOD OF CONTACT PLUG IN SEMICONDUCTOR DEVICE             

1A to 1C are cross-sectional views illustrating a cell contact forming process according to the prior art.

2A through 2E are cross-sectional views illustrating a cell contact plug forming process according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: substrate 201: device isolation film

202: gate insulating film 203: gate conductive film

204: gate hard mask 205: impurity diffusion region

206: etch stop film 207: interlayer insulating film

208: buffer insulating film 209: mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to prevent SAC fail when forming a contact hole using a Self Align Contact (hereinafter referred to as SAC) process, and to prevent defects during plug isolation. It relates to a method for forming a contact plug of a semiconductor device capable of suppressing the occurrence of defects.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the integration of semiconductor devices is accelerated, various elements constituting the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept is introduced.

In forming such a contact plug, a landing plug contact is known as having a larger area at the upper part than the lower part contacted to increase the contact area with a minimum area at the lower part and to increase the process margin for subsequent processes at the upper part. ) Technology has been introduced and commonly used.

In addition, in order to form such a contact, it is difficult to etch between structures having a high aspect ratio. In this case, an SAC process for obtaining an etching profile using an etching selectivity between two materials, for example, an oxide film and a nitride film, has been introduced.

For the SAC process, CF and CHF-based gases are used, and an etch stop film and a spacer using a nitride film are required to prevent an attack on the conductive pattern below.

For example, in the case of a gate electrode, spacers of nitride layers are formed on upper and side surfaces thereof, and spacers are used in a structure in which a plurality of nitride layers are stacked as the aspect ratio increases, and due to stress generation between the nitride layers or between the nitride layer and the substrate. A buffer oxide film is used between nitride films in consideration of cracks and the like and reliability of the device. A representative example thereof is a spacer having a triple structure of a nitride film / oxide film / nitride film. In order to prevent cell contact attack, an etch stop layer based on a nitride film is further formed on the triple structure.

Hereinafter, a cell contact process using the aforementioned SAC etching process will be described, and FIGS. 1A to 1C are cross-sectional views illustrating a cell contact forming process according to the prior art.

First, as shown in FIG. 1A, a gate hard mask 104 / gate conduction is formed on a semiconductor substrate 100 on which various elements for forming a semiconductor device, for example, a field insulating film 101 and a well (not shown), are formed. Gate electrode patterns G1 to G5 in which the film 103 / gate insulating film 102 are stacked are formed.

The gate insulating film 102 uses a conventional oxide-based material film such as a silicon oxide film, and the gate conductive film 103 typically uses polysilicon, W, WN, WSi _x, or a combination thereof.

The gate hard mask 104 is used to protect the gate conductive layer 103 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the etching speed is significantly different from that of the interlayer insulating layer. Use For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and an oxide-based material is used when a polymer-based low dielectric film is used as the interlayer insulating film. do.

An impurity diffusion region 105 such as a source / drain junction is formed in the substrate 100 between the gate electrode patterns G1 to G5.

A spacer (not shown) is formed along the profile in which the gate electrode patterns G1 to G5 are formed. An etch stop layer 106 is formed on the entire surface of the spacer to serve as an etch stop to prevent attack of the underlying structures such as the spacers and the gate electrode patterns G1 to G5 in an etching process using a subsequent SAC method. In this case, the etch stop layer 106 may be formed along the lower profile, and a nitride layer-based material layer is used as the etch stop layer 106.

Next, as shown in FIG. 1B, an oxide-based interlayer insulating film 107 is formed over the entire structure where the etch stop film 106 is formed.

When the interlayer insulating film 107 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra) -Ethyl-Ortho-Silicate (HDP) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. have.

Subsequently, a photoresist pattern 108 for forming a cell contact plug is formed on the interlayer insulating film 107. An anti-reflection film is typically used between the photoresist pattern 108 and the underlying layer, but is omitted here for the sake of simplicity.

Subsequently, the interlayer insulating film 107 and the etch stop film 106 are etched using the photoresist pattern 108 as an etch mask to expose the impurity diffusion region 105 between the adjacent gate electrode patterns G1 to G5. The hole 109 is formed.

The above-described contact hole 119 forming process is generally an SAC etching process using an etching selectivity of the interlayer insulating layer 107 and the gate hard mask 104. The photoresist pattern 108 is formed as an etching mask. ) And a contact for exposing the substrate 100 (specifically, the impurity diffusion region 105) by removing the etch stop layer 106 and the spacer. The hole 109 is divided into an opening process and a cleaning process for extending the opening of the contact hole 109 and removing an etching residue.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

On the other hand, while the vertical height of the gate electrode patterns G1 to G5 increases with high integration, the width of the gate electrode pattern and the spacing therebetween decrease with decreasing pitch. Therefore, in the SAC etching process, the etching target is increased as shown in 'a', so that excessive loss of the gate hard mask 104 occurs as shown in 'b' in order to proceed with sufficient excessive etching, resulting in SAC fail. In addition, the possibility of contact not open is increased to proceed with excessive etching without a margin.

In the case of SAC etching process for storage node contact, the problem tends to increase even in the case of line type contact hole pattern due to the decrease of margin.

Subsequently, the photoresist pattern 108 is removed through an ashing process. When an organic material is used as the antireflection film, the photoresist pattern 108 is removed as in the ashing process.

Subsequently, as shown in FIG. 1C, a plug forming conductive material is deposited on the entire surface where the contact hole 109 is formed to sufficiently fill the contact hole 109, and then planarize to a target to which the gate hard mask 104 is exposed. The process may be performed to form a plug 110 electrically connected to the impurity diffusion region 105 through the contact hole 109 and having the gate hard mask 104 flattened thereon. As the plug forming conductive material, polysilicon is mainly used.

The planarization process for plug 110 isolation mainly uses chemical mechanical polishing (hereinafter referred to as CMP).

Meanwhile, in order to solve the above-mentioned problems, the CMP process may be performed to reduce the target during the SAC etching process, but residues such as polysilicon remain in the stepped portion caused by the difference in the polishing selectivity during the CMP process. Is likely to cause

The present invention has been proposed to solve the above problems of the prior art, and provides a method for forming a contact plug of a semiconductor device capable of preventing a bridge phenomenon between plugs while preventing SAC failure when forming a contact hole using a SAC process. For that purpose.

In order to achieve the above object, the present invention comprises the steps of: forming a plurality of neighboring conductive patterns having a hard mask thereon on a substrate on which a conductive film is formed; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on a target to which the etch stop layer is exposed; Depositing a buffer insulating layer having a thickness sufficient to alleviate the step difference generated during the planarization process; Selectively etching the buffer insulating layer, the interlayer insulating layer, and the etch stop layer to form a contact hole exposing the conductive layer; Forming a conductive film to fill the contact hole; And forming a plug in which the hard mask is exposed to form a planarization process and forming an isolated plug in the contact hole.

The present invention forms an etch stop layer and an interlayer dielectric layer after forming a conductive pattern (eg, a gate electrode pattern, a bit line, etc.), and reduces the etch target by performing a planarization process with a target at which the top of the etch stop layer or the spacer is exposed. After depositing a buffer insulating film on the entire surface to reduce the step difference between the patterns generated in the polishing process to reduce the etching target, the SAC etching process is performed to form a plug.

Therefore, SAC failing such as a contact sickle opening phenomenon can be prevented, and generation of a bridge between plugs due to a planarization process performed to reduce an etching target can be suppressed.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.                     

2A to 2E are cross-sectional views illustrating a cell contact plug forming process according to an exemplary embodiment of the present invention, with reference to this, a plug forming process according to an exemplary embodiment of the present invention will be described.

First, as shown in FIG. 2A, a gate hard mask 204 / gate conductive film 203 / gate insulating film is formed on a semiconductor substrate 200 on which various elements for forming a semiconductor device such as an isolation layer 201 and a well are formed. The gate electrode patterns G1 to G5 on which 202 are stacked are formed.

The gate insulating film 202 uses a conventional oxide-based material film such as a silicon oxide film, and the gate conductive film 203 typically uses polysilicon, W, WN, WSi _x, or a combination thereof.

The gate hard mask 204 is used to protect the gate conductive layer 203 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for the subsequent contact formation, and the material having a significantly different etching speed from the interlayer insulating layer. Use For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and an oxide-based material is used when a polymer-based low dielectric film is used as the interlayer insulating film. do.

An impurity diffusion region 205 such as a source / drain junction is formed in the substrate 200 between the gate electrode patterns G1 to G5.

A spacer S having, for example, a single or plural structure of the nitride film or a nitride film / oxide film / nitride film structure is formed along the profile in which the gate electrode patterns G1 to G5 are formed.

Subsequently, an etch stop layer 206 is formed on the entire surface where the spacer is formed in order to prevent attack of underlying structures such as gate electrode patterns G1 to G5 in an etching process using a subsequent SAC method. In this case, the etch stop film 206 is preferably formed along the profile of the lower structure, and a nitride film-based material film is used.

Subsequently, an oxide-based interlayer insulating film 207 is formed on the entire structure where the etch stop film 206 is formed.

When the interlayer insulating film 207 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. In addition to the oxide film, an inorganic or organic low dielectric constant is used. Membrane can be used.

Subsequently, as shown in FIG. 2B, the interlayer insulating layer 207 is partially planarized to expose the etch stop layer 106 at a portion where a subsequent SAC etching process is to be performed to reduce the etching target during the SAC etching process. In the case of planarization, a conventional CMP process is applied.

Due to the characteristics of the polishing CMP process, a step occurs due to the difference in the density of the pattern and the polishing selectivity between the materials. Generally, the polishing of the interlayer insulating film 207 around the gate electrode patterns G1 to G5 is excessive. Occurs.

Meanwhile, a planar etching process may be used in addition to CMP during planarization.                     

Due to such a step, a buffer insulating layer 208 for removing the step is deposited on the flattened front surface in order to suppress the bridge between plugs due to the residues in the subsequent plug process. As the buffer insulating film 208, an oxide film series having a low dielectric constant is preferably used.

The buffer insulating film 206 is preferably formed to a minimum thickness that can eliminate the step.

Subsequently, as shown in FIG. 2C, a mask pattern 209 for forming a cell contact plug is formed on the buffer insulating layer 208.

Here, the mask pattern 209 may be a conventional photoresist pattern, may include a photoresist pattern and a hard mask, or may refer to only a hard mask. As the hard mask material, an insulating material based on Al ₂ O ₃ or a nitride film, or a conductive material such as tungsten or polysilicon may be used.

That is, this indicates that a sacrificial hard mask such as tungsten, polysilicon, or nitride may be used to secure the etching resistance of the photoresist and prevent the pattern deformation due to the limitation of the resolution in the photolithography process.

On the other hand, when forming a photoresist pattern, an anti-reflection film can be used between the lower part and the lower part. The anti-reflection film is used between the photoresist pattern and the lower structure for the purpose of improving the adhesion between the lower structure and the photoresist to prevent unwanted reflections due to high reflectivity of the lower part during exposure for pattern formation and to prevent unwanted reflections. . In this case, the anti-reflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on the process.

Looking at the photoresist pattern forming process in more detail, a photoresist for an F ₂ exposure source or an ArF exposure source on an underlying structure such as a buffer insulating film 208, an antireflection film, or a hard mask material film, for example, an ArF exposure source. The photoresist, COMA or acrylate, is applied to an appropriate thickness by spin coating or the like, and then a predetermined reticle (not shown) is used to define the width of the F ₂ exposure source or ArF exposure source and the contact plug. A photoresist as a cell contact open mask is selectively exposed by selectively exposing a predetermined portion of the photoresist, leaving portions exposed or not exposed by the exposure process through a developing process, and then removing etch residues through a post-cleaning process or the like. Form a pattern.

Here, the photoresist pattern may be in the form of a hole type, bar type or tee type.

Subsequently, as shown in FIG. 2D, the etch stop between the adjacent gate electrode patterns G1 to G5 is etched by etching the buffer insulating film 208 and the interlayer insulating film 207, which are layers to be etched, using the mask pattern 210 as an etching mask. The contact hole 210 is formed by performing a SAC etching process in which the etching stops at the film 206.

At this time, the recipe of the conventional SAC etching process is applied, such as fluorine-based plasma, such as C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C ₅ F ₁₀ CxFy (x, y is 1 to 10) as the stock angle, and a gas for generating a polymer in the SAC process, that is, a gas such as CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ is added thereto. As a carrier gas, an inert gas such as He, Ne, Ar, or Xe is used.

At this time, the etch stop layer 206 remains in a spacer shape on the side surfaces of the gate electrode patterns G1 to G5 on which the contact holes 210 are formed.

In a subsequent process, a conventional photoresist strip process is performed to remove the mask pattern 210 if it contains a photoresist pattern.

If the mask pattern 210 includes only the sacrificial hard mask, the hard mask removing process may be omitted.

Subsequently, the contact hole exposing the substrate 200 (specifically, the impurity diffusion region 205) by removing the etch stop layer 206 from the bottom of the contact hole 210 by performing a full surface etching or a wet cleaning process. 210) Open process.

Subsequently, wet cleaning is performed using a cleaning solution such as BOE to secure the CD on the bottom of the contact hole and to remove the etching by-products remaining after the SAC and the front surface etching. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrochloric acid having a ratio of 50: 1 to 500: 1.

Subsequently, as shown in FIG. 2E, the conductive film for plug formation is deposited on the entire surface of the substrate 200 on which the contact hole 210 is formed to sufficiently fill the contact hole 210.

Here, the most commonly used material for forming a conductive film for plug formation is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and metal such as tungsten may be used instead of polysilicon.

Subsequently, a CMP or an entire surface etching process may be performed to form a cell contact plug 211 electrically connected to the substrate 200 through the contact hole 210 and planarized and isolated from the gate hard mask 204.

Meanwhile, in the above-described embodiment, the cell contact plug forming process is taken as an example, but it may be applied to a bit line contact plug or a storage node contact plug forming process.

Therefore, in the storage node contact plug forming process, the lower impurity diffusion region 205 may be replaced by a cell contact plug or a contact pad, and the gate electrode pattern may be replaced by a bit line.

Accordingly, the lower stepped portion is alleviated to some extent by the buffer insulating film 208, so that the occurrence of bridges between the plugs 211 due to the residue of the plug-forming conductive film at the time of plug 211 isolation can be suppressed.

According to the present invention as described above, after forming a conductive pattern such as a gate electrode pattern or a bit line, an interlayer insulating film is formed, a planarization process is performed on a target to which the top of the etch stop film or the spacer is exposed, and then the buffer insulating film is formed on the entire surface. By depositing a thin film, the level | step difference which arose at the time of planarization is alleviated to some extent.

Therefore, by reducing the SAC etching target and performing the SAC etching process, it is possible to prevent SAC failing such as contact sickle opening phenomenon and to suppress the plug-to-plug bridge phenomenon caused by residual plug material in the step generated during planarization. It was found through the examples.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent SAC failing during the contact forming process, can suppress the occurrence of bridges between plugs, and improve the yield of semiconductor devices.

Claims (10)

Forming a plurality of neighboring conductive patterns having a hard mask on the substrate on which the conductive film is formed; Forming spacers on both sidewalls of the conductive pattern; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on a target to which the etch stop layer is exposed; Forming a buffer insulating film on the entire surface of the substrate to fill a step generated during the planarization process to provide a flat surface; Selectively etching the buffer insulating layer, the interlayer insulating layer, and the etch stop layer to form a contact hole exposing the conductive layer; Forming a conductive film for plug to fill the contact hole; And Performing a planarization process on the target to which the hard mask is exposed to form an isolated plug embedded in the contact hole Contact plug forming method of a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And said interlayer insulating film and said buffer insulating film comprise an oxide film. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 1 or 2, A method of forming a contact plug of a semiconductor device, wherein the planarization process uses an entire surface etching process or a chemical mechanical polishing process. Claim 4 was abandoned when the registration fee was paid. The method according to claim 1 or 2, Forming the contact hole, Forming a mask pattern for forming a contact hole on the buffer insulating layer having a flat surface; Forming a contact hole exposing the etch stop layer by sequentially etching the buffer insulating layer and the interlayer insulating layer using the mask pattern as an etch mask; And removing the etch stop layer under the contact hole to expose the conductive layer. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein In the forming of the contact hole, CxFy (x, y is 1 to 10) as a stock corner gas, and a gas for generating a polymer, ie, one of CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ , is added thereto. When the inert gas of any one of He, Ne, Ar or Xe is used as a carrier gas. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, In the forming of the mask pattern, a photolithography process using an exposure source of ArF or F ₂ is used. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The mask pattern, A method of forming a contact plug of a semiconductor device, comprising: a photoresist pattern, a photoresist pattern / sacrificial hardmask, or a sacrificial hardmask. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The sacrificial hard mask may include any one of a nitride film, a tungsten film, and a polysilicon film. Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 1 or 2, And the plug conductive film comprises a polysilicon film. Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 1 or 2, The plurality of conductive patterns may include at least one of a gate electrode pattern, a bit line, and a metal wiring.

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