KR20050116487A - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device capable of preventing SAC fail due to the attack of the buffer oxide film in the SAC etching process to be aligned with the conductive pattern having a spacer of the spacer nitride film / buffer oxide film / sealing nitride film structure To this end, the present invention comprises the steps of forming a plurality of neighboring conductive patterns having a hard mask on the substrate on which the conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film having a planarization thereon on the entire surface where the spacer is formed; Selectively etching the interlayer insulating film to form a contact hole exposing the spacer; Forming an anti-attack layer along the profile in which the contact hole is formed; And etching the attack prevention layer and the spacer to expose the conductive layer on the bottom surface of the contact hole.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing SAC fail when forming a contact hole using a Self Align Contact (hereinafter referred to as SAC) process.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In forming such a contact plug, a landing plug contact is known as having a larger area at the upper part than the lower part contacted to increase the contact area with a minimum area at the lower part and to increase the process margin for subsequent processes at the upper part. ) Technology has been introduced and commonly used.

In addition, in order to form such a contact, it is difficult to etch between structures having a high aspect ratio. In this case, an SAC process for obtaining an etching profile using an etching selectivity between two materials, for example, an oxide film and a nitride film, has been introduced.

For the SAC process, CF and CHF-based gases are used, and an etch stop film and a spacer using a nitride film are required to prevent an attack on the conductive pattern below.

For example, in the case of a gate electrode, spacers of nitride layers are formed on upper and side surfaces thereof, and spacers are used in a structure in which a plurality of nitride layers are stacked as the aspect ratio increases, and due to stress generation between the nitride layers or between the nitride layer and the substrate. A buffer oxide film is used between nitride films in consideration of cracks and the like and reliability of the device. A representative example thereof is a spacer having a triple structure of a nitride film / oxide film / nitride film. In order to prevent cell contact attack, an etch stop layer based on a nitride film is further formed on the triple structure.

Hereinafter, a cell contact process using the aforementioned SAC etching process will be described, and FIGS. 1A to 1I are cross-sectional views illustrating a cell contact plug forming process according to the related art.

First, as shown in FIG. 1A, a gate hard mask 104 / tungsten film is formed on a semiconductor substrate 100 on which various elements for forming a semiconductor device, for example, a field insulating film 101 and a well (not shown), are formed. A gate electrode pattern having a structure in which (103) / polysilicon film 102 / gate insulating film (not shown) is stacked is formed.

The gate insulating film uses a conventional oxide film-based material film such as a silicon oxide film. In this example, a laminated structure of tungsten film 103 / polysilicon film 102 is used as the gate conductive film. In addition, polysilicon, tungsten film, tungsten nitride, and tungsten silicide are used. Or the like or a combination thereof.

The gate hard mask 104 is to protect the gate conductive layer from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation. use. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region such as a source / drain junction is formed in the substrate 100 between the gate electrode patterns.

Subsequently, in the etching process for forming the gate electrode pattern illustrated in FIG. 1B, the side of the gate electrode is selectively oxidized to form a selective oxide layer (not shown) to recover the deteriorated characteristics, and then a spacer is formed along the profile in which the selective oxide layer is formed. Form 105.

Next, a TEOS (Tetra ethyl Ortho Silicate) film 106 is formed along the profile in which the spacer 105 is formed.

FIG. 2 illustrates a process cross-section in which a spacer 105 is formed along a profile in which a gate electrode pattern is formed.

Referring to FIG. 2, a gate electrode pattern in which a polysilicon film 102, a tungsten film 103, and a hard mask 104 are stacked is formed, and a selective oxide film (SO) is formed on a sidewall thereof by a selective oxidation process. And a spacer 105 having a nitride film (N) / oxide film (O) / nitride film (N) structure comprising a sealing nitride film 105a, a buffer oxide film 105b, and a spacer nitride film 105c along the profile thereof. Formed.

Subsequently, as shown in FIG. 1C, a deep-out process using a COR oxide removal (COR) mask is performed to remove the TEOS film 106 in the cell region.

Subsequently, as shown in FIG. 1D, the COR mask is removed and etching is performed to prevent attack of the underlying structures such as the spacer 105 and the gate electrode pattern in an etching process using a subsequent SAC method on the entire surface where the spacer 105 is formed. An etch stop layer 107 serving as a stop is formed. In this case, the etch stop film 107 is preferably formed along the lower profile, and a nitride film-based material film is used as the etch stop film 107.

Next, as shown in FIG. 1E, an oxide-based interlayer insulating film 108 is formed over the entire structure where the etch stop film 107 is formed.

When the interlayer insulating film 108 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra) -Ethyl-Ortho-Silicate (HDP) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. have.

Subsequently, as shown in FIG. 1F, the interlayer insulating film 108 is planarized through a planarization process such as chemical mechanical polishing (hereinafter referred to as CMP) or full surface etching. This is to prevent pattern defects due to uneven surfaces in subsequent photolithography processes.

Subsequently, as shown in FIG. 1G, a photoresist pattern 109 for forming a cell contact plug is formed on the interlayer insulating film 108. An anti-reflection film is usually used between the photoresist pattern 109 and the underlying layer, but is omitted here for the sake of simplicity.

Subsequently, as shown in FIG. 1H, the interlayer insulating film 108, the etch stop film 107 and the spacer 105 are etched using the photoresist pattern 109 as an etch mask to form a substrate between adjacent gate electrode patterns ( A contact hole 110 exposing 100 is formed.

The above-described contact hole 110 forming process is generally an SAC etching process using an etch selectivity of the interlayer insulating film 108 and the gate hard mask 104. The photoresist pattern 109 is used as an etching mask. ) And a contact hole for exposing the substrate 100 (specifically, impurity diffusion region) by removing the etch stop layer 107 and the spacer 106 by etching the SAC etch process to stop the etch stop in the etch stop layer 107. (109) It is divided into an open process and a cleaning process for removing the etching residue by expanding the opening of the contact hole 109.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

On the other hand, since the nitride film is vulnerable to stress, the spacer 105 is formed to have a spacer nitride film 105c / buffer oxide film 105b / sealing nitride film 105a structure. In such a stacked structure, when micro cracks are generated in the spacer nitride film 105c due to excessive etching of the spacer nitride film 105c, the attack is performed along the buffer oxide film 105b by the wet chemical injected along the micro cracks. Occurs.

This attack eventually causes a bridge between the subsequent cell contact plug and the gate conductive film.

Reference numeral 111 denotes a fragile portion in which the spacer 105 is etched during the etching and thus the buffer oxide layer 105b is lost.

Subsequently, the photoresist pattern 109 is removed through an ashing process. When an organic material is used as the antireflection film, the photoresist pattern 109 is removed as in the ashing process.

Subsequently, as shown in FIG. 1I, a plug forming conductive material is deposited on the entire surface where the contact hole 110 is formed to sufficiently fill the contact hole 110, and then planarize to a target to which the gate hard mask 104 is exposed. The process may be performed to electrically connect the impurity diffusion region of the substrate 100 through the contact hole 110 to form the gate hard mask 104 or the interlayer insulating layer 108 and the flattened plug 112. As the plug forming conductive material, polysilicon is mainly used.

In the planarization for plug 110 isolation, a CMP process is mainly used.

Even in a portion where the buffer oxide film 105b is attacked, a bridge between the gate conductive film and the plug is induced as shown by reference numeral 113 to generate an electrical short circuit.

The present invention has been proposed to solve the above problems of the prior art, SAC fail due to the attack of the buffer oxide film in the SAC etching process to be aligned with the conductive pattern having a spacer of the spacer nitride film / buffer oxide film / sealing nitride film structure It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the damage.

In order to achieve the above object, the present invention comprises the steps of: forming a plurality of neighboring conductive patterns having a hard mask thereon on a substrate on which a conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film having a planarization thereon on the entire surface where the spacer is formed; Selectively etching the interlayer insulating film to form a contact hole exposing the spacer; Forming an anti-attack layer along the profile in which the contact hole is formed; And etching the attack prevention layer and the spacer to expose the conductive layer on the bottom surface of the contact hole.

In the present invention, after forming a conductive pattern (eg, a gate electrode pattern, a bit line, etc.) having a spacer having a nitride film, an oxide film, or a nitride film structure, an SAC etching process is performed without forming an etch stop film and exposing the spacers and exposing the spacers. By forming an attack prevention film along the profile of the contact hole formed before the contact opening process, it is possible to prevent the attack by the chemical generated along the oxide film forming the spacer during the contact opening process using the attack stop film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3J are cross-sectional views illustrating a cell contact plug forming process according to an exemplary embodiment of the present invention. With reference to this, a plug forming process according to an exemplary embodiment of the present invention will be described.

First, as shown in FIG. 3A, a gate hard mask 304 / tungsten film is formed on a semiconductor substrate 300 on which various elements for forming a semiconductor device, for example, a field insulating film 301 and a well (not shown), are formed. A gate electrode pattern having a structure in which 303 / polysilicon film 302 / gate insulating film (not shown) is stacked is formed.

The gate insulating film uses a conventional oxide film-based material film such as a silicon oxide film. In this example, a laminated structure of tungsten film 103 / polysilicon film 102 is used as the gate conductive film. In addition, polysilicon, tungsten film, tungsten nitride, and tungsten silicide are used. Or the like or a combination thereof.

The gate hard mask 304 protects the gate conductive layer from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for the subsequent contact formation. use. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region such as a source / drain junction is formed in the substrate 300 between the gate electrode patterns.

Subsequently, in the etching process for forming the gate electrode pattern shown in FIG. 3B, the side of the gate electrode is selectively oxidized to form a selective oxide layer (not shown) to recover the deteriorated characteristics, and then a spacer is formed along the profile in which the selective oxide layer is formed. 305 is formed.

Next, the TEOS film 306 is formed along the profile in which the spacer 305 is formed.

4 is a view illustrating a process cross section in which a spacer 305 is formed along a profile in which a gate electrode pattern is formed.

Referring to FIG. 4, a gate electrode pattern in which a polysilicon film 302, a tungsten film 303, and a hard mask 304 are stacked is formed, and a selective oxide film SO is formed on a sidewall thereof by a selective oxidation process. A spacer 305 having a nitride film (N) / oxide film (O) / nitride film (N) structure including a sealing nitride film 305a, a buffer oxide film 305b, and a spacer nitride film 305c is formed along the profile. .

Here, it is preferable that the selective oxide film SO has a thickness of 25 GPa, the sealing nitride film 305a is 70 GPa, the buffer oxide film 305b is 80 GPa, and the spacer nitride film 305c is about 90 GPa.

Subsequently, as shown in FIG. 3C, a dip-out process using a COR mask is performed to remove the TEOS film 306 in the cell region.

Subsequently, as shown in FIG. 3D, after removing the COR mask, an oxide-based interlayer insulating film 307 is formed on the entire structure where the spacer 305 is formed.

When the interlayer insulating film 307 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. In addition to the oxide film, an inorganic or organic low dielectric constant is used. Membrane can be used.

Subsequently, as shown in FIG. 3E, the interlayer insulating film 307 is planarized through a planarization process such as CMP or full surface etching. This is to prevent pattern defects due to uneven surfaces in subsequent photolithography processes.

Subsequently, as illustrated in FIG. 3F, a mask pattern 308 for forming a cell contact plug is formed on the interlayer insulating layer 307.

Here, the mask pattern 308 may be a conventional photoresist pattern, may include a photoresist pattern and a hard mask, or may refer to only a hard mask. As the hard mask material, an insulating material based on Al ₂ O ₃ or a nitride film, or a conductive material such as tungsten or polysilicon may be used.

That is, this indicates that a sacrificial hard mask such as tungsten, polysilicon, or nitride may be used to secure the etching resistance of the photoresist and prevent the pattern deformation due to the limitation of the resolution in the photolithography process.

On the other hand, when forming a photoresist pattern, an anti-reflection film can be used between the lower part and the lower part. The anti-reflection film is used between the photoresist pattern and the lower structure for the purpose of improving the adhesion between the lower structure and the photoresist to prevent unwanted reflections due to high reflectivity of the lower part during exposure for pattern formation and to prevent unwanted reflections. . In this case, the antireflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on a process.

Looking at the photoresist pattern forming process in more detail, a photoresist for an F ₂ exposure source or an ArF exposure source on an underlying structure such as an interlayer insulating film 307, an antireflection film, or a hard mask material film, for example, an ArF exposure source. The photoresist, COMA or acrylate, is applied to an appropriate thickness by spin coating or the like, and then a predetermined reticle (not shown) is used to define the width of the F ₂ exposure source or ArF exposure source and the contact plug. A photoresist as a cell contact open mask is selectively exposed by selectively exposing a predetermined portion of the photoresist, leaving portions exposed or not exposed by the exposure process through a developing process, and then removing etch residues through a post-cleaning process or the like. Form a pattern.

Here, the photoresist pattern may be in the form of a hole type, bar type or tee type.

Subsequently, as shown in FIG. 3G, the interlayer insulating layer 307, which is a layer to be etched, is etched using the mask pattern 308 as an etch mask to perform an SAC etching process in which the etching is stopped at the spacers 305 between neighboring gate electrode patterns. To form a contact hole 309.

At this time, the recipe of the conventional SAC etching process is applied, such as fluorine-based plasma, such as C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C ₅ F ₁₀ CxFy (x, y is 1 to 10) as a stock corner gas, and a gas for generating a polymer in the SAC process, that is, CaHbFc (a, b, such as CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ ). c adds 1-10) gas, and uses inert gas, such as He, Ne, Ar, or Xe, as a carrier gas at this time.

Next, the mask pattern 308 is removed.

The process of forming the contact hole 309 for forming the contact plug is generally a SAC etching process using an etching selectivity of the interlayer insulating film 308 and the gate hard mask 304. The interlayer insulating film is formed by using the mask pattern 308 as an etching mask. 308 is etched to stop the etch stop in the etch stop film or the like, and the contact hole 309 to expose the substrate 300 (specifically, impurity diffusion region) by removing the etch stop film and the spacer 305 is opened. The process and the opening of the contact hole 309 is expanded and divided into a cleaning process for removing the etching residue.

However, in the present invention, the etch stop layer is not formed before the SAC etching process in order to prevent the buffer oxide layer 305b from being lost due to the micro cracks generated in the spacer nitride layer 305c forming the spacer in the SAC etching or continuous contact opening process. Instead, the attack prevention layer 310 is formed along the profile in which the contact holes are formed after the SAC etching and mask pattern 108 are removed.

Therefore, due to the attack prevention film 310, it is possible to prevent the wet chemical from penetrating through the micro crack due to the edge strain of the spacer nitride film 305c in the contact opening and cleaning process.

That is, as shown in FIG. 3H, the attack prevention layer 310 is formed along the profile in which the contact hole 309 is formed.

The attack prevention film 310 is preferably formed to a thickness of 1 kPa to 1000 kPa, and a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film is used.

Meanwhile, when the mask pattern 308 includes the photoresist pattern, only the photoresist pattern and the anti-reflection film may be removed and the hard mask may be left. The remaining hard mask can then be removed in the planarization process for subsequent plug isolation. However, it may be desirable to remove the hard mask because the hard mask may interfere with the SEM imaging for CD measurement.

When the antireflection film is used as an organic series, it can be removed like the photoresist pattern in the ashing process for removing the photoresist pattern.

Subsequently, as shown in FIG. 3I, an anti-attack layer 310 and a spacer 305 are removed from the bottom of the contact hole 309 by performing an entire surface etching or wet cleaning process to remove the substrate 300, specifically, an impurity diffusion region. The contact opening process is performed to expose.

Subsequently, wet cleaning is performed using a cleaning solution such as BOE to secure the CD on the bottom of the contact hole and to remove the etching by-products remaining after the SAC and the front surface etching. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrofluoric acid having a ratio of 50: 1 to 500: 1 in water and hydrofluoric acid. In addition, it is also possible to use a chemical mixture of the fruit water (H ₂ O ₂ ) and pure water (H ₂ O) in hydrofluoric acid.

At this time, it can be seen that the attack is prevented by the attack prevention layer 310 at the portion of '311' which was relatively vulnerable to the attack of the wet chemical.

Here, the most commonly used material for forming a conductive film for plug formation is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and metal such as tungsten may be used instead of polysilicon. When depositing using polysilicon, the deposition temperature is preferably about 450 ° C to 700 ° C.

Meanwhile, in the above-described embodiment, the cell contact plug forming process is taken as an example, but it may be applied to a bit line contact plug or a storage node contact plug forming process.

In addition, the present invention can be applied to any contact hole forming process aligned to the side surface of the conductive pattern having a spacer having a nitride film / oxide film / nitride film on its side surface.

Therefore, in the storage node contact plug forming process, the lower impurity diffusion region may be replaced by a cell contact plug or a contact pad, and the gate electrode pattern may be replaced by a bit line.

According to the present invention made as described above, in performing an etching process for forming a contact plug which is aligned with a side surface of a conductive pattern such as a gate electrode pattern or a bit line having a spacer having an N / O / N structure on its side, By eliminating the etch stop layer formed on the spacer before the etch process and stopping the etch process on the spacer, the anti-tack film is formed along the etched profile, that is, the contact hole formed profile, and the contact open process is performed. It was found through the examples that the loss of the buffer oxide film due to the wet chemical penetrated through the micro crack due to the strain can be prevented.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent SAC failing during the contact forming process, and can suppress the occurrence of bridges between the plug and the conductive pattern, thereby improving the yield of the semiconductor device.

1A to 1I are cross-sectional views illustrating a cell contact plug forming process according to the prior art.

FIG. 2 is a view illustrating a process cross section in which a spacer is formed along a profile in which a gate electrode pattern is formed; FIG.

3A to 3J are cross-sectional views illustrating a cell contact plug forming process according to an embodiment of the present invention.

4 is a view illustrating a process cross section in which a spacer 305 is formed along a profile in which a gate electrode pattern is formed;

Explanation of symbols on the main parts of the drawings

300: substrate 301: device isolation film

302: gate insulating film 303: tungsten film

304: polysilicon film 305: gate hard mask

307: interlayer insulating film 309: contact hole

310: Attack prevention film 311: Chemical attack weak part

Claims (11)

Forming a plurality of neighboring conductive patterns having a hard mask on the substrate on which the conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film having a planarization thereon on the entire surface where the spacer is formed; Selectively etching the interlayer insulating film to form a contact hole exposing the spacer; Forming an anti-attack layer along the profile in which the contact hole is formed; And Etching the attack prevention layer and the spacer to expose the conductive layer on the bottom of the contact hole; Semiconductor device manufacturing method comprising a. The method of claim 1, The attack prevention film is a semiconductor device manufacturing method comprising a nitride film. The method according to claim 1 or 2, The attack prevention film is formed to a thickness of 1 ~ 1000Å semiconductor device manufacturing method characterized in that. The method according to claim 1 or 2, Forming the contact hole, Forming a mask pattern for forming a contact hole on the entire surface including the interlayer insulating layer; And forming a contact hole exposing the spacer by etching the interlayer insulating layer using the mask pattern as an etch mask. The method of claim 4, wherein In the forming of the contact hole, CxFy (x, y is 1 to 10) as a stock corner gas, and a gas for generating a polymer, that is, CaHbFc (a, b, c is 1 to 10) is added thereto, and He, A method for forming a contact plug in a semiconductor device, comprising using an inert gas of any one of Ne, Ar, or Xe. The method of claim 5, In the forming of the mask pattern, a photolithography process using an exposure source of ArF or F ₂ is used. The method of claim 4, wherein The mask pattern is, A method of forming a contact plug of a semiconductor device, comprising: a photoresist pattern, a photoresist pattern / sacrificial hardmask, or a sacrificial hardmask. The method of claim 7, wherein The sacrificial hard mask may include any one of a nitride film, a tungsten film, and a polysilicon film. The method according to claim 1 or 2, After exposing the conductive film, Cleaning the bottom of the contact hole; Depositing a conductive film for plug formation on the entire surface where the contact hole is formed; And removing a portion of the conductive film to form an isolated plug by a planarization process. The method of claim 9, The plug forming conductive film may include a polysilicon film. The method according to claim 1 or 2, The plurality of conductive patterns may include any one of a gate electrode pattern, a bit line, and a metal wiring.