KR20050116493A - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can minimize the loss of the conductive film in the open portion when removing the hard mask after the open portion forming process to expose the conductive film containing silicon using a hard mask containing silicon. To this end, the present invention comprises the steps of forming a conductive film comprising silicon on the substrate; Forming an insulating etching layer on the conductive film; Forming a hard mask including the silicon on the etched layer and defining a region to be formed with an open part; Forming an open portion to expose a portion of the conductive layer by etching the etched layer using the hard mask as an etch mask; And removing the hard mask while performing a front-side etching using HBr plasma in a high density plasma apparatus to prevent attack on the conductive layer.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of removing a hard mask without attacking at the bottom when forming a contact hole using a Self Align Contact (SAC) process. .

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In forming such a contact plug, a landing plug contact is known as having a larger area at the upper part than the lower part contacted to increase the contact area with a minimum area at the lower part and to increase the process margin for subsequent processes at the upper part. ) Technology has been introduced and commonly used.

In addition, in order to form such a contact, it is difficult to etch between structures having a high aspect ratio. In this case, an SAC process for obtaining an etching profile using an etching selectivity between two materials, for example, an oxide film and a nitride film, has been introduced.

For the SAC process, CF and CHF-based gases are used, and an etch stop film and a spacer using a nitride film are required to prevent an attack on the conductive pattern below.

For example, in the case of a gate electrode, spacers of nitride layers are formed on upper and side surfaces thereof, and spacers are used in a structure in which a plurality of nitride layers are stacked as the aspect ratio increases, and due to stress generation between the nitride layers or between the nitride layer and the substrate. A buffer oxide film is used between nitride films in consideration of cracks and the like and reliability of the device. A representative example thereof is a spacer having a triple structure of a nitride film / oxide film / nitride film. In order to prevent cell contact attack, an etch stop layer based on a nitride film is further formed on the triple structure.

Hereinafter, a storage node contact hole process using the aforementioned SAC etching process will be described. FIGS. 1A to 1D are cross-sectional views illustrating a storage node contact hole forming process according to the prior art.

First, as shown in FIG. 1A, a first interlayer insulating film 101 is formed on a semiconductor substrate 100 on which various elements for forming semiconductor devices such as wells and transistors are formed.

When the first interlayer insulating film 101 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra-Ethyl-Ortho-Silicate) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. It is available.

For reference, the gate electrode pattern is omitted here.

Subsequently, the first interlayer insulating layer 101 is selectively etched to form a contact hole exposing an impurity diffusion region (not shown) of the substrate 100. At this time, the SAC etching process is applied.

Subsequently, a conductive film such as polysilicon is deposited to fill the contact hole, and then a planarization process is performed on the target to which the gate hard mask is exposed to form a plurality of isolated cell contact plugs 102.

Subsequently, a second interlayer insulating film 103 is formed on the entire surface where the cell contact plug 102 is formed. The second interlayer insulating film 103 uses an oxide film-based material film or a low dielectric constant film that is substantially the same as the first interlayer insulating film 102.

Subsequently, although not shown in the drawing, the second interlayer insulating film 103 is selectively etched to expose a portion of the cell contact plug 102 to define a bit line formation region, and then similar to the process of forming the cell contact plug 102. The process forms a bitline contact plug (not shown). Subsequently, a bit line B / L electrically connected to the bit line contact plug is formed.

The bit line has a structure in which the bit line hard mask 105 / bit line conductive film 104 is stacked. The bit line conductive film 104 typically uses polysilicon, W, WN, WSi _x alone or in combination thereof.

The bit line hard mask 105 is to protect the bit line conductive layer 104 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for forming the contact hole for the subsequent storage node, the interlayer insulating layer and the etching rate Use materials that differ significantly. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

Subsequently, an etch stop layer is formed along the profile in which the bit lines B / L are formed to serve as an etch stop to prevent attack of an underlying structure such as the bit lines B / L in an etching process using a subsequent SAC method. It is omitted here for the sake of simplicity of the drawings.

In this case, the etch stop film is preferably formed along the lower profile, and a nitride film-based material film is used as the etch stop film.

Next, an oxide-based third interlayer insulating film 106 is formed on the entire structure where the bit lines B / L are formed. The third interlayer insulating film 106 is also used as a material similar to the first and second interlayer insulating films 101 and 103.

Subsequently, a hard mask polysilicon film 107a is formed on the third interlayer insulating film 106. Here, the polysilicon film 107a for the hard mask is a material film substantially the same as the cell contact plug 102 below, and a polysilicon film is mainly used.

Subsequently, a photoresist pattern 108 for forming a contact hole for a storage node is formed on the polymask 107a for the hard mask. An anti-reflection film is generally used between the photoresist pattern 108 and the polysilicon film 107a for hard masks for the purpose of preventing diffuse reflection and increasing adhesion, but the description is omitted here for the sake of simplicity.

Subsequently, as illustrated in FIG. 1B, the hard mask 107b defining the storage node contact hole forming region to be formed by etching the hardmask polysilicon layer 107a using the photoresist pattern 108 as an etch mask. Form,

Subsequently, an ashing or photoresist strip process is performed to remove the photoresist pattern 108.

Subsequently, as shown in FIG. 1C, the third interlayer insulating film 106 and the second interlayer insulating film 103 are etched using the hard mask 107b as an etch mask, and are aligned with the side surfaces of the bit lines B / L. An open part 109 exposing the cell contact plug 102 to which the storage node contact is to be made, that is, a contact hole for the storage node is formed.

The process of forming the open portion 109 is generally a SAC etching process using an etching selectivity of the third and second interlayer insulating films 106 and 103 and the bit line hard mask 105. The SAC etching process of etching the third and second interlayer insulating films 106 and 103 with an etching mask to stop the etching from the etching stop film (not shown), and removing the etching stop film and the spacer, thereby removing the cell contact plug 102. ) Is divided into an open process of exposing the open portion 109 and a cleaning process to remove the etching residue by expanding the opening of the open portion 109.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

Subsequently, as shown in FIG. 1D, the hard mask 107b is removed through front etching. On the other hand, since the cell contact plug 102 uses a film made of the same silicon as the hard mask 107b, for example, a polysilicon film, excessive consumption of the sal contact plug 102 occurs when the hard mask 107b is removed. As shown by reference numeral 110, all of the cell contact plugs 102 may be removed and attack may occur to the substrate 100.

On the other hand, if the hard mask 107b is not removed at this stage, electron charge-up does not occur during SEM (Scanning Electron Microscopy) imaging for critical dimension (hereinafter, referred to as CD) observation. As a result, accurate FICD (Final Inspection Critical Dimension) measurement is not performed, and since plug consumption increases during subsequent plug formation, it is desirable to remove the hard mask 107b using a material containing silicon.

In the surface etching process for removing a hard mask containing silicon, such as polysilicon used in the above-described conventional storage node contact hole forming process, it is not possible to prevent the consumption of the plug mainly using polysilicon and thus damage the silicon substrate. There is a problem that the characteristics and yield of the device is reduced.

The present invention has been proposed to solve the above problems of the prior art, the loss of the conductive film in the open portion during the removal of the hard mask after the open portion forming process to expose the conductive film containing silicon using a hard mask containing silicon. An object of the present invention is to provide a method for manufacturing a semiconductor device that can minimize the.

In order to achieve the above object, the present invention comprises the steps of forming a conductive film containing silicon on the substrate; Forming an insulating etching layer on the conductive film; Forming a hard mask including the silicon on the etched layer and defining a region to be formed with an open part; Forming an open portion to expose a portion of the conductive layer by etching the etched layer using the hard mask as an etch mask; And removing the hard mask while performing a front-side etching using HBr plasma in a high density plasma apparatus to prevent attack on the conductive layer.

The present invention uses an HBr plasma under high temperature and high pressure process conditions to minimize the loss of the bottom conductive film during the hard mask removal after the open mask forming process exposing the conductive film containing silicon using a hard mask containing silicon. By inducing an aspect ratio dependent etching (ARDE) phenomenon, the hard mask is removed well, but the consumption of the conductive film under the open portion is minimized.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2D are cross-sectional views illustrating a process of forming a contact hole for a storage node according to an embodiment of the present invention, and with reference to this, a process of forming a contact hole for a storage node according to an embodiment of the present invention will be described.

Meanwhile, in the process of forming the open part of the present invention, which is described below, the storage node contact hole forming process is used as an example, but in addition, the contact hole forming process for forming the cell contact plug and the contact hole forming process for the bit line contact may be performed. It can be applied to the contact hole forming process, and can be applied to various forms such as T-type, I-type, and hole-type in the form of patterns for forming contact holes.

First, as shown in FIG. 2A, a first interlayer insulating film 201 is formed on a semiconductor substrate 200 on which various elements for forming semiconductor devices such as wells and transistors are formed.

When the first interlayer insulating film 201 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. A low dielectric constant film can be used.

For reference, the gate electrode pattern is omitted here.

Subsequently, the first interlayer insulating film 201 is selectively etched to form a contact hole exposing an impurity diffusion region (not shown) of the substrate 200. At this time, the SAC etching process is applied.

Subsequently, a conductive film such as polysilicon is deposited to fill the contact hole, and then a planarization process is performed on the target to which the gate hard mask is exposed to form a plurality of isolated cell contact plugs 202.

Although polysilicon is used as the cell contact plug 202 material, the present invention may be applied to any conductive film including silicon such as amorphous silicon, selective epitaxial growth (SEG) silicon film, and the like.

Subsequently, a second interlayer insulating film 203 is formed on the entire surface where the cell contact plug 202 is formed. The second interlayer insulating film 203 uses an oxide film-based material film or a low dielectric constant film that is substantially the same as the first interlayer insulating film 202.

Subsequently, although not shown in the drawing, the second interlayer insulating film 203 is selectively etched to expose a portion of the cell contact plug 202 to define a bit line formation region, and then similar to the process of forming the cell contact plug 202. The process forms a bitline contact plug (not shown). Subsequently, a bit line B / L electrically connected to the bit line contact plug is formed.

The bit line has a structure in which the bit line hard mask 205 / bit line conductive film 204 is stacked. The bit line conductive film 204 typically uses polysilicon, W, WN, WSi _x alone or in combination thereof.

The bit line hard mask 205 is to protect the bit line conductive layer 204 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for forming the contact hole for the subsequent storage node, the interlayer insulating layer and the etching rate Use materials that differ significantly. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

Subsequently, an etch stop layer is formed along the profile in which the bit lines B / L are formed to serve as an etch stop to prevent attack of an underlying structure such as the bit lines B / L in an etching process using a subsequent SAC method. It is omitted here for the sake of simplicity of the drawings.

In this case, the etch stop film is preferably formed along the lower profile, and a nitride film-based material film is used as the etch stop film.

Next, an oxide film-based third interlayer insulating film 206 is formed over the entire structure where the bit lines B / L are formed. The third interlayer insulating film 206 is also used as a material similar to the first and second interlayer insulating films 101 and 103.

Subsequently, a hard mask polysilicon film 207a is formed on the third interlayer insulating film 206. Here, the polysilicon film 207a for the hard mask is a material film substantially the same as the cell contact plug 202 below, and a doped polysilicon film, an undoped polysilicon film, an amorphous silicon film, and a silicon film by SEG. It includes all of them.

Subsequently, a photoresist pattern 208 for forming a storage node contact hole is formed on the hard mask polysilicon layer 207a. An anti-reflection film is generally used between the photoresist pattern 208 and the hard mask polysilicon film 207a for the purpose of preventing diffuse reflection and increasing adhesion, but the description is omitted here for the sake of simplicity.

Subsequently, as shown in FIG. 2B, the hard mask 207b defining the storage node contact hole formation region to be formed by etching the polysilicon layer 207a for the hard mask using the photoresist pattern 208 as an etch mask. Form,

Subsequently, an ashing or photoresist strip process is performed to remove the photoresist pattern 208.

Subsequently, as shown in FIG. 2C, the third interlayer insulating layer 206 and the second interlayer insulating layer 203 are etched using the hard mask 207b as an etch mask, and are aligned with the side surfaces of the bit line B / L. An open part 209 exposing the cell contact plug 202 to which the storage node contact is to be made, that is, a contact hole for the storage node is formed.

The process of forming the open portion 209 described above is generally a SAC etching process using an etching selectivity of the third and second interlayer insulating films 206 and 203 and the bit line hard mask 205. The SAC etching process of etching the third and second interlayer insulating layers 206 and 203 with an etching mask to stop the etching from the etching stop layer (not shown), and removing the etching stop layer and the spacer, thereby removing the cell contact plug 202. ) Is divided into an open process 209 exposing the open portion and an opening process of the open portion 209 and a washing process to remove the etching residue.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

Subsequently, as shown in FIG. 2D, the hard mask 207b is removed while performing a dry front surface etching using HBr plasma in the high density plasma apparatus to prevent attack of the cell contact plug 202.

At this time, HBr plasma is used in high density devices such as TCP (Transfomer Coupled Plasma), ICP (Inductive Coupled Plasma), ECR (Electron Cyclotron Resonance), or DPS (Decoupled Plasma Source) type to maintain the chamber at high temperature and pressure. In the state, the entire surface is etched to remove the hard mask 207b, and it can be seen that the attack on the cell contact plug 202 at the lower side occurs very little as shown in 'A'.

Here, when the hard mask 207b is etched and the bias power is applied at 30 W or less while maintaining the temperature of the substrate 200 in the chamber at 50 ° C. or more and the pressure at 100 mTorr or more, the aspect ratio is large. The bottom of the open portion 209 causes the etch stop of the cell contact plug 202, that is, the cell contact under the open portion 209 while completely removing the hard mask 207b on the top of the open portion 209 on the ARDE principle. The consumption of the plug 202 can be minimized.

As described above, if the hard mask 207b is not removed at this stage, electron charge-up is not performed during SEM imaging for CD observation, so accurate FICD measurement is not performed. Since the consumption of is increased, it is desirable to remove the hard mask 207b using a material containing silicon.

The recipe in the front etching process for removing the aforementioned hard mask 207b will be described in more detail.

High density plasma equipment such as TCP, ICP, DPS or ECR type is used, and the substrate temperature is maintained at 50 ° C to 100 ° C during the etching process, the chamber pressure is maintained at 100mTorr to 1000mTorr, and the source power is 100W to 500W. The bias power is 0W to 30W, respectively. HBr is used from 100SCCM to 300SCCM.

At this time, in order to increase the reproducibility of etching, oxygen (O ₂ ) of 0 SCCM to 5 SCCM may be further added.

Subsequently, wet cleaning is performed using a cleaning solution such as BOE to secure the CD on the bottom of the contact hole and to remove the etching by-products remaining after the SAC and the front surface etching. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrochloric acid having a ratio of 50: 1 to 500: 1.

Subsequently, although not shown in the drawing, the conductive layer for forming the storage node contact plug is deposited on the entire surface of the substrate 200 on which the open portion 209 is formed to sufficiently fill the open portion 209.

Here, the most commonly used material for forming a conductive film for plug formation is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and metal such as tungsten may be used instead of polysilicon.

Subsequently, a CMP or an entire surface etching process may be performed to form a storage node contact plug electrically connected to the cell contact plug 202 through the open portion 209 and planarized thereon, and isolated.

Meanwhile, in the above-described embodiment, the storage node contact plug forming process is taken as an example, but it may be applied to a cell contact plug or a bit line contact plug forming process.

Therefore, in the cell contact plug forming process, the lower cell contact plug will be replaced with an impurity diffusion region of the substrate, and the bit line will be replaced with a gate electrode pattern.

According to the present invention made as described above, a process of high temperature and high pressure in order to minimize the loss of the bottom conductive film at the time of removing the hard mask after the open portion forming process to expose the conductive film containing silicon using a hard mask containing silicon. By inducing the ARDE phenomenon using the HBr plasma under the conditions, it was found through the embodiment that the hard mask is well removed but the consumption of the conductive film under the open part can be minimized.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above, by minimizing the attack of the bottom surface of the open portion when removing the hard mask, there is an effect that can shorten the development period by preventing the failure of the semiconductor device.

1A to 1D are cross-sectional views illustrating a process for forming a contact hole for a storage node according to the prior art.

2A to 2D are cross-sectional views illustrating a process of forming a contact hole for a storage node according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: substrate 201: first interlayer insulating film

202: cell contact plug 203: second interlayer insulating film

204: bit line conductive film 205: bit line hard mask

206: third interlayer insulating film 207b: hard mask

209: open section

Claims (13)

Forming a conductive film comprising silicon on the substrate; Forming an insulating etching layer on the conductive film; Forming a hard mask including the silicon on the etched layer and defining a region to be formed with an open part; Forming an open portion to expose a portion of the conductive layer by etching the etched layer using the hard mask as an etch mask; And Removing the hard mask while performing an entire surface etching using HBr plasma in a high density plasma apparatus to prevent attack on the conductive layer; Semiconductor device manufacturing method comprising a. The method of claim 1, In removing the hard mask, In the equipment of any one type of TCP, ICP, DPS or ECR, the temperature of the substrate is maintained at 50 ° C to 100 ° C, the chamber pressure is maintained at 100mTorr to 1000mTorr, the source power is 100W to 500W, and the bias power is A semiconductor device manufacturing method characterized by using from 0W to 30W. The method according to claim 1 or 2, The method of manufacturing a semiconductor device, characterized in that using the HBr 100SCCM to 300SCCM. The method according to claim 1 or 2, In removing the hard mask, The method of manufacturing a semiconductor device, characterized in that using the plasma further added oxygen of 0SCCM to 5SCCM to the HBr. According to claim 1, The silicon-containing conductive film may include any one of a cell contact plug, a bit line contact plug, and a storage node contact plug. The method of claim 1, The conductive film comprising silicon comprises a gate electrode pattern or a bit line. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that the etched layer includes an oxide film. The method of claim 7, wherein In the etching of the etched layer, A method for manufacturing a semiconductor device, comprising using a self-aligned contact etching process. The method of claim 8, In the etching of the etched layer, The etching profile in which the open portion is formed is aligned along the side of the conductive pattern. The method of claim 9, The conductive pattern includes a bit line. The method according to claim 8 or 9, In the etching of the etched layer, CxFy (x, y is 1 to 10) as a stock corner gas, and a gas for generating a polymer is added thereto, that is, any one of CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ , wherein A method for fabricating a semiconductor device comprising using an inert gas of any one of He, Ne, Ar, or Xe as a carrier gas. The method of claim 1, Forming a hard mask, Depositing a material layer for a hard mask including silicon on the etched layer; Forming a photoresist pattern on the hard mask material layer, the photoresist pattern defining a region to be formed in the open part; Etching the hard mask material layer using the photoresist pattern as an etch mask to form the hard mask; Removing the photoresist pattern. The method of claim 12, In the step of forming the photoresist pattern, using a photolithography process using an exposure source of ArF or F ₂ .