CN112185887B - Manufacturing method of MIM capacitor - Google Patents

Manufacturing method of MIM capacitor Download PDF

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Publication number
CN112185887B
CN112185887B CN202010937668.4A CN202010937668A CN112185887B CN 112185887 B CN112185887 B CN 112185887B CN 202010937668 A CN202010937668 A CN 202010937668A CN 112185887 B CN112185887 B CN 112185887B
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layer
substrate
etching
metal layer
plate metal
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CN112185887A (en
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杨宏旭
刘俊文
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a manufacturing method of an MIM capacitor, and relates to the field of semiconductor manufacturing. The manufacturing method of the MIM capacitor comprises the steps of forming an alignment mark; forming an oxide layer on the substrate; forming a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer above the oxide layer in sequence; etching the upper pole plate metal layer, the dielectric layer and the lower pole plate metal layer to form the MIM capacitor; the problem that the peeling phenomenon is easy to occur at the edge of the substrate in the manufacturing process of the current MIM capacitor is solved; the method achieves the effect of reducing the risk of peeling off the edge of the substrate under the condition of not increasing the production cost.

Description

Manufacturing method of MIM capacitor
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an MIM capacitor.
Background
Capacitors are one of the commonly used passive devices and are widely used in various chips. Capacitors in semiconductor devices include MIM (metal insulator metal) capacitors, PIP (poly-insulator-poly) capacitors, MOM (metal oxide metal) capacitors, etc., wherein PIP capacitors are widely used because of their relatively simple fabrication.
The MIM capacitor comprises a lower plate, an upper plate and a dielectric layer positioned between the upper plate and the lower plate, and can be manufactured in the BEOL (Back End of Line) processing process. In the manufacturing of the MIM capacitor, after an alignment mark is formed on a substrate through photoetching and etching processes, photoresist trimming needs to be carried out on the substrate, and then an upper plate metal layer, a dielectric layer and a lower plate metal layer which form the MIM capacitor are deposited on the substrate.
However, after the photoresist edge removal process, the stacked thin film structure in the edge region of the substrate changes, and after the upper plate metal layer, the dielectric layer, and the lower plate metal layer that form the MIM capacitor are deposited, the unreasonable thin film stacked structure causes excessive stress, which may cause peeling risk in the edge region.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method of manufacturing a MIM capacitor. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing an MIM capacitor, where the method includes:
forming an alignment mark on the substrate;
forming an oxide layer on the substrate;
forming a lower pole plate metal layer, a dielectric layer and an upper pole plate metal layer above the oxide layer in sequence;
and etching the upper pole plate metal layer, the dielectric layer and the upper pole plate metal layer to form the MIM capacitor.
Optionally, forming an alignment mark on the substrate includes:
defining an alignment mark pattern through a photoetching process;
and etching the nitrogen-doped silicon carbide layer and the metal interconnection layer by an etching process to form the alignment mark.
Optionally, in the process of forming the alignment mark, the substrate is subjected to photoresist edge removal processing.
Optionally, the photoresist at the edge region of the substrate is removed by a photoresist edge removal process.
Optionally, the lower plate metal layer is made of tantalum nitride, and the upper plate metal layer is made of tantalum nitride.
Optionally, the dielectric layer is made of silicon nitride or silicon dioxide.
Optionally, before forming the alignment mark on the substrate, the method further includes:
depositing a low-k metal material to form a metal interconnection layer;
a nitrogen doped silicon carbide layer is formed over the metal interconnect layer.
Optionally, the etching the upper plate metal layer, the dielectric layer, and the lower plate metal layer to form an MIM capacitor includes:
defining an upper polar plate pattern through a photoetching process;
etching the upper pole plate metal layer through an etching process to form an upper pole plate;
etching the dielectric layer by taking the upper polar plate as a mask;
and etching the lower pole plate metal layer to form a lower pole plate.
The technical scheme at least comprises the following advantages:
forming an alignment mark on the substrate, forming an oxide layer on the substrate, sequentially forming a lower plate metal layer, a dielectric layer and an upper plate metal layer above the oxide layer, and etching the upper plate metal layer, the dielectric layer and the lower plate metal layer to form the MIM capacitor; the problem that the peeling phenomenon is easy to occur at the edge of the substrate in the manufacturing process of the current MIM capacitor is solved; the method achieves the effect of reducing the risk of peeling off the edge of the substrate under the condition of not increasing the production cost.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart illustrating a method for fabricating an MIM capacitor according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an alignment mark provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of a thin film stack in the edge area of a substrate provided by an embodiment of the present application;
fig. 4 is a schematic diagram of a thin film stack in an area beyond an edge area of a substrate according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for manufacturing a MIM capacitor according to an embodiment of the present application is shown, the method including at least the following steps:
step 101, forming an alignment mark on a substrate.
A metal interconnection layer in a metal interconnection structure and an NDC (Nitride Doped Silicon Carbide) layer are formed on the substrate. In order to facilitate alignment operation in subsequent processes, an alignment mark needs to be formed on the substrate.
And etching the NDC layer and the metal interconnection layer through an etching process to form an alignment mark.
Before etching to form the alignment mark, an alignment mark pattern needs to be defined on the substrate through a photolithography process. In the photolithography process, in order to avoid the photoresist on the edge of the substrate from affecting the patterns of other parts, the photoresist edge needs to be repaired, and after the photoresist edge is repaired, the photoresist on the edge area of the substrate is removed. In the etching process of the alignment mark, the NDC of the edge area of the substrate is etched and removed because the edge area of the substrate is not provided with the photoresist.
The edge region of the substrate refers to a region inward from the edge of the substrate by a predetermined distance, which is determined according to actual conditions. For example, the diameter of the substrate is 300mm, and the edge area of the substrate is 0-3 mm inward of the edge of the substrate.
As shown in fig. 2, an alignment mark 23 is formed in a region within the substrate edge region, and the alignment mark 23 is formed in the NDC layer 22 and the metal interconnection layer 21. And at the edge region of the substrate, the NDC and the photoresist above the metal interconnect layer are removed.
Step 102, an oxide layer is formed on a substrate.
An oxide layer is formed on the surface of the substrate in both the edge region and the region within the edge region.
In the edge area of the substrate, the oxide layer is positioned above the metal interconnection layer; the oxide layer is located over the NDC layer in a region within the edge region of the substrate.
And 103, forming a lower plate metal layer, a dielectric layer and an upper plate metal layer above the oxide layer in sequence.
The dielectric layer is non-conductive.
As shown in fig. 3, in the edge region of the substrate, an oxide layer 24, a lower plate metal layer 31, a dielectric layer 32, and an upper plate metal layer 33 are sequentially disposed above the metal interconnection layer 21; as shown in fig. 4, in the region within the edge region of the substrate, the NDC layer 22, the oxide layer 24, the lower plate metal layer 31, the dielectric layer 32, and the upper plate metal layer 33 are sequentially disposed above the metal interconnection layer 21.
The oxide layer in the edge area of the substrate serves as a buffer layer, after a lower pole plate metal layer, a dielectric layer and an upper pole plate metal layer are formed, the film stacking condition in the edge area is changed, the MIM stacking stress is reduced, and the stripping phenomenon in the edge area is avoided.
And 104, etching the upper plate metal layer, the dielectric layer and the lower plate metal layer to form the MIM capacitor.
And etching the upper plate metal layer according to the design pattern of the MIM capacitor to form an upper plate, sequentially etching the dielectric layer and the lower plate metal layer, and covering the dielectric layer on the upper plate after etching.
It should be noted that the lower plate metal layer is etched or not etched according to the design requirement of the MIM capacitor.
In summary, in the manufacturing method of the MIM capacitor provided in the embodiment of the present application, the alignment mark is formed on the substrate, the oxide layer is formed on the substrate, the lower plate metal layer, the dielectric layer, and the upper plate metal layer are sequentially formed above the oxide layer, and the upper plate metal layer, the dielectric layer, and the lower plate metal layer are etched to form the MIM capacitor; the problem that the edge of a substrate is easy to peel off in the manufacturing process of the MIM capacitor at present is solved; the method achieves the effect of reducing the risk of peeling off the edge of the substrate under the condition of not increasing the production cost.
Another embodiment of the present application provides a method for manufacturing a MIM capacitor, the method at least including the following steps:
step 201, depositing a low-k metal material to form a metal interconnection layer.
In the process of forming the metal interconnection structure, a metal interconnection layer is formed.
In one example, the material of the metal interconnect layer is copper.
In step 202, a nitrogen doped silicon carbide layer is formed over the metal layer.
Depositing NDC above the metal interconnection layer to form an NDC layer; the edge of the substrate and the area within the edge of the substrate are both formed with a layer of NDC. NDC acts as a metal barrier.
In step 203, an alignment mark pattern is defined by a photolithography process.
Photoresist is spin-coated on a substrate, and exposure is performed using a mask plate with an alignment mark pattern.
And in the process of forming the alignment mark, carrying out photoresist edge removal treatment on the substrate. Because the excess photoresist can be gathered at the edge of the substrate in the photoresist spin coating process, in order to avoid the photoresist gathered at the edge from affecting other patterns or polluting the back of the wafer, a chemical method (chemical EBR) and/or an optical method (optical EBR, also called WEE) is used for removing the photoresist at the edge of the substrate.
After the photolithography process is completed, an alignment mark pattern is formed in the photoresist layer on the surface of the substrate.
And step 204, etching the nitrogen-doped silicon carbide layer and the metal interconnection layer through an etching process to form an alignment mark.
And etching the NDC layer corresponding to the alignment mark pattern by an etching process, and then etching the metal interconnection layer corresponding to the alignment mark pattern, wherein the metal interconnection layer corresponding to the alignment mark pattern is not completely removed by etching, so as to form the alignment mark. Since the photoresist in the edge region of the substrate is removed, the NDC in the edge region of the substrate is also removed during the etching of the alignment mark since it is not protected by the photoresist.
In one example, the alignment marks are formed as shown in FIG. 2.
In step 205, an oxide layer is formed on the substrate.
This step is explained in step 102 above and will not be described here.
And step 206, forming a lower plate metal layer, a dielectric layer and an upper plate metal layer on the oxide layer in sequence.
Optionally, the lower plate metal layer is made of tantalum nitride (TaN), and the upper plate metal layer is made of tantalum nitride (TaN).
Optionally, the dielectric layer is made of silicon nitride or silicon dioxide.
In step 207, a top plate pattern is defined by a photolithography process.
And 208, etching the upper plate metal layer through an etching process to form an upper plate.
And 209, etching the dielectric layer by taking the upper polar plate as a mask.
The upper polar plate covers the etched dielectric layer.
And step 210, etching the lower plate metal layer to form a lower plate.
The lower polar plate is covered by the etched dielectric layer.
The upper electrode plate, the etched dielectric layer and the lower electrode plate form an MIM capacitor.
By changing the technological process for manufacturing the MIM capacitor, the photoetching process of the alignment mark can be not adjusted, the film stacking of the edge area of the substrate is changed, the oxide layer is reserved in the edge area to be used as a buffer layer, the stacking stress is improved, and the effect of reducing the peeling risk of the film at the edge of the substrate is realized.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. A method of fabricating a MIM capacitor, the method comprising:
sequentially forming a metal interconnection layer and a nitrogen-doped silicon carbide layer on a substrate;
forming alignment marks in the nitrogen-doped silicon carbide layer and the metal interconnection layer, and removing the nitrogen-doped silicon carbide layer in the edge area of the substrate;
forming an oxide layer on the nitrogen-doped silicon carbide layer and the metal interconnection layer in the edge region of the substrate;
forming a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer above the oxide layer in sequence;
and etching the upper pole plate metal layer, the dielectric layer and the lower pole plate metal layer to form the MIM capacitor.
2. The method of claim 1, wherein forming the alignment mark on the substrate comprises:
defining an alignment mark pattern through a photoetching process;
and etching the nitrogen-doped silicon carbide layer and the metal interconnection layer by an etching process to form the alignment mark.
3. The method according to claim 1 or 2, wherein the substrate is subjected to a photoresist edge removal process during the formation of the alignment mark.
4. A method as claimed in claim 3, characterized in that the photoresist is removed in the edge area of the substrate by a photoresist trimming process.
5. The method of claim 1, wherein the lower plate metal layer is made of tantalum nitride and the upper plate metal layer is made of tantalum nitride.
6. The method of claim 1, wherein the dielectric layer is made of silicon nitride or silicon dioxide.
7. The method of claim 1 or 2, wherein prior to forming the alignment mark on the substrate, the method further comprises:
depositing a low-k metal material to form a metal interconnection layer;
a nitrogen doped silicon carbide layer is formed over the metal interconnect layer.
8. The method of claim 1, wherein the etching the top plate metal layer, the dielectric layer, and the bottom plate metal layer to form the MIM capacitor comprises:
defining an upper polar plate pattern through a photoetching process;
etching the upper pole plate metal layer through an etching process to form an upper pole plate;
etching the dielectric layer by taking the upper polar plate as a mask;
and etching the lower pole plate metal layer to form a lower pole plate.
CN202010937668.4A 2020-09-08 2020-09-08 Manufacturing method of MIM capacitor Active CN112185887B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876371A (en) * 2017-01-04 2017-06-20 上海华虹宏力半导体制造有限公司 The manufacture method of MIM capacitor
CN111627812A (en) * 2020-06-28 2020-09-04 华虹半导体(无锡)有限公司 Etching method applied to MIM capacitor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876371A (en) * 2017-01-04 2017-06-20 上海华虹宏力半导体制造有限公司 The manufacture method of MIM capacitor
CN111627812A (en) * 2020-06-28 2020-09-04 华虹半导体(无锡)有限公司 Etching method applied to MIM capacitor

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